439 lines
9.8 KiB
Systemverilog
439 lines
9.8 KiB
Systemverilog
`ifndef VX_CONFIG
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`define VX_CONFIG
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`ifndef NUM_CLUSTERS
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`define NUM_CLUSTERS 1
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`endif
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`ifndef NUM_CORES
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`define NUM_CORES 1
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`endif
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`ifndef NUM_WARPS
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`define NUM_WARPS 4
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`endif
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`ifndef NUM_THREADS
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`define NUM_THREADS 4
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`endif
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`ifndef NUM_BARRIERS
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`define NUM_BARRIERS 4
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`endif
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`ifndef L2_ENABLE
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`define L2_ENABLE 0
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`endif
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`ifndef L3_ENABLE
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`define L3_ENABLE 0
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`endif
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`ifndef SM_ENABLE
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`define SM_ENABLE 1
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`endif
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`ifndef MEM_BLOCK_SIZE
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`define MEM_BLOCK_SIZE 64
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`endif
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`ifndef L1_BLOCK_SIZE
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`define L1_BLOCK_SIZE (`NUM_THREADS * 4)
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`endif
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`ifndef STARTUP_ADDR
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`define STARTUP_ADDR 32'h80000000
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`endif
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`ifndef IO_BASE_ADDR
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`define IO_BASE_ADDR 32'hFF000000
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`endif
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`ifndef IO_ADDR_SIZE
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`define IO_ADDR_SIZE (32'hFFFFFFFF - `IO_BASE_ADDR + 1)
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`endif
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`ifndef IO_COUT_ADDR
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`define IO_COUT_ADDR (32'hFFFFFFFF - `MEM_BLOCK_SIZE + 1)
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`endif
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`ifndef IO_COUT_SIZE
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`define IO_COUT_SIZE `MEM_BLOCK_SIZE
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`endif
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`ifndef IO_CSR_ADDR
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`define IO_CSR_ADDR `IO_BASE_ADDR
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`endif
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`ifndef SMEM_BASE_ADDR
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`define SMEM_BASE_ADDR `IO_BASE_ADDR
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`endif
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`ifndef EXT_M_DISABLE
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`define EXT_M_ENABLE
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`endif
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`ifndef EXT_F_DISABLE
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`define EXT_F_ENABLE
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`endif
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`ifndef EXT_TEX_DISABLE
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`define EXT_TEX_ENABLE
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`endif
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// Device identification
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`define VENDOR_ID 0
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`define ARCHITECTURE_ID 0
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`define IMPLEMENTATION_ID 0
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///////////////////////////////////////////////////////////////////////////////
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`ifndef LATENCY_IMUL
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`define LATENCY_IMUL 3
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`endif
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`ifndef LATENCY_FNCP
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`define LATENCY_FNCP 2
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`endif
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`ifndef LATENCY_FMA
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`define LATENCY_FMA 4
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`endif
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`ifndef LATENCY_FDIV
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`ifdef ALTERA_S10
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`define LATENCY_FDIV 34
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`else
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`define LATENCY_FDIV 15
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`endif
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`endif
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`ifndef LATENCY_FSQRT
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`ifdef ALTERA_S10
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`define LATENCY_FSQRT 25
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`else
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`define LATENCY_FSQRT 10
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`endif
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`endif
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`ifndef LATENCY_FDIVSQRT
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`define LATENCY_FDIVSQRT 32
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`endif
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`ifndef LATENCY_FCVT
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`define LATENCY_FCVT 5
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`endif
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`define RESET_DELAY 6
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// CSR Addresses //////////////////////////////////////////////////////////////
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// User Floating-Point CSRs
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`define CSR_FFLAGS 12'h001
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`define CSR_FRM 12'h002
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`define CSR_FCSR 12'h003
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`define CSR_SATP 12'h180
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`define CSR_PMPCFG0 12'h3A0
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`define CSR_PMPADDR0 12'h3B0
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`define CSR_MSTATUS 12'h300
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`define CSR_MISA 12'h301
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`define CSR_MEDELEG 12'h302
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`define CSR_MIDELEG 12'h303
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`define CSR_MIE 12'h304
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`define CSR_MTVEC 12'h305
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`define CSR_MEPC 12'h341
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// Machine Performance-monitoring counters
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`define CSR_MPM_BASE 12'hB00
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`define CSR_MPM_BASE_H 12'hB80
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// PERF: pipeline
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`define CSR_MCYCLE 12'hB00
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`define CSR_MCYCLE_H 12'hB80
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`define CSR_MPM_RESERVED 12'hB01
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`define CSR_MPM_RESERVED_H 12'hB81
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`define CSR_MINSTRET 12'hB02
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`define CSR_MINSTRET_H 12'hB82
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`define CSR_MPM_IBUF_ST 12'hB03
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`define CSR_MPM_IBUF_ST_H 12'hB83
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`define CSR_MPM_SCRB_ST 12'hB04
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`define CSR_MPM_SCRB_ST_H 12'hB84
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`define CSR_MPM_ALU_ST 12'hB05
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`define CSR_MPM_ALU_ST_H 12'hB85
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`define CSR_MPM_LSU_ST 12'hB06
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`define CSR_MPM_LSU_ST_H 12'hB86
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`define CSR_MPM_CSR_ST 12'hB07
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`define CSR_MPM_CSR_ST_H 12'hB87
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`define CSR_MPM_FPU_ST 12'hB08
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`define CSR_MPM_FPU_ST_H 12'hB88
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`define CSR_MPM_GPU_ST 12'hB09
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`define CSR_MPM_GPU_ST_H 12'hB89
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// PERF: icache
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`define CSR_MPM_ICACHE_READS 12'hB0A // total reads
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`define CSR_MPM_ICACHE_READS_H 12'hB8A
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`define CSR_MPM_ICACHE_MISS_R 12'hB0B // total misses
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`define CSR_MPM_ICACHE_MISS_R_H 12'hB8B
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`define CSR_MPM_ICACHE_PIPE_ST 12'hB0C // pipeline stalls
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`define CSR_MPM_ICACHE_PIPE_ST_H 12'hB8C
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`define CSR_MPM_ICACHE_CRSP_ST 12'hB0D // core response stalls
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`define CSR_MPM_ICACHE_CRSP_ST_H 12'hB8D
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// PERF: dcache
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`define CSR_MPM_DCACHE_READS 12'hB0E // total reads
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`define CSR_MPM_DCACHE_READS_H 12'hB8E
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`define CSR_MPM_DCACHE_WRITES 12'hB0F // total writes
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`define CSR_MPM_DCACHE_WRITES_H 12'hB8F
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`define CSR_MPM_DCACHE_MISS_R 12'hB10 // read misses
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`define CSR_MPM_DCACHE_MISS_R_H 12'hB90
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`define CSR_MPM_DCACHE_MISS_W 12'hB11 // write misses
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`define CSR_MPM_DCACHE_MISS_W_H 12'hB91
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`define CSR_MPM_DCACHE_BANK_ST 12'hB12 // bank conflicts stalls
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`define CSR_MPM_DCACHE_BANK_ST_H 12'hB92
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`define CSR_MPM_DCACHE_MSHR_ST 12'hB13 // MSHR stalls
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`define CSR_MPM_DCACHE_MSHR_ST_H 12'hB93
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`define CSR_MPM_DCACHE_PIPE_ST 12'hB14 // pipeline stalls
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`define CSR_MPM_DCACHE_PIPE_ST_H 12'hB94
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`define CSR_MPM_DCACHE_CRSP_ST 12'hB15 // core response stalls
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`define CSR_MPM_DCACHE_CRSP_ST_H 12'hB95
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// PERF: smem
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`define CSR_MPM_SMEM_READS 12'hB16 // total reads
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`define CSR_MPM_SMEM_READS_H 12'hB96
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`define CSR_MPM_SMEM_WRITES 12'hB17 // total writes
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`define CSR_MPM_SMEM_WRITES_H 12'hB97
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`define CSR_MPM_SMEM_BANK_ST 12'hB18 // bank conflicts stalls
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`define CSR_MPM_SMEM_BANK_ST_H 12'hB98
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// PERF: memory
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`define CSR_MPM_MEM_READS 12'hB19 // memory reads
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`define CSR_MPM_MEM_READS_H 12'hB99
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`define CSR_MPM_MEM_WRITES 12'hB1A // memory writes
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`define CSR_MPM_MEM_WRITES_H 12'hB9A
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`define CSR_MPM_MEM_ST 12'hB1B // memory request stalls
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`define CSR_MPM_MEM_ST_H 12'hB9B
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`define CSR_MPM_MEM_LAT 12'hB1C // memory latency (total)
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`define CSR_MPM_MEM_LAT_H 12'hB9C
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// Machine Information Registers
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`define CSR_MVENDORID 12'hF11
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`define CSR_MARCHID 12'hF12
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`define CSR_MIMPID 12'hF13
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`define CSR_MHARTID 12'hF14
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// User SIMT CSRs
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`define CSR_WTID 12'hCC0
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`define CSR_LTID 12'hCC1
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`define CSR_GTID 12'hCC2
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`define CSR_LWID 12'hCC3
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`define CSR_GWID `CSR_MHARTID
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`define CSR_GCID 12'hCC5
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// Machine SIMT CSRs
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`define CSR_NT 12'hFC0
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`define CSR_NW 12'hFC1
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`define CSR_NC 12'hFC2
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////////// Texture Units //////////////////////////////////////////////////////
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`define NUM_TEX_UNITS 2
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`define CSR_TEX_STATES 7
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`define CSR_TEX_BEGIN(x) (12'hFD0 + (x) * `CSR_TEX_STATES)
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`define CSR_TEX_ADDR(x) (`CSR_TEX_BEGIN(x) + 12'h00)
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`define CSR_TEX_FORMAT(x) (`CSR_TEX_BEGIN(x) + 12'h01)
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`define CSR_TEX_WRAP(x) (`CSR_TEX_BEGIN(x) + 12'h02)
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`define CSR_TEX_FILTER(x) (`CSR_TEX_BEGIN(x) + 12'h03)
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`define CSR_TEX_MIPOFF(x) (`CSR_TEX_BEGIN(x) + 12'h04)
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`define CSR_TEX_WIDTH(x) (`CSR_TEX_BEGIN(x) + 12'h05)
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`define CSR_TEX_HEIGHT(x) (`CSR_TEX_BEGIN(x) + 12'h06)
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// Pipeline Queues ////////////////////////////////////////////////////////////
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// Size of LSU Request Queue
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`ifndef LSUQ_SIZE
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`define LSUQ_SIZE (`NUM_WARPS * 2)
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`endif
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// Size of FPU Request Queue
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`ifndef FPUQ_SIZE
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`define FPUQ_SIZE 8
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`endif
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// Icache Configurable Knobs //////////////////////////////////////////////////
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// Size of cache in bytes
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`ifndef ICACHE_SIZE
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`define ICACHE_SIZE 16384
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`endif
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// Core Request Queue Size
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`ifndef ICREQ_SIZE
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`define ICREQ_SIZE 0
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`endif
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// Core Response Queue Size
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`ifndef ICRSQ_SIZE
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`define ICRSQ_SIZE 2
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`endif
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// Miss Handling Register Size
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`ifndef IMSHR_SIZE
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`define IMSHR_SIZE `NUM_WARPS
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`endif
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// Memory Request Queue Size
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`ifndef IMREQ_SIZE
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`define IMREQ_SIZE 4
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`endif
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// Memory Response Queue Size
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`ifndef IMRSQ_SIZE
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`define IMRSQ_SIZE 0
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`endif
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// Dcache Configurable Knobs //////////////////////////////////////////////////
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// Size of cache in bytes
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`ifndef DCACHE_SIZE
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`define DCACHE_SIZE 16384
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`endif
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// Number of banks
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`ifndef DNUM_BANKS
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`define DNUM_BANKS `NUM_THREADS
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`endif
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// Number of bank ports
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`ifndef DNUM_PORTS
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`define DNUM_PORTS 1
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`endif
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// Core Request Queue Size
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`ifndef DCREQ_SIZE
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`define DCREQ_SIZE 0
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`endif
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// Core Response Queue Size
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`ifndef DCRSQ_SIZE
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`define DCRSQ_SIZE 2
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`endif
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// Miss Handling Register Size
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`ifndef DMSHR_SIZE
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`define DMSHR_SIZE `LSUQ_SIZE
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`endif
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// Memory Request Queue Size
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`ifndef DMREQ_SIZE
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`define DMREQ_SIZE 4
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`endif
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// Memory Response Queue Size
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`ifndef DMRSQ_SIZE
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`define DMRSQ_SIZE 0
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`endif
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// SM Configurable Knobs //////////////////////////////////////////////////////
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// per thread stack size
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`ifndef STACK_SIZE
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`define STACK_SIZE 1024
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`endif
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// Size of cache in bytes
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`ifndef SMEM_SIZE
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`define SMEM_SIZE (`STACK_SIZE * `NUM_WARPS * `NUM_THREADS)
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`endif
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// Number of banks
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`ifndef SNUM_BANKS
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`define SNUM_BANKS `NUM_THREADS
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`endif
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// Core Request Queue Size
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`ifndef SCREQ_SIZE
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`define SCREQ_SIZE 2
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`endif
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// Core Response Queue Size
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`ifndef SCRSQ_SIZE
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`define SCRSQ_SIZE 2
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`endif
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// L2cache Configurable Knobs /////////////////////////////////////////////////
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// Size of cache in bytes
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`ifndef L2CACHE_SIZE
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`define L2CACHE_SIZE 131072
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`endif
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// Number of banks
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`ifndef L2NUM_BANKS
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`define L2NUM_BANKS `MIN(`NUM_CORES, 4)
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`endif
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// Core Request Queue Size
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`ifndef L2CREQ_SIZE
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`define L2CREQ_SIZE 0
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`endif
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// Core Response Queue Size
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`ifndef L2CRSQ_SIZE
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`define L2CRSQ_SIZE 2
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`endif
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// Miss Handling Register Size
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`ifndef L2MSHR_SIZE
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`define L2MSHR_SIZE 16
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`endif
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// Memory Request Queue Size
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`ifndef L2MREQ_SIZE
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`define L2MREQ_SIZE 4
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`endif
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// Memory Response Queue Size
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`ifndef L2MRSQ_SIZE
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`define L2MRSQ_SIZE 0
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`endif
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// L3cache Configurable Knobs /////////////////////////////////////////////////
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// Size of cache in bytes
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`ifndef L3CACHE_SIZE
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`define L3CACHE_SIZE 1048576
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`endif
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// Number of banks
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`ifndef L3NUM_BANKS
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`define L3NUM_BANKS `MIN(`NUM_CLUSTERS, 4)
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`endif
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// Core Request Queue Size
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`ifndef L3CREQ_SIZE
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`define L3CREQ_SIZE 0
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`endif
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// Core Response Queue Size
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`ifndef L3CRSQ_SIZE
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`define L3CRSQ_SIZE 2
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`endif
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// Miss Handling Register Size
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`ifndef L3MSHR_SIZE
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`define L3MSHR_SIZE 16
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`endif
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// Memory Request Queue Size
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`ifndef L3MREQ_SIZE
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`define L3MREQ_SIZE 4
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`endif
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// Memory Response Queue Size
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`ifndef L3MRSQ_SIZE
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`define L3MRSQ_SIZE 0
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`endif
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`endif
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