141 lines
5.9 KiB
Verilog
141 lines
5.9 KiB
Verilog
`include "VX_define.vh"
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module VX_instr_demux (
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input wire clk,
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input wire reset,
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// inputs
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VX_ibuffer_if ibuffer_if,
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VX_gpr_rsp_if gpr_rsp_if,
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// outputs
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VX_alu_req_if alu_req_if,
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VX_lsu_req_if lsu_req_if,
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VX_csr_req_if csr_req_if,
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VX_fpu_req_if fpu_req_if,
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VX_gpu_req_if gpu_req_if
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);
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wire [`NT_BITS-1:0] tid;
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wire alu_req_ready;
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wire lsu_req_ready;
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wire csr_req_ready;
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wire fpu_req_ready;
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wire gpu_req_ready;
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VX_priority_encoder #(
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.N (`NUM_THREADS)
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) tid_select (
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.data_in (ibuffer_if.tmask),
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.index (tid),
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`UNUSED_PIN (onehot),
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`UNUSED_PIN (valid_out)
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);
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wire [31:0] next_PC = ibuffer_if.PC + 4;
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// ALU unit
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wire alu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_ALU);
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VX_skid_buffer #(
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `ALU_BITS + `MOD_BITS + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32))
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) alu_buffer (
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.clk (clk),
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.reset (reset),
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.valid_in (alu_req_valid),
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.ready_in (alu_req_ready),
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.data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, next_PC, `ALU_OP(ibuffer_if.op_type), ibuffer_if.op_mod, ibuffer_if.imm, ibuffer_if.use_PC, ibuffer_if.use_imm, ibuffer_if.rd, ibuffer_if.wb, tid, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}),
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.data_out ({alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.next_PC, alu_req_if.op_type, alu_req_if.op_mod, alu_req_if.imm, alu_req_if.use_PC, alu_req_if.use_imm, alu_req_if.rd, alu_req_if.wb, alu_req_if.tid, alu_req_if.rs1_data, alu_req_if.rs2_data}),
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.valid_out (alu_req_if.valid),
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.ready_out (alu_req_if.ready)
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);
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// lsu unit
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wire lsu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_LSU);
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wire lsu_is_fence = `LSU_IS_FENCE(ibuffer_if.op_mod);
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VX_skid_buffer #(
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + `LSU_BITS + 1 + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32))
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) lsu_buffer (
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.clk (clk),
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.reset (reset),
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.valid_in (lsu_req_valid),
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.ready_in (lsu_req_ready),
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.data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, `LSU_OP(ibuffer_if.op_type), lsu_is_fence, ibuffer_if.imm, ibuffer_if.rd, ibuffer_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}),
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.data_out ({lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.op_type, lsu_req_if.is_fence, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data}),
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.valid_out (lsu_req_if.valid),
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.ready_out (lsu_req_if.ready)
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);
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// csr unit
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wire csr_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_CSR);
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VX_skid_buffer #(
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + `CSR_BITS + `CSR_ADDR_BITS + `NR_BITS + 1 + 1 + `NR_BITS + 32)
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) csr_buffer (
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.clk (clk),
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.reset (reset),
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.valid_in (csr_req_valid),
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.ready_in (csr_req_ready),
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.data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, `CSR_OP(ibuffer_if.op_type), ibuffer_if.imm[`CSR_ADDR_BITS-1:0], ibuffer_if.rd, ibuffer_if.wb, ibuffer_if.use_imm, ibuffer_if.rs1, gpr_rsp_if.rs1_data[0]}),
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.data_out ({csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.op_type, csr_req_if.addr, csr_req_if.rd, csr_req_if.wb, csr_req_if.use_imm, csr_req_if.rs1, csr_req_if.rs1_data}),
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.valid_out (csr_req_if.valid),
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.ready_out (csr_req_if.ready)
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);
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// fpu unit
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`ifdef EXT_F_ENABLE
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wire fpu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_FPU);
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VX_skid_buffer #(
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + `FPU_BITS + `MOD_BITS + `NR_BITS + 1 + (3 * `NUM_THREADS * 32))
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) fpu_buffer (
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.clk (clk),
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.reset (reset),
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.valid_in (fpu_req_valid),
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.ready_in (fpu_req_ready),
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.data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, `FPU_OP(ibuffer_if.op_type), ibuffer_if.op_mod, ibuffer_if.rd, ibuffer_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data, gpr_rsp_if.rs3_data}),
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.data_out ({fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.op_type, fpu_req_if.op_mod, fpu_req_if.rd, fpu_req_if.wb, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data}),
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.valid_out (fpu_req_if.valid),
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.ready_out (fpu_req_if.ready)
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);
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`else
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`UNUSED_VAR (gpr_rsp_if.rs3_data)
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assign fpu_req_ready = 0;
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`endif
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// gpu unit
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wire gpu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_GPU);
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VX_skid_buffer #(
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `GPU_BITS + `MOD_BITS + `NR_BITS + 1 + (3 * `NUM_THREADS * 32)) //update number of bits
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) gpu_buffer (
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.clk (clk),
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.reset (reset),
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.valid_in (gpu_req_valid),
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.ready_in (gpu_req_ready),
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.data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, next_PC, `GPU_OP(ibuffer_if.op_type), ibuffer_if.op_mod, ibuffer_if.rd, ibuffer_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data, gpr_rsp_if.rs3_data}),
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.data_out ({gpu_req_if.wid, gpu_req_if.tmask, gpu_req_if.PC, gpu_req_if.next_PC, gpu_req_if.op_type, gpu_req_if.op_mod, gpu_req_if.rd, gpu_req_if.wb, gpu_req_if.rs1_data, gpu_req_if.rs2_data, gpu_req_if.rs3_data}),
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.valid_out (gpu_req_if.valid),
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.ready_out (gpu_req_if.ready)
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);
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// can take next request?
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reg ready_r;
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always @(*) begin
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case (ibuffer_if.ex_type)
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`EX_ALU: ready_r = alu_req_ready;
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`EX_LSU: ready_r = lsu_req_ready;
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`EX_CSR: ready_r = csr_req_ready;
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`EX_FPU: ready_r = fpu_req_ready;
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`EX_GPU: ready_r = gpu_req_ready;
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default: ready_r = 1'b1; // ignore NOPs
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endcase
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end
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assign ibuffer_if.ready = ready_r;
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endmodule |