Hansung Kim bc45c40231 tensor: Rename half.hpp -> half.h ...

addResource() thinks it's a Verilog source file if it ends in .hpp, for
some reason.

2024-05-02 16:17:20 -07:00

..

dpi

tensor: Rename half.hpp -> half.h

2024-05-02 16:17:20 -07:00

rtl

Wrap hardcoded configs with SYNTHESIS

2024-05-02 16:17:04 -07:00

scripts

Vortex 2.0 changes:

2023-11-10 02:47:05 -08:00

syn

- using SV_DPI defines to disable DPI in synthesis-based simulations

2024-01-28 00:22:21 -08:00

unittest

test case update

2024-03-28 13:04:02 -07:00

.gitignore

Vortex 2.0 changes:

2023-11-10 02:47:05 -08:00

Makefile

Vortex 2.0 changes:

2023-11-10 02:47:05 -08:00

VX_config.h

round robin warp scheduling

2024-04-16 23:03:00 -07:00