c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
245 lines
8.3 KiB
Systemverilog
245 lines
8.3 KiB
Systemverilog
// Date: 02/2/2016
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// Compliant with CCI-P spec v0.71
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package ccip_if_pkg;
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//=====================================================================
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// CCI-P interface defines
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//=====================================================================
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parameter CCIP_VERSION_NUMBER = 12'h071;
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parameter CCIP_CLADDR_WIDTH = 42;
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parameter CCIP_CLDATA_WIDTH = 512;
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parameter CCIP_MMIOADDR_WIDTH = 16;
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parameter CCIP_MMIODATA_WIDTH = 64;
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parameter CCIP_TID_WIDTH = 9;
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parameter CCIP_MDATA_WIDTH = 16;
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// Number of requests that can be accepted after almost full is asserted.
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parameter CCIP_TX_ALMOST_FULL_THRESHOLD = 8;
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parameter CCIP_MMIO_RD_TIMEOUT = 512;
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parameter CCIP_SYNC_RESET_POLARITY=1; // Active High Reset
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// Base types
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//----------------------------------------------------------------------
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typedef logic [CCIP_CLADDR_WIDTH-1:0] t_ccip_clAddr;
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typedef logic [CCIP_CLDATA_WIDTH-1:0] t_ccip_clData;
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typedef logic [CCIP_MMIOADDR_WIDTH-1:0] t_ccip_mmioAddr;
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typedef logic [CCIP_MMIODATA_WIDTH-1:0] t_ccip_mmioData;
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typedef logic [CCIP_TID_WIDTH-1:0] t_ccip_tid;
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typedef logic [CCIP_MDATA_WIDTH-1:0] t_ccip_mdata;
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typedef logic [1:0] t_ccip_clNum;
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typedef logic [2:0] t_ccip_qwIdx;
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// Request Type Encodings
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//----------------------------------------------------------------------
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// Channel 0
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typedef enum logic [3:0] {
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eREQ_RDLINE_I = 4'h0, // Memory Read with FPGA Cache Hint=Invalid
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eREQ_RDLINE_S = 4'h1 // Memory Read with FPGA Cache Hint=Shared
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} t_ccip_c0_req;
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// Channel 1
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typedef enum logic [3:0] {
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eREQ_WRLINE_I = 4'h0, // Memory Write with FPGA Cache Hint=Invalid
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eREQ_WRLINE_M = 4'h1, // Memory Write with FPGA Cache Hint=Modified
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eREQ_WRPUSH_I = 4'h2, // Memory Write with DDIO Hint ** NOT SUPPORTED CURRENTLY **
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eREQ_WRFENCE = 4'h4, // Memory Write Fence
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// eREQ_ATOMIC = 4'h5, // Atomic operation: Compare-Exchange for Memory Addr ** NOT SUPPORTED CURRENTELY **
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eREQ_INTR = 4'h6 // Interrupt the CPU ** NOT SUPPORTED CURRENTLY **
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} t_ccip_c1_req;
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// Response Type Encodings
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//----------------------------------------------------------------------
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// Channel 0
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typedef enum logic [3:0] {
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eRSP_RDLINE = 4'h0, // Memory Read
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eRSP_UMSG = 4'h4 // UMsg received
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// eRSP_ATOMIC = 4'h5 // Atomic Operation: Compare-Exchange for Memory Addr
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} t_ccip_c0_rsp;
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// Channel 1
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typedef enum logic [3:0] {
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eRSP_WRLINE = 4'h0, // Memory Write
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eRSP_WRFENCE = 4'h4, // Memory Write Fence
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eRSP_INTR = 4'h6 // Interrupt delivered to the CPU ** NOT SUPPORTED CURRENTLY **
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} t_ccip_c1_rsp;
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//
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// Virtual Channel Select
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//----------------------------------------------------------------------
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typedef enum logic [1:0] {
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eVC_VA = 2'b00,
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eVC_VL0 = 2'b01,
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eVC_VH0 = 2'b10,
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eVC_VH1 = 2'b11
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} t_ccip_vc;
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// Multi-CL Memory Request
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//----------------------------------------------------------------------
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typedef enum logic [1:0] {
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eCL_LEN_1 = 2'b00,
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eCL_LEN_2 = 2'b01,
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eCL_LEN_4 = 2'b11
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} t_ccip_clLen;
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//
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// Structures for Request and Response headers
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//----------------------------------------------------------------------
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typedef struct packed {
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t_ccip_vc vc_sel;
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logic [1:0] rsvd1; // reserved, drive 0
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t_ccip_clLen cl_len;
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t_ccip_c0_req req_type;
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logic [5:0] rsvd0; // reserved, drive 0
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t_ccip_clAddr address;
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t_ccip_mdata mdata;
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} t_ccip_c0_ReqMemHdr;
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parameter CCIP_C0TX_HDR_WIDTH = $bits(t_ccip_c0_ReqMemHdr);
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typedef struct packed {
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logic [5:0] rsvd2;
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t_ccip_vc vc_sel;
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logic sop;
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logic rsvd1; // reserved, drive 0
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t_ccip_clLen cl_len;
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t_ccip_c1_req req_type;
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logic [5:0] rsvd0; // reserved, drive 0
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t_ccip_clAddr address;
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t_ccip_mdata mdata;
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} t_ccip_c1_ReqMemHdr;
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parameter CCIP_C1TX_HDR_WIDTH = $bits(t_ccip_c1_ReqMemHdr);
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typedef struct packed {
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logic [5:0] rsvd2; // reserved, drive 0
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t_ccip_vc vc_sel;
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logic [3:0] rsvd1; // reserved, drive 0
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t_ccip_c1_req req_type;
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logic [47:0] rsvd0; // reserved, drive 0
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t_ccip_mdata mdata;
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}t_ccip_c1_ReqFenceHdr;
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typedef struct packed {
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t_ccip_vc vc_used;
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logic rsvd1; // reserved, don't care
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logic hit_miss;
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logic [1:0] rsvd0; // reserved, don't care
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t_ccip_clNum cl_num;
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t_ccip_c0_rsp resp_type;
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t_ccip_mdata mdata;
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} t_ccip_c0_RspMemHdr;
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parameter CCIP_C0RX_HDR_WIDTH = $bits(t_ccip_c0_RspMemHdr);
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typedef struct packed {
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t_ccip_vc vc_used;
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logic rsvd1; // reserved, don't care
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logic hit_miss;
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logic format;
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logic rsvd0; // reserved, don't care
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t_ccip_clNum cl_num;
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t_ccip_c1_rsp resp_type;
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t_ccip_mdata mdata;
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} t_ccip_c1_RspMemHdr;
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parameter CCIP_C1RX_HDR_WIDTH = $bits(t_ccip_c1_RspMemHdr);
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typedef struct packed {
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logic [7:0] rsvd0; // reserved, don't care
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t_ccip_c1_rsp resp_type;
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t_ccip_mdata mdata;
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} t_ccip_c1_RspFenceHdr;
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// Alternate Channel 0 MMIO request from host :
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// MMIO requests arrive on the same channel as read responses, sharing
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// t_if_ccip_c0_Rx below. When either mmioRdValid or mmioWrValid is set
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// the message is an MMIO request and should be processed by casting
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// t_if_ccip_c0_Rx.hdr to t_ccip_c0_ReqMmioHdr.
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typedef struct packed {
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t_ccip_mmioAddr address; // 4B aligned Mmio address
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logic [1:0] length; // 2'b00- 4B, 2'b01- 8B, 2'b10- 64B
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logic rsvd; // reserved, don't care
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t_ccip_tid tid;
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} t_ccip_c0_ReqMmioHdr;
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typedef struct packed {
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t_ccip_tid tid; // Returned back from ReqMmioHdr
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} t_ccip_c2_RspMmioHdr;
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parameter CCIP_C2TX_HDR_WIDTH = $bits(t_ccip_c2_RspMmioHdr);
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//------------------------------------------------------------------------
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// CCI-P Input & Output bus structures
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//
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// Users are encouraged to use these for AFU development
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//------------------------------------------------------------------------
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// Channel 0 : Memory Reads
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typedef struct packed {
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t_ccip_c0_ReqMemHdr hdr; // Request Header
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logic valid; // Request Valid
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} t_if_ccip_c0_Tx;
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// Channel 1 : Memory Writes, Interrupts, CmpXchg
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typedef struct packed {
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t_ccip_c1_ReqMemHdr hdr; // Request Header
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t_ccip_clData data; // Request Data
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logic valid; // Request Wr Valid
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} t_if_ccip_c1_Tx;
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// Channel 2 : MMIO Read response
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typedef struct packed {
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t_ccip_c2_RspMmioHdr hdr; // Response Header
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logic mmioRdValid; // Response Read Valid
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t_ccip_mmioData data; // Response Data
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} t_if_ccip_c2_Tx;
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// Wrap all Tx channels
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typedef struct packed {
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t_if_ccip_c0_Tx c0;
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t_if_ccip_c1_Tx c1;
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t_if_ccip_c2_Tx c2;
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} t_if_ccip_Tx;
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// Channel 0: Memory Read response, MMIO Request
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typedef struct packed {
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t_ccip_c0_RspMemHdr hdr; // Rd Response/ MMIO req Header
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t_ccip_clData data; // Rd Data / MMIO req Data
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// Only one of valid, mmioRdValid and mmioWrValid may be set
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// in a cycle. When either mmioRdValid or mmioWrValid are true
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// the hdr must be processed specially. See t_ccip_c0_ReqMmioHdr
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// above.
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logic rspValid; // Rd Response Valid
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logic mmioRdValid; // MMIO Read Valid
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logic mmioWrValid; // MMIO Write Valid
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} t_if_ccip_c0_Rx;
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// Channel 1: Memory Writes
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typedef struct packed {
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t_ccip_c1_RspMemHdr hdr; // Response Header
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logic rspValid; // Response Valid
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} t_if_ccip_c1_Rx;
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// Wrap all channels
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typedef struct packed {
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logic c0TxAlmFull; // C0 Request Channel Almost Full
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logic c1TxAlmFull; // C1 Request Channel Almost Full
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t_if_ccip_c0_Rx c0;
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t_if_ccip_c1_Rx c1;
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} t_if_ccip_Rx;
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typedef union packed {
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t_ccip_c0_RspMemHdr rspMemHdr;
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t_ccip_c0_ReqMmioHdr reqMmioHdr;
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} t_if_ccip_c0_RxHdr;
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endpackage
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