c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
413 lines
13 KiB
Systemverilog
413 lines
13 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "vortex_afu.vh"
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module VX_afu_wrap #(
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parameter C_S_AXI_CTRL_ADDR_WIDTH = 8,
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parameter C_S_AXI_CTRL_DATA_WIDTH = 32,
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parameter C_M_AXI_MEM_ID_WIDTH = 16,
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parameter C_M_AXI_MEM_ADDR_WIDTH = 32,
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parameter C_M_AXI_MEM_DATA_WIDTH = 512
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) (
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// System signals
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input wire ap_clk,
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input wire ap_rst_n,
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// AXI4 master interface
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`REPEAT (`M_AXI_MEM_NUM_BANKS, GEN_AXI_MEM, REPEAT_COMMA),
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// AXI4-Lite slave interface
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input wire s_axi_ctrl_awvalid,
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output wire s_axi_ctrl_awready,
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input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr,
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input wire s_axi_ctrl_wvalid,
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output wire s_axi_ctrl_wready,
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input wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata,
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input wire [C_S_AXI_CTRL_DATA_WIDTH/8-1:0] s_axi_ctrl_wstrb,
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input wire s_axi_ctrl_arvalid,
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output wire s_axi_ctrl_arready,
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input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr,
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output wire s_axi_ctrl_rvalid,
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input wire s_axi_ctrl_rready,
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output wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata,
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output wire [1:0] s_axi_ctrl_rresp,
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output wire s_axi_ctrl_bvalid,
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input wire s_axi_ctrl_bready,
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output wire [1:0] s_axi_ctrl_bresp,
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output wire interrupt
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);
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localparam C_M_AXI_MEM_NUM_BANKS = `M_AXI_MEM_NUM_BANKS;
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localparam STATE_IDLE = 0;
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localparam STATE_RUN = 1;
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wire m_axi_mem_awvalid_a [C_M_AXI_MEM_NUM_BANKS];
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wire m_axi_mem_awready_a [C_M_AXI_MEM_NUM_BANKS];
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wire [C_M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_awaddr_a [C_M_AXI_MEM_NUM_BANKS];
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wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_awid_a [C_M_AXI_MEM_NUM_BANKS];
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wire [7:0] m_axi_mem_awlen_a [C_M_AXI_MEM_NUM_BANKS];
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wire m_axi_mem_wvalid_a [C_M_AXI_MEM_NUM_BANKS];
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wire m_axi_mem_wready_a [C_M_AXI_MEM_NUM_BANKS];
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wire [C_M_AXI_MEM_DATA_WIDTH-1:0] m_axi_mem_wdata_a [C_M_AXI_MEM_NUM_BANKS];
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wire [C_M_AXI_MEM_DATA_WIDTH/8-1:0] m_axi_mem_wstrb_a [C_M_AXI_MEM_NUM_BANKS];
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wire m_axi_mem_wlast_a [C_M_AXI_MEM_NUM_BANKS];
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wire m_axi_mem_bvalid_a [C_M_AXI_MEM_NUM_BANKS];
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wire m_axi_mem_bready_a [C_M_AXI_MEM_NUM_BANKS];
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wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_bid_a [C_M_AXI_MEM_NUM_BANKS];
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wire [1:0] m_axi_mem_bresp_a [C_M_AXI_MEM_NUM_BANKS];
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wire m_axi_mem_arvalid_a [C_M_AXI_MEM_NUM_BANKS];
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wire m_axi_mem_arready_a [C_M_AXI_MEM_NUM_BANKS];
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wire [C_M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_araddr_a [C_M_AXI_MEM_NUM_BANKS];
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wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_arid_a [C_M_AXI_MEM_NUM_BANKS];
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wire [7:0] m_axi_mem_arlen_a [C_M_AXI_MEM_NUM_BANKS];
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wire m_axi_mem_rvalid_a [C_M_AXI_MEM_NUM_BANKS];
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wire m_axi_mem_rready_a [C_M_AXI_MEM_NUM_BANKS];
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wire [C_M_AXI_MEM_DATA_WIDTH-1:0] m_axi_mem_rdata_a [C_M_AXI_MEM_NUM_BANKS];
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wire m_axi_mem_rlast_a [C_M_AXI_MEM_NUM_BANKS];
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wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_rid_a [C_M_AXI_MEM_NUM_BANKS];
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wire [1:0] m_axi_mem_rresp_a [C_M_AXI_MEM_NUM_BANKS];
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// convert memory interface to array
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`REPEAT (`M_AXI_MEM_NUM_BANKS, AXI_MEM_TO_ARRAY, REPEAT_SEMICOLON);
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wire clk = ap_clk;
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wire reset = ~ap_rst_n;
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reg [`CLOG2(`RESET_DELAY+1)-1:0] vx_reset_ctr;
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reg [15:0] vx_pending_writes;
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reg vx_busy_wait;
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reg vx_running;
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wire vx_busy;
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wire [63:0] mem_base [C_M_AXI_MEM_NUM_BANKS];
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wire dcr_wr_valid;
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wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr;
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wire [`VX_DCR_DATA_WIDTH-1:0] dcr_wr_data;
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reg state;
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wire ap_reset;
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wire ap_start;
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wire ap_idle = ~vx_running;
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wire ap_done = ~(state == STATE_RUN || vx_pending_writes != 0);
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wire ap_ready = 1'b1;
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`ifdef SCOPE
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wire scope_bus_in;
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wire scope_bus_out;
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wire scope_reset = reset;
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`endif
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always @(posedge ap_clk) begin
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if (reset || ap_reset) begin
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state <= STATE_IDLE;
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vx_busy_wait <= 0;
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vx_running <= 0;
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end else begin
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case (state)
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STATE_IDLE: begin
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if (ap_start) begin
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`ifdef DBG_TRACE_AFU
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`TRACE(2, ("%d: STATE RUN\n", $time));
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`endif
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state <= STATE_RUN;
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vx_running <= 0;
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end
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end
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STATE_RUN: begin
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if (vx_running) begin
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if (vx_busy_wait) begin
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// wait until processor goes busy
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if (vx_busy) begin
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vx_busy_wait <= 0;
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end
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end else begin
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// wait until the processor is not busy
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if (~vx_busy) begin
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state <= STATE_IDLE;
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`ifdef DBG_TRACE_AFU
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`TRACE(2, ("%d: AFU: End execution\n", $time));
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`TRACE(2, ("%d: STATE IDLE\n", $time));
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`endif
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end
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end
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end else begin
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// wait until the reset sequence is complete
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if (vx_reset_ctr == (`RESET_DELAY-1)) begin
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`ifdef DBG_TRACE_AFU
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`TRACE(2, ("%d: AFU: Begin execution\n", $time));
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`endif
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vx_running <= 1;
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vx_busy_wait <= 1;
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end
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end
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end
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endcase
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end
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end
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reg m_axi_mem_wfire;
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reg m_axi_mem_bfire;
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always @(*) begin
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m_axi_mem_wfire = 0;
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m_axi_mem_bfire = 0;
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for (integer i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin
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m_axi_mem_wfire |= m_axi_mem_wvalid_a[i] && m_axi_mem_wready_a[i];
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m_axi_mem_bfire |= m_axi_mem_bvalid_a[i] && m_axi_mem_bready_a[i];
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end
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end
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always @(posedge ap_clk) begin
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if (reset || ap_reset) begin
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vx_pending_writes <= '0;
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end else begin
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if (m_axi_mem_wfire && ~m_axi_mem_bfire)
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vx_pending_writes <= vx_pending_writes + 1;
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if (~m_axi_mem_wfire && m_axi_mem_bfire)
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vx_pending_writes <= vx_pending_writes - 1;
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end
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end
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always @(posedge ap_clk) begin
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if (state == STATE_RUN) begin
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vx_reset_ctr <= vx_reset_ctr + 1;
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end else begin
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vx_reset_ctr <= '0;
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end
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end
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VX_afu_ctrl #(
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.AXI_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH),
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.AXI_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH),
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.AXI_NUM_BANKS (C_M_AXI_MEM_NUM_BANKS)
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) afu_ctrl (
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.clk (ap_clk),
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.reset (reset || ap_reset),
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.clk_en (1'b1),
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.s_axi_awvalid (s_axi_ctrl_awvalid),
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.s_axi_awready (s_axi_ctrl_awready),
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.s_axi_awaddr (s_axi_ctrl_awaddr),
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.s_axi_wvalid (s_axi_ctrl_wvalid),
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.s_axi_wready (s_axi_ctrl_wready),
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.s_axi_wdata (s_axi_ctrl_wdata),
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.s_axi_wstrb (s_axi_ctrl_wstrb),
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.s_axi_arvalid (s_axi_ctrl_arvalid),
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.s_axi_arready (s_axi_ctrl_arready),
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.s_axi_araddr (s_axi_ctrl_araddr),
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.s_axi_rvalid (s_axi_ctrl_rvalid),
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.s_axi_rready (s_axi_ctrl_rready),
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.s_axi_rdata (s_axi_ctrl_rdata),
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.s_axi_rresp (s_axi_ctrl_rresp),
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.s_axi_bvalid (s_axi_ctrl_bvalid),
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.s_axi_bready (s_axi_ctrl_bready),
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.s_axi_bresp (s_axi_ctrl_bresp),
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.ap_reset (ap_reset),
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.ap_start (ap_start),
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.ap_done (ap_done),
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.ap_ready (ap_ready),
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.ap_idle (ap_idle),
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.interrupt (interrupt),
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`ifdef SCOPE
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.scope_bus_in (scope_bus_out),
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.scope_bus_out (scope_bus_in),
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`endif
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.mem_base (mem_base),
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.dcr_wr_valid (dcr_wr_valid),
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.dcr_wr_addr (dcr_wr_addr),
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.dcr_wr_data (dcr_wr_data)
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);
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wire [`XLEN-1:0] m_axi_mem_awaddr_w [C_M_AXI_MEM_NUM_BANKS];
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wire [`XLEN-1:0] m_axi_mem_araddr_w [C_M_AXI_MEM_NUM_BANKS];
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for (genvar i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin
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assign m_axi_mem_awaddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_awaddr_w[i]) + C_M_AXI_MEM_ADDR_WIDTH'(mem_base[i]);
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assign m_axi_mem_araddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_araddr_w[i]) + C_M_AXI_MEM_ADDR_WIDTH'(mem_base[i]);
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end
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`SCOPE_IO_SWITCH (2)
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Vortex_axi #(
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.AXI_DATA_WIDTH (C_M_AXI_MEM_DATA_WIDTH),
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.AXI_ADDR_WIDTH (`XLEN),
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.AXI_TID_WIDTH (C_M_AXI_MEM_ID_WIDTH),
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.AXI_NUM_BANKS (C_M_AXI_MEM_NUM_BANKS)
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) vortex_axi (
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`SCOPE_IO_BIND (1)
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.clk (ap_clk),
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.reset (reset || ap_reset || ~vx_running),
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.m_axi_awvalid (m_axi_mem_awvalid_a),
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.m_axi_awready (m_axi_mem_awready_a),
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.m_axi_awaddr (m_axi_mem_awaddr_w),
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.m_axi_awid (m_axi_mem_awid_a),
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`UNUSED_PIN (m_axi_awlen),
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`UNUSED_PIN (m_axi_awsize),
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`UNUSED_PIN (m_axi_awburst),
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`UNUSED_PIN (m_axi_awlock),
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`UNUSED_PIN (m_axi_awcache),
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`UNUSED_PIN (m_axi_awprot),
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`UNUSED_PIN (m_axi_awqos),
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`UNUSED_PIN (m_axi_awregion),
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.m_axi_wvalid (m_axi_mem_wvalid_a),
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.m_axi_wready (m_axi_mem_wready_a),
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.m_axi_wdata (m_axi_mem_wdata_a),
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.m_axi_wstrb (m_axi_mem_wstrb_a),
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.m_axi_wlast (m_axi_mem_wlast_a),
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.m_axi_bvalid (m_axi_mem_bvalid_a),
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.m_axi_bready (m_axi_mem_bready_a),
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.m_axi_bid (m_axi_mem_bid_a),
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.m_axi_bresp (m_axi_mem_bresp_a),
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.m_axi_arvalid (m_axi_mem_arvalid_a),
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.m_axi_arready (m_axi_mem_arready_a),
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.m_axi_araddr (m_axi_mem_araddr_w),
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.m_axi_arid (m_axi_mem_arid_a),
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.m_axi_arlen (m_axi_mem_arlen_a),
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`UNUSED_PIN (m_axi_arsize),
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`UNUSED_PIN (m_axi_arburst),
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`UNUSED_PIN (m_axi_arlock),
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`UNUSED_PIN (m_axi_arcache),
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`UNUSED_PIN (m_axi_arprot),
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`UNUSED_PIN (m_axi_arqos),
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`UNUSED_PIN (m_axi_arregion),
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.m_axi_rvalid (m_axi_mem_rvalid_a),
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.m_axi_rready (m_axi_mem_rready_a),
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.m_axi_rdata (m_axi_mem_rdata_a),
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.m_axi_rlast (m_axi_mem_rlast_a),
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.m_axi_rid (m_axi_mem_rid_a),
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.m_axi_rresp (m_axi_mem_rresp_a),
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.dcr_wr_valid (dcr_wr_valid),
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.dcr_wr_addr (dcr_wr_addr),
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.dcr_wr_data (dcr_wr_data),
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.busy (vx_busy)
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);
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// SCOPE //////////////////////////////////////////////////////////////////////
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`ifdef DBG_SCOPE_AFU
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`ifdef SCOPE
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`define TRIGGERS { \
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reset, \
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ap_start, \
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ap_done, \
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ap_idle, \
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interrupt, \
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vx_busy_wait, \
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vx_busy, \
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vx_running \
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}
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`define PROBES { \
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vx_pending_writes \
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}
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VX_scope_tap #(
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.SCOPE_ID (0),
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.TRIGGERW ($bits(`TRIGGERS)),
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.PROBEW ($bits(`PROBES))
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) scope_tap (
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.clk(clk),
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.reset(scope_reset_w[0]),
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.start(1'b0),
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.stop(1'b0),
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.triggers(`TRIGGERS),
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.probes(`PROBES),
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.bus_in(scope_bus_in_w[0]),
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.bus_out(scope_bus_out_w[0])
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);
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`endif
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`ifdef CHIPSCOPE
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ila_afu ila_afu_inst (
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.clk (ap_clk),
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.probe0 ({
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ap_start,
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ap_done,
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ap_idle,
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interrupt
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}),
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.probe1 ({
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vx_pending_writes,
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vx_busy_wait,
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vx_busy,
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vx_running
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})
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);
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`endif
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`else
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`SCOPE_IO_UNUSED_W(0)
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`endif
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`ifdef SIMULATION
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`ifndef VERILATOR
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// disable assertions until full reset
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reg [`CLOG2(`RESET_DELAY+1)-1:0] assert_delay_ctr;
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reg assert_enabled;
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initial begin
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$assertoff(0, vortex_axi);
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end
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always @(posedge ap_clk) begin
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if (reset) begin
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assert_delay_ctr <= '0;
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assert_enabled <= 0;
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end else begin
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if (~assert_enabled) begin
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if (assert_delay_ctr == (`RESET_DELAY-1)) begin
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assert_enabled <= 1;
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$asserton(0, vortex_axi); // enable assertions
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end else begin
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assert_delay_ctr <= assert_delay_ctr + 1;
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end
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end
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end
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end
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`endif
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`endif
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`ifdef DBG_TRACE_AFU
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always @(posedge ap_clk) begin
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for (integer i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin
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if (m_axi_mem_awvalid_a[i] && m_axi_mem_awready_a[i]) begin
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`TRACE(2, ("%d: AFU Wr Req [%0d]: addr=0x%0h, tag=0x%0h\n", $time, i, m_axi_mem_awaddr_a[i], m_axi_mem_awid_a[i]));
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end
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if (m_axi_mem_wvalid_a[i] && m_axi_mem_wready_a[i]) begin
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`TRACE(2, ("%d: AFU Wr Req [%0d]: data=0x%0h\n", $time, i, m_axi_mem_wdata_a[i]));
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end
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if (m_axi_mem_arvalid_a[i] && m_axi_mem_arready_a[i]) begin
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`TRACE(2, ("%d: AFU Rd Req [%0d]: addr=0x%0h, tag=0x%0h\n", $time, i, m_axi_mem_araddr_a[i], m_axi_mem_arid_a[i]));
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end
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if (m_axi_mem_rvalid_a[i] && m_axi_mem_rready_a[i]) begin
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`TRACE(2, ("%d: AVS Rd Rsp [%0d]: data=0x%0h, tag=0x%0h\n", $time, i, m_axi_mem_rdata_a[i], m_axi_mem_rid_a[i]));
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end
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end
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end
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`endif
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endmodule
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