149 lines
5.5 KiB
Verilog
149 lines
5.5 KiB
Verilog
`include "vortex_afu.vh"
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/* verilator lint_off IMPORTSTAR */
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import ccip_if_pkg::*;
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import local_mem_cfg_pkg::*;
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/* verilator lint_on IMPORTSTAR */
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module vortex_afu_sim #(
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parameter NUM_LOCAL_MEM_BANKS = 2
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) (
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// global signals
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input clk,
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input reset,
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// IF signals between CCI and AFU
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input logic vcp2af_sRxPort_c0_TxAlmFull,
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input logic vcp2af_sRxPort_c1_TxAlmFull,
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input t_ccip_vc vcp2af_sRxPort_c0_hdr_vc_used,
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input logic vcp2af_sRxPort_c0_hdr_rsvd1,
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input logic vcp2af_sRxPort_c0_hdr_hit_miss,
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input logic [1:0] vcp2af_sRxPort_c0_hdr_rsvd0,
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input t_ccip_clNum vcp2af_sRxPort_c0_hdr_cl_num,
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input t_ccip_c0_rsp vcp2af_sRxPort_c0_hdr_resp_type,
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input t_ccip_mdata vcp2af_sRxPort_c0_hdr_mdata,
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input t_ccip_clData vcp2af_sRxPort_c0_data,
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input logic vcp2af_sRxPort_c0_rspValid,
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input logic vcp2af_sRxPort_c0_mmioRdValid,
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input logic vcp2af_sRxPort_c0_mmioWrValid,
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input t_ccip_vc vcp2af_sRxPort_c1_hdr_vc_used,
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input logic vcp2af_sRxPort_c1_hdr_rsvd1,
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input logic vcp2af_sRxPort_c1_hdr_hit_miss,
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input logic vcp2af_sRxPort_c1_hdr_format,
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input logic vcp2af_sRxPort_c1_hdr_rsvd0,
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input t_ccip_clNum vcp2af_sRxPort_c1_hdr_cl_num,
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input t_ccip_c1_rsp vcp2af_sRxPort_c1_hdr_resp_type,
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input t_ccip_mdata vcp2af_sRxPort_c1_hdr_mdata,
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input logic vcp2af_sRxPort_c1_rspValid,
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output t_ccip_vc af2cp_sTxPort_c0_hdr_vc_sel,
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output logic [1:0] af2cp_sTxPort_c0_hdr_rsvd1,
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output t_ccip_clLen af2cp_sTxPort_c0_hdr_cl_len,
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output t_ccip_c0_req af2cp_sTxPort_c0_hdr_req_type,
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output logic [5:0] af2cp_sTxPort_c0_hdr_rsvd0,
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output t_ccip_clAddr af2cp_sTxPort_c0_hdr_address,
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output t_ccip_mdata af2cp_sTxPort_c0_hdr_mdata,
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output logic af2cp_sTxPort_c0_valid,
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output logic [5:0] af2cp_sTxPort_c1_hdr_rsvd2,
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output t_ccip_vc af2cp_sTxPort_c1_hdr_vc_sel,
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output logic af2cp_sTxPort_c1_hdr_sop,
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output logic af2cp_sTxPort_c1_hdr_rsvd1,
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output t_ccip_clLen af2cp_sTxPort_c1_hdr_cl_len,
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output t_ccip_c1_req af2cp_sTxPort_c1_hdr_req_type,
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output logic [5:0] af2cp_sTxPort_c1_hdr_rsvd0,
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output t_ccip_clAddr af2cp_sTxPort_c1_hdr_address,
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output t_ccip_mdata af2cp_sTxPort_c1_hdr_mdata,
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output t_ccip_clData af2cp_sTxPort_c1_data,
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output logic af2cp_sTxPort_c1_valid,
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output t_ccip_tid af2cp_sTxPort_c2_hdr_tid,
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output logic af2cp_sTxPort_c2_mmioRdValid,
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output t_ccip_mmioData af2cp_sTxPort_c2_data,
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// Avalon signals for local memory access
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output t_local_mem_data avs_writedata,
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input t_local_mem_data avs_readdata,
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output t_local_mem_addr avs_address,
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input logic avs_waitrequest,
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output logic avs_write,
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output logic avs_read,
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output t_local_mem_byte_mask avs_byteenable,
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output t_local_mem_burst_cnt avs_burstcount,
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input avs_readdatavalid,
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output logic [$clog2(NUM_LOCAL_MEM_BANKS)-1:0] mem_bank_select
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);
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vortex_afu #(
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.NUM_LOCAL_MEM_BANKS(NUM_LOCAL_MEM_BANKS)
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) vortex_afu (
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.clk(clk),
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.SoftReset(reset),
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.cp2af_sRxPort({
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vcp2af_sRxPort_c0_TxAlmFull,
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vcp2af_sRxPort_c1_TxAlmFull,
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vcp2af_sRxPort_c0_hdr_vc_used,
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vcp2af_sRxPort_c0_hdr_rsvd1,
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vcp2af_sRxPort_c0_hdr_hit_miss,
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vcp2af_sRxPort_c0_hdr_rsvd0,
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vcp2af_sRxPort_c0_hdr_cl_num,
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vcp2af_sRxPort_c0_hdr_resp_type,
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vcp2af_sRxPort_c0_hdr_mdata,
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vcp2af_sRxPort_c0_data,
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vcp2af_sRxPort_c0_rspValid,
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vcp2af_sRxPort_c0_mmioRdValid,
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vcp2af_sRxPort_c0_mmioWrValid,
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vcp2af_sRxPort_c1_hdr_vc_used,
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vcp2af_sRxPort_c1_hdr_rsvd1,
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vcp2af_sRxPort_c1_hdr_hit_miss,
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vcp2af_sRxPort_c1_hdr_format,
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vcp2af_sRxPort_c1_hdr_rsvd0,
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vcp2af_sRxPort_c1_hdr_cl_num,
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vcp2af_sRxPort_c1_hdr_resp_type,
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vcp2af_sRxPort_c1_hdr_mdata,
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vcp2af_sRxPort_c1_rspValid}
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),
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.af2cp_sTxPort({
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af2cp_sTxPort_c0_hdr_vc_sel,
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af2cp_sTxPort_c0_hdr_rsvd1,
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af2cp_sTxPort_c0_hdr_cl_len,
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af2cp_sTxPort_c0_hdr_req_type,
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af2cp_sTxPort_c0_hdr_rsvd0,
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af2cp_sTxPort_c0_hdr_address,
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af2cp_sTxPort_c0_hdr_mdata,
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af2cp_sTxPort_c0_valid,
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af2cp_sTxPort_c1_hdr_rsvd2,
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af2cp_sTxPort_c1_hdr_vc_sel,
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af2cp_sTxPort_c1_hdr_sop,
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af2cp_sTxPort_c1_hdr_rsvd1,
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af2cp_sTxPort_c1_hdr_cl_len,
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af2cp_sTxPort_c1_hdr_req_type,
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af2cp_sTxPort_c1_hdr_rsvd0,
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af2cp_sTxPort_c1_hdr_address,
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af2cp_sTxPort_c1_hdr_mdata,
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af2cp_sTxPort_c1_data,
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af2cp_sTxPort_c1_valid,
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af2cp_sTxPort_c2_hdr_tid,
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af2cp_sTxPort_c2_mmioRdValid,
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af2cp_sTxPort_c2_data
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}),
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.avs_writedata(avs_writedata),
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.avs_readdata(avs_readdata),
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.avs_address(avs_address),
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.avs_waitrequest(avs_waitrequest),
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.avs_write(avs_write),
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.avs_read(avs_read),
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.avs_byteenable(avs_byteenable),
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.avs_burstcount(avs_burstcount),
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.avs_readdatavalid(avs_readdatavalid),
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.mem_bank_select(mem_bank_select)
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);
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endmodule |