84 lines
3.7 KiB
Verilog
84 lines
3.7 KiB
Verilog
`include "VX_define.vh"
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module VX_issue_demux (
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// inputs
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VX_decode_if decode_if,
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VX_gpr_read_if gpr_read_if,
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input wire [`ISTAG_BITS-1:0] issue_tag,
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// outputs
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VX_alu_req_if alu_req_if,
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VX_lsu_req_if lsu_req_if,
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VX_csr_req_if csr_req_if,
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VX_mul_req_if mul_req_if,
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VX_fpu_req_if fpu_req_if,
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VX_gpu_req_if gpu_req_if
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);
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// ALU unit
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assign alu_req_if.valid = decode_if.valid && (decode_if.ex_type == `EX_ALU);
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assign alu_req_if.thread_mask = decode_if.thread_mask;
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assign alu_req_if.issue_tag = issue_tag;
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assign alu_req_if.warp_num = decode_if.warp_num;
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assign alu_req_if.curr_PC = decode_if.curr_PC;
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assign alu_req_if.alu_op = `ALU_OP(decode_if.ex_op);
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assign alu_req_if.rs1_data = decode_if.rs1_is_PC ? {`NUM_THREADS{decode_if.curr_PC}} : gpr_read_if.rs1_data;
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assign alu_req_if.rs2_data = decode_if.rs2_is_imm ? {`NUM_THREADS{decode_if.imm}} : gpr_read_if.rs2_data;
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assign alu_req_if.offset = decode_if.imm;
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assign alu_req_if.next_PC = decode_if.next_PC;
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// LSU unit
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assign lsu_req_if.valid = decode_if.valid && (decode_if.ex_type == `EX_LSU);
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assign lsu_req_if.thread_mask = decode_if.thread_mask;
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assign lsu_req_if.issue_tag = issue_tag;
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assign lsu_req_if.warp_num = decode_if.warp_num;
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assign lsu_req_if.curr_PC = decode_if.curr_PC;
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assign lsu_req_if.base_addr = gpr_read_if.rs1_data;
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assign lsu_req_if.store_data = gpr_read_if.rs2_data;
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assign lsu_req_if.offset = decode_if.imm;
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assign lsu_req_if.rw = `LSU_RW(decode_if.ex_op);
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assign lsu_req_if.byteen = `LSU_BE(decode_if.ex_op);
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assign lsu_req_if.rd = decode_if.rd;
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assign lsu_req_if.wb = decode_if.wb;
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// CSR unit
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assign csr_req_if.valid = decode_if.valid && (decode_if.ex_type == `EX_CSR);
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assign csr_req_if.issue_tag = issue_tag;
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assign csr_req_if.warp_num = decode_if.warp_num;
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assign csr_req_if.curr_PC = decode_if.curr_PC;
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assign csr_req_if.csr_op = `CSR_OP(decode_if.ex_op);
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assign csr_req_if.csr_addr = decode_if.imm[`CSR_ADDR_SIZE-1:0];
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assign csr_req_if.csr_mask = decode_if.rs2_is_imm ? 32'(decode_if.rs1) : gpr_read_if.rs1_data[0];
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assign csr_req_if.is_io = 1'b0;
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// MUL unit
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`ifdef EXT_M_ENABLE
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assign mul_req_if.valid = decode_if.valid && (decode_if.ex_type == `EX_MUL);
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assign mul_req_if.issue_tag = issue_tag;
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assign mul_req_if.mul_op = `MUL_OP(decode_if.ex_op);
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assign mul_req_if.rs1_data = gpr_read_if.rs1_data;
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assign mul_req_if.rs2_data = gpr_read_if.rs2_data;
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`endif
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// FPU unit
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`ifdef EXT_F_ENABLE
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assign fpu_req_if.valid = decode_if.valid && (decode_if.ex_type == `EX_FPU);
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assign fpu_req_if.issue_tag = issue_tag;
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assign fpu_req_if.warp_num = decode_if.warp_num;
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assign fpu_req_if.fpu_op = `FPU_OP(decode_if.ex_op);
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assign fpu_req_if.rs1_data = gpr_read_if.rs1_data;
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assign fpu_req_if.rs2_data = gpr_read_if.rs2_data;
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assign fpu_req_if.rs3_data = gpr_read_if.rs3_data;
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assign fpu_req_if.frm = decode_if.frm;
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`endif
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// GPU unit
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assign gpu_req_if.valid = decode_if.valid && (decode_if.ex_type == `EX_GPU);
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assign gpu_req_if.thread_mask = decode_if.thread_mask;
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assign gpu_req_if.issue_tag = issue_tag;
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assign gpu_req_if.warp_num = decode_if.warp_num;
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assign gpu_req_if.gpu_op = `GPU_OP(decode_if.ex_op);
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assign gpu_req_if.rs1_data = gpr_read_if.rs1_data;
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assign gpu_req_if.rs2_data = gpr_read_if.rs2_data[0];
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assign gpu_req_if.next_PC = decode_if.next_PC;
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endmodule |