76 lines
1.9 KiB
Verilog
76 lines
1.9 KiB
Verilog
`include "VX_platform.vh"
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module VX_multiplier #(
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parameter WIDTHA = 1,
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parameter WIDTHB = 1,
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parameter WIDTHP = 1,
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parameter SIGNED = 0,
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parameter PIPELINE = 0
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) (
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input wire clk,
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input wire reset,
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input wire clk_en,
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input wire [WIDTHA-1:0] dataa,
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input wire [WIDTHB-1:0] datab,
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output wire [WIDTHP-1:0] result
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);
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`ifdef QUARTUS
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lpm_mult quartus_mult (
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.clock (clk),
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.dataa (dataa),
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.datab (datab),
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.result (result),
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.sclr (reset),
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.aclr (1'b0),
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.clken (clk_en),
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.sum (1'b0)
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);
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defparam quartus_mult.lpm_type = "LPM_MULT",
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quartus_mult.lpm_widtha = WIDTHA,
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quartus_mult.lpm_widthb = WIDTHB,
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quartus_mult.lpm_widthp = WIDTHP,
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quartus_mult.lpm_representation = SIGNED ? "SIGNED" : "UNSIGNED",
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quartus_mult.lpm_pipeline = PIPELINE,
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quartus_mult.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9";
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`else
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wire [WIDTHP-1:0] result_unqual;
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if (SIGNED) begin
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assign result_unqual = $signed(dataa) * $signed(datab);
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end else begin
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assign result_unqual = dataa * datab;
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end
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if (PIPELINE == 0) begin
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assign result = result_unqual;
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end else begin
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reg [WIDTHP-1:0] result_pipe [0:PIPELINE-1];
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genvar i;
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for (i = 0; i < PIPELINE; i++) begin
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always @(posedge clk) begin
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if (reset) begin
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result_pipe[i] <= 0;
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end
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else if (clk_en) begin
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if (i == 0) begin
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result_pipe[i] <= result_unqual;
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end else begin
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result_pipe[i] <= result_pipe[i-1];
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end
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end
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end
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end
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assign result = result_pipe[PIPELINE-1];
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end
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`endif
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endmodule |