c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
66 lines
2.6 KiB
Systemverilog
66 lines
2.6 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`ifndef VX_CACHE_DEFINE_VH
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`define VX_CACHE_DEFINE_VH
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`include "VX_define.vh"
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`define CS_REQ_SEL_BITS `CLOG2(NUM_REQS)
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`define CS_WORD_WIDTH (8 * WORD_SIZE)
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`define CS_LINE_WIDTH (8 * LINE_SIZE)
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`define CS_BANK_SIZE (CACHE_SIZE / NUM_BANKS)
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`define CS_WAY_SEL_BITS `CLOG2(NUM_WAYS)
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`define CS_LINES_PER_BANK (`CS_BANK_SIZE / (LINE_SIZE * NUM_WAYS))
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`define CS_WORDS_PER_LINE (LINE_SIZE / WORD_SIZE)
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`define CS_WORD_ADDR_WIDTH (`MEM_ADDR_WIDTH-`CLOG2(WORD_SIZE))
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`define CS_MEM_ADDR_WIDTH (`MEM_ADDR_WIDTH-`CLOG2(LINE_SIZE))
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`define CS_LINE_ADDR_WIDTH (`CS_MEM_ADDR_WIDTH-`CLOG2(NUM_BANKS))
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// Word select
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`define CS_WORD_SEL_BITS `CLOG2(`CS_WORDS_PER_LINE)
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`define CS_WORD_SEL_ADDR_START 0
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`define CS_WORD_SEL_ADDR_END (`CS_WORD_SEL_ADDR_START+`CS_WORD_SEL_BITS-1)
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// Bank select
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`define CS_BANK_SEL_BITS `CLOG2(NUM_BANKS)
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`define CS_BANK_SEL_ADDR_START (1+`CS_WORD_SEL_ADDR_END)
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`define CS_BANK_SEL_ADDR_END (`CS_BANK_SEL_ADDR_START+`CS_BANK_SEL_BITS-1)
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// Line select
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`define CS_LINE_SEL_BITS `CLOG2(`CS_LINES_PER_BANK)
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`define CS_LINE_SEL_ADDR_START (1+`CS_BANK_SEL_ADDR_END)
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`define CS_LINE_SEL_ADDR_END (`CS_LINE_SEL_ADDR_START+`CS_LINE_SEL_BITS-1)
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// Tag select
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`define CS_TAG_SEL_BITS (`CS_WORD_ADDR_WIDTH-1-`CS_LINE_SEL_ADDR_END)
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`define CS_TAG_SEL_ADDR_START (1+`CS_LINE_SEL_ADDR_END)
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`define CS_TAG_SEL_ADDR_END (`CS_WORD_ADDR_WIDTH-1)
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`define CS_LINE_TAG_ADDR(x) x[`CS_LINE_ADDR_WIDTH-1 : `CS_LINE_SEL_BITS]
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///////////////////////////////////////////////////////////////////////////////
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`define CS_LINE_TO_MEM_ADDR(x, i) {x, `CS_BANK_SEL_BITS'(i)}
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`define CS_MEM_ADDR_TO_BANK_ID(x) x[0 +: `CS_BANK_SEL_BITS]
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`define CS_MEM_TAG_TO_REQ_ID(x) x[MSHR_ADDR_WIDTH-1:0]
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`define CS_MEM_TAG_TO_BANK_ID(x) x[MSHR_ADDR_WIDTH +: `CS_BANK_SEL_BITS]
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`define CS_LINE_TO_FULL_ADDR(x, i) {x, (`XLEN-$bits(x))'(i << (`XLEN-$bits(x)-`CS_BANK_SEL_BITS))}
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`define CS_MEM_TO_FULL_ADDR(x) {x, (`XLEN-$bits(x))'(0)}
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`endif // VX_CACHE_DEFINE_VH
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