54 lines
1.5 KiB
Systemverilog
54 lines
1.5 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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interface VX_pipeline_perf_if ();
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wire [`PERF_CTR_BITS-1:0] sched_idles;
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wire [`PERF_CTR_BITS-1:0] sched_stalls;
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wire [`PERF_CTR_BITS-1:0] ibf_stalls;
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wire [`PERF_CTR_BITS-1:0] scb_stalls;
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wire [`PERF_CTR_BITS-1:0] scb_uses [`NUM_EX_UNITS];
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wire [`PERF_CTR_BITS-1:0] ifetches;
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wire [`PERF_CTR_BITS-1:0] loads;
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wire [`PERF_CTR_BITS-1:0] stores;
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wire [`PERF_CTR_BITS-1:0] ifetch_latency;
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wire [`PERF_CTR_BITS-1:0] load_latency;
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modport schedule (
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output sched_idles,
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output sched_stalls
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);
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modport issue (
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output ibf_stalls,
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output scb_stalls,
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output scb_uses
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);
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modport slave (
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input sched_idles,
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input sched_stalls,
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input ibf_stalls,
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input scb_stalls,
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input scb_uses,
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input ifetches,
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input loads,
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input stores,
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input ifetch_latency,
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input load_latency
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);
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endinterface
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