146 lines
4.2 KiB
C++
146 lines
4.2 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "socket.h"
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#include "cluster.h"
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using namespace vortex;
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Socket::Socket(const SimContext& ctx,
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uint32_t socket_id,
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Cluster* cluster,
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const Arch &arch, const
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DCRS &dcrs)
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: SimObject(ctx, "socket")
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, icache_mem_req_port(this)
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, icache_mem_rsp_port(this)
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, dcache_mem_req_port(this)
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, dcache_mem_rsp_port(this)
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, socket_id_(socket_id)
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, cores_(arch.socket_size())
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, cluster_(cluster)
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{
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auto cores_per_socket = cores_.size();
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char sname[100];
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snprintf(sname, 100, "socket%d-icaches", socket_id);
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icaches_ = CacheCluster::Create(sname, cores_per_socket, NUM_ICACHES, 1, CacheSim::Config{
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!ICACHE_ENABLED,
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log2ceil(ICACHE_SIZE), // C
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log2ceil(L1_LINE_SIZE), // L
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log2ceil(sizeof(uint32_t)), // W
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log2ceil(ICACHE_NUM_WAYS),// A
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1, // B
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XLEN, // address bits
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1, // number of ports
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1, // number of inputs
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true, // write-through
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false, // write response
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(uint8_t)arch.num_warps(), // mshr
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2, // pipeline latency
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});
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icaches_->MemReqPort.bind(&icache_mem_req_port);
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icache_mem_rsp_port.bind(&icaches_->MemRspPort);
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snprintf(sname, 100, "socket%d-dcaches", socket_id);
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dcaches_ = CacheCluster::Create(sname, cores_per_socket, NUM_DCACHES, NUM_LSU_LANES, CacheSim::Config{
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!DCACHE_ENABLED,
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log2ceil(DCACHE_SIZE), // C
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log2ceil(L1_LINE_SIZE), // L
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log2ceil(sizeof(Word)), // W
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log2ceil(DCACHE_NUM_WAYS),// A
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log2ceil(DCACHE_NUM_BANKS), // B
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XLEN, // address bits
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1, // number of ports
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DCACHE_NUM_BANKS, // number of inputs
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true, // write-through
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false, // write response
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DCACHE_MSHR_SIZE, // mshr
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2, // pipeline latency
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});
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dcaches_->MemReqPort.bind(&dcache_mem_req_port);
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dcache_mem_rsp_port.bind(&dcaches_->MemRspPort);
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// create cores
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for (uint32_t i = 0; i < cores_per_socket; ++i) {
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uint32_t core_id = socket_id * cores_per_socket + i;
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cores_.at(i) = Core::Create(core_id, this, arch, dcrs);
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cores_.at(i)->icache_req_ports.at(0).bind(&icaches_->CoreReqPorts.at(i).at(0));
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icaches_->CoreRspPorts.at(i).at(0).bind(&cores_.at(i)->icache_rsp_ports.at(0));
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for (uint32_t j = 0; j < NUM_LSU_LANES; ++j) {
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cores_.at(i)->dcache_req_ports.at(j).bind(&dcaches_->CoreReqPorts.at(i).at(j));
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dcaches_->CoreRspPorts.at(i).at(j).bind(&cores_.at(i)->dcache_rsp_ports.at(j));
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}
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}
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}
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Socket::~Socket() {
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//--
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}
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void Socket::reset() {
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//--
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}
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void Socket::tick() {
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//--
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}
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void Socket::attach_ram(RAM* ram) {
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for (auto core : cores_) {
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core->attach_ram(ram);
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}
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}
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bool Socket::running() const {
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for (auto& core : cores_) {
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if (core->running())
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return true;
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}
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return false;
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}
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bool Socket::check_exit(Word* exitcode, bool riscv_test) const {
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bool done = true;
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Word exitcode_ = 0;
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for (auto& core : cores_) {
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Word ec;
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if (core->check_exit(&ec, riscv_test)) {
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exitcode_ |= ec;
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} else {
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done = false;
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}
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}
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*exitcode = exitcode_;
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return done;
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}
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void Socket::barrier(uint32_t bar_id, uint32_t count, uint32_t core_id) {
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cluster_->barrier(bar_id, count, socket_id_ * cores_.size() + core_id);
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}
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void Socket::resume(uint32_t core_index) {
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cores_.at(core_index)->resume();
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}
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Socket::PerfStats Socket::perf_stats() const {
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Socket::PerfStats perf;
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perf.icache = icaches_->perf_stats();
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perf.dcache = dcaches_->perf_stats();
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return perf;
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} |