240 lines
8.0 KiB
Systemverilog
240 lines
8.0 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`ifndef VX_GPU_PKG_VH
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`define VX_GPU_PKG_VH
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`include "VX_define.vh"
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package VX_gpu_pkg;
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typedef struct packed {
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logic valid;
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logic [`NUM_THREADS-1:0] tmask;
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} tmc_t;
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typedef struct packed {
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logic valid;
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logic [`NUM_WARPS-1:0] wmask;
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logic [`XLEN-1:0] pc;
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} wspawn_t;
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typedef struct packed {
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logic valid;
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logic is_dvg;
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logic [`NUM_THREADS-1:0] then_tmask;
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logic [`NUM_THREADS-1:0] else_tmask;
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logic [`XLEN-1:0] next_pc;
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} split_t;
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typedef struct packed {
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logic valid;
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logic is_dvg;
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} join_t;
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typedef struct packed {
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logic valid;
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logic [`NB_WIDTH-1:0] id;
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logic is_global;
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`ifdef GBAR_ENABLE
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logic [`MAX(`NW_WIDTH, `NC_WIDTH)-1:0] size_m1;
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`else
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logic [`NW_WIDTH-1:0] size_m1;
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`endif
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} barrier_t;
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typedef struct packed {
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logic [`XLEN-1:0] startup_addr;
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logic [7:0] mpm_class;
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} base_dcrs_t;
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typedef struct packed {
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logic [`PERF_CTR_BITS-1:0] reads;
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logic [`PERF_CTR_BITS-1:0] writes;
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logic [`PERF_CTR_BITS-1:0] read_misses;
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logic [`PERF_CTR_BITS-1:0] write_misses;
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logic [`PERF_CTR_BITS-1:0] bank_stalls;
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logic [`PERF_CTR_BITS-1:0] mshr_stalls;
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logic [`PERF_CTR_BITS-1:0] mem_stalls;
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logic [`PERF_CTR_BITS-1:0] crsp_stalls;
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} cache_perf_t;
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typedef struct packed {
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logic [`PERF_CTR_BITS-1:0] reads;
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logic [`PERF_CTR_BITS-1:0] writes;
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logic [`PERF_CTR_BITS-1:0] latency;
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} mem_perf_t;
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/* verilator lint_off UNUSED */
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////////////////////////// Icache Parameters //////////////////////////////
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// Word size in bytes
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localparam ICACHE_WORD_SIZE = 4;
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localparam ICACHE_ADDR_WIDTH = (`MEM_ADDR_WIDTH - `CLOG2(ICACHE_WORD_SIZE));
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// Block size in bytes
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localparam ICACHE_LINE_SIZE = `L1_LINE_SIZE;
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// Core request tag Id bits
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localparam ICACHE_TAG_ID_BITS = `NW_WIDTH;
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// Core request tag bits
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localparam ICACHE_TAG_WIDTH = (`UUID_WIDTH + ICACHE_TAG_ID_BITS);
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// Memory request data bits
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localparam ICACHE_MEM_DATA_WIDTH = (ICACHE_LINE_SIZE * 8);
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// Memory request tag bits
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`ifdef ICACHE_ENABLE
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localparam ICACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_MEM_TAG_WIDTH(`ICACHE_MSHR_SIZE, 1, `NUM_ICACHES);
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`else
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localparam ICACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_BYPASS_TAG_WIDTH(1, ICACHE_LINE_SIZE, ICACHE_WORD_SIZE, ICACHE_TAG_WIDTH, `SOCKET_SIZE, `NUM_ICACHES);
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`endif
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////////////////////////// Dcache Parameters //////////////////////////////
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// Word size in bytes
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localparam DCACHE_WORD_SIZE = (`XLEN / 8);
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localparam DCACHE_ADDR_WIDTH = (`MEM_ADDR_WIDTH - `CLOG2(DCACHE_WORD_SIZE));
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// Block size in bytes
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localparam DCACHE_LINE_SIZE = `L1_LINE_SIZE;
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// Input request size
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localparam DCACHE_NUM_REQS = `MAX(`DCACHE_NUM_BANKS, `SMEM_NUM_BANKS);
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// Memory request size
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localparam LSU_MEM_REQS = `NUM_LSU_LANES;
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// Batch select bits
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localparam DCACHE_NUM_BATCHES = ((LSU_MEM_REQS + DCACHE_NUM_REQS - 1) / DCACHE_NUM_REQS);
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localparam DCACHE_BATCH_SEL_BITS = `CLOG2(DCACHE_NUM_BATCHES);
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// Core request tag Id bits
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localparam LSUQ_TAG_BITS = (`CLOG2(`LSUQ_SIZE) + DCACHE_BATCH_SEL_BITS);
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localparam DCACHE_TAG_ID_BITS = (LSUQ_TAG_BITS + `CACHE_ADDR_TYPE_BITS);
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// Core request tag bits
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localparam DCACHE_TAG_WIDTH = (`UUID_WIDTH + DCACHE_TAG_ID_BITS);
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localparam DCACHE_NOSM_TAG_WIDTH = (DCACHE_TAG_WIDTH - `SM_ENABLED);
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// Memory request data bits
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localparam DCACHE_MEM_DATA_WIDTH = (DCACHE_LINE_SIZE * 8);
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// Memory request tag bits
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`ifdef DCACHE_ENABLE
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localparam DCACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_NC_MEM_TAG_WIDTH(`DCACHE_MSHR_SIZE, `DCACHE_NUM_BANKS, DCACHE_NUM_REQS, DCACHE_LINE_SIZE, DCACHE_WORD_SIZE, DCACHE_NOSM_TAG_WIDTH, `SOCKET_SIZE, `NUM_DCACHES);
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`else
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localparam DCACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_NC_BYPASS_TAG_WIDTH(DCACHE_NUM_REQS, DCACHE_LINE_SIZE, DCACHE_WORD_SIZE, DCACHE_NOSM_TAG_WIDTH, `SOCKET_SIZE, `NUM_DCACHES);
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`endif
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/////////////////////////////// L1 Parameters /////////////////////////////
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localparam L1_MEM_TAG_WIDTH = `MAX(ICACHE_MEM_TAG_WIDTH, DCACHE_MEM_TAG_WIDTH);
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localparam L1_MEM_ARB_TAG_WIDTH = (L1_MEM_TAG_WIDTH + `CLOG2(2));
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/////////////////////////////// L2 Parameters /////////////////////////////
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localparam ICACHE_MEM_ARB_IDX = 0;
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localparam DCACHE_MEM_ARB_IDX = ICACHE_MEM_ARB_IDX + 1;
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// Word size in bytes
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localparam L2_WORD_SIZE = `L1_LINE_SIZE;
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// Input request size
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localparam L2_NUM_REQS = `NUM_SOCKETS;
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// Core request tag bits
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localparam L2_TAG_WIDTH = L1_MEM_ARB_TAG_WIDTH;
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// Memory request data bits
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localparam L2_MEM_DATA_WIDTH = (`L2_LINE_SIZE * 8);
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// Memory request tag bits
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`ifdef L2_ENABLE
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localparam L2_MEM_TAG_WIDTH = `CACHE_NC_MEM_TAG_WIDTH(`L2_MSHR_SIZE, `L2_NUM_BANKS, L2_NUM_REQS, `L2_LINE_SIZE, L2_WORD_SIZE, L2_TAG_WIDTH);
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`else
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localparam L2_MEM_TAG_WIDTH = `CACHE_NC_BYPASS_TAG_WIDTH(L2_NUM_REQS, `L2_LINE_SIZE, L2_WORD_SIZE, L2_TAG_WIDTH);
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`endif
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/////////////////////////////// L3 Parameters /////////////////////////////
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// Word size in bytes
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localparam L3_WORD_SIZE = `L2_LINE_SIZE;
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// Input request size
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localparam L3_NUM_REQS = `NUM_CLUSTERS;
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// Core request tag bits
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localparam L3_TAG_WIDTH = L2_MEM_TAG_WIDTH;
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// Memory request data bits
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localparam L3_MEM_DATA_WIDTH = (`L3_LINE_SIZE * 8);
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// Memory request tag bits
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`ifdef L3_ENABLE
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localparam L3_MEM_TAG_WIDTH = `CACHE_NC_MEM_TAG_WIDTH(`L3_MSHR_SIZE, `L3_NUM_BANKS, L3_NUM_REQS, `L3_LINE_SIZE, L3_WORD_SIZE, L3_TAG_WIDTH);
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`else
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localparam L3_MEM_TAG_WIDTH = `CACHE_NC_BYPASS_TAG_WIDTH(L3_NUM_REQS, `L3_LINE_SIZE, L3_WORD_SIZE, L3_TAG_WIDTH);
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`endif
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/* verilator lint_on UNUSED */
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/////////////////////////////// Issue parameters //////////////////////////
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localparam ISSUE_ISW = `CLOG2(`ISSUE_WIDTH);
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localparam ISSUE_ISW_W = `UP(ISSUE_ISW);
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localparam ISSUE_RATIO = `NUM_WARPS / `ISSUE_WIDTH;
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localparam ISSUE_WIS = `CLOG2(ISSUE_RATIO);
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localparam ISSUE_WIS_W = `UP(ISSUE_WIS);
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`IGNORE_UNUSED_BEGIN
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function logic [`NW_WIDTH-1:0] wis_to_wid(
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input logic [ISSUE_WIS_W-1:0] wis,
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input logic [ISSUE_ISW_W-1:0] isw
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);
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if (ISSUE_WIS == 0) begin
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wis_to_wid = `NW_WIDTH'(isw);
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end else if (ISSUE_ISW == 0) begin
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wis_to_wid = `NW_WIDTH'(wis);
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end else begin
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wis_to_wid = `NW_WIDTH'({wis, isw});
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end
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endfunction
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function logic [ISSUE_ISW_W-1:0] wid_to_isw(
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input logic [`NW_WIDTH-1:0] wid
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);
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if (ISSUE_ISW != 0) begin
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wid_to_isw = wid[ISSUE_ISW_W-1:0];
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end else begin
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wid_to_isw = 0;
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end
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endfunction
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function logic [ISSUE_WIS_W-1:0] wid_to_wis(
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input logic [`NW_WIDTH-1:0] wid
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);
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if (ISSUE_WIS != 0) begin
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wid_to_wis = ISSUE_WIS_W'(wid >> ISSUE_ISW);
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end else begin
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wid_to_wis = 0;
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end
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endfunction
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`IGNORE_UNUSED_END
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endpackage
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`endif // VX_GPU_PKG_VH
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