d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
52 lines
1.5 KiB
Systemverilog
52 lines
1.5 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_cache_define.vh"
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module VX_cache_init #(
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// Size of cache in bytes
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parameter CACHE_SIZE = 1024,
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// Size of line inside a bank in bytes
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parameter LINE_SIZE = 16,
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// Number of banks
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parameter NUM_BANKS = 1,
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// Number of associative ways
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parameter NUM_WAYS = 1
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) (
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input wire clk,
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input wire reset,
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output wire [`CS_LINE_SEL_BITS-1:0] addr_out,
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output wire valid_out
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);
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reg enabled;
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reg [`CS_LINE_SEL_BITS-1:0] line_ctr;
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always @(posedge clk) begin
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if (reset) begin
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enabled <= 1;
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line_ctr <= '0;
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end else begin
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if (enabled) begin
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if (line_ctr == ((2 ** `CS_LINE_SEL_BITS)-1)) begin
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enabled <= 0;
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end
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line_ctr <= line_ctr + `CS_LINE_SEL_BITS'(1);
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end
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end
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end
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assign addr_out = line_ctr;
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assign valid_out = enabled;
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endmodule
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