d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
78 lines
2.4 KiB
Verilog
78 lines
2.4 KiB
Verilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`timescale 1ns/1ns
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`include "VX_fifo_queue.v"
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`define check(x, y) if ((x == y) !== 1) if ((x == y) === 0) $error("x=%h, expected=%h", x, y); else $warning("x=%h, expected=%h", x, y)
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module testbench();
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reg clk;
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reg reset;
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reg[3:0] data_in;
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reg push;
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reg pop;
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wire[3:0] data_out;
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wire full;
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wire empty;
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VX_fifo_queue #(
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.DATAW (4),
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.DEPTH (4)
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) dut (
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.clk(clk),
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.reset(reset),
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.data_in(data_in),
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.push(push),
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.pop(pop),
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.data_out(data_out),
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.empty(empty),
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.full(full),
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`UNUSED_PIN (alm_empty),
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`UNUSED_PIN (alm_full),
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`UNUSED_VAR (size)
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);
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always begin
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#1 clk = !clk;
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end
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initial begin
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$monitor ("%d: clk=%b rst=%b push=%b, pop=%b, din=%h, empty=%b, full=%b, dout=%h",
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$time, clk, reset, push, pop, data_in, empty, full, data_out);
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#0 clk=0; reset=1; pop=0; push=0;
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#2 reset=0; data_in=4'ha; pop=0; push=1;
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#2 `check(full, 0); `check(data_out, 4'ha); `check(empty, 0);
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#0 data_in=4'hb;
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#2 `check(full, 0); `check(data_out, 4'ha); `check(empty, 0);
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#0 data_in=4'hc;
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#2 `check(full, 0); `check(data_out, 4'ha); `check(empty, 0);
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#0 data_in=4'hd;
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#2 `check(full, 1); `check(data_out, 4'ha); `check(empty, 0);
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#0 push=0; pop=1;
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#2 `check(full, 0); `check(data_out, 4'hb); `check(empty, 0);
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#2 `check(full, 0); `check(data_out, 4'hc); `check(empty, 0);
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#2 `check(full, 0); `check(data_out, 4'hd); `check(empty, 0);
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#2 `check(full, 0); `check(data_out, 4'ha); `check(empty, 1);
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#0 data_in=4'he; push=1; pop=0;
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#2 `check(full, 0); `check(data_out, 4'he); `check(empty, 0);
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#0 data_in=4'hf; pop=1;
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#2 `check(full, 0); `check(data_out, 4'hf); `check(empty, 0);
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#0 push=0;
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#2 `check(full, 0); `check(data_out, 4'hc); `check(empty, 1);
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#1 $finish;
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end
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endmodule
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