504 lines
19 KiB
C++
504 lines
19 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "utils.h"
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#include <iostream>
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#include <fstream>
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#include <list>
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#include <cstring>
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#include <vector>
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#include <vortex.h>
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#include <assert.h>
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#define RT_CHECK(_expr, _cleanup) \
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do { \
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int _ret = _expr; \
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if (0 == _ret) \
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break; \
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printf("Error: '%s' returned %d!\n", #_expr, (int)_ret); \
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_cleanup \
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} while (false)
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uint64_t aligned_size(uint64_t size, uint64_t alignment) {
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assert(0 == (alignment & (alignment - 1)));
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return (size + alignment - 1) & ~(alignment - 1);
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}
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bool is_aligned(uint64_t addr, uint64_t alignment) {
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assert(0 == (alignment & (alignment - 1)));
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return 0 == (addr & (alignment - 1));
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}
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///////////////////////////////////////////////////////////////////////////////
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class AutoPerfDump {
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public:
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AutoPerfDump() : perf_class_(0) {}
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~AutoPerfDump() {
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for (auto hdevice : hdevices_) {
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vx_dump_perf(hdevice, stdout);
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}
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}
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void add_device(vx_device_h hdevice) {
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auto perf_class_s = getenv("PERF_CLASS");
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if (perf_class_s) {
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perf_class_ = std::atoi(perf_class_s);
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vx_dcr_write(hdevice, VX_DCR_BASE_MPM_CLASS, perf_class_);
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}
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hdevices_.push_back(hdevice);
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}
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void remove_device(vx_device_h hdevice) {
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hdevices_.remove(hdevice);
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vx_dump_perf(hdevice, stdout);
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}
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int get_perf_class() const {
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return perf_class_;
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}
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private:
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std::list<vx_device_h> hdevices_;
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int perf_class_;
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};
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#ifdef DUMP_PERF_STATS
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AutoPerfDump gAutoPerfDump;
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#endif
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void perf_add_device(vx_device_h hdevice) {
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#ifdef DUMP_PERF_STATS
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gAutoPerfDump.add_device(hdevice);
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#else
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(void)hdevice;
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#endif
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}
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void perf_remove_device(vx_device_h hdevice) {
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#ifdef DUMP_PERF_STATS
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gAutoPerfDump.remove_device(hdevice);
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#else
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(void)hdevice;
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#endif
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}
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///////////////////////////////////////////////////////////////////////////////
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extern int vx_upload_kernel_bytes(vx_device_h hdevice, const void* content, uint64_t size) {
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int err = 0;
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if (NULL == content || 0 == size)
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return -1;
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uint64_t kernel_base_addr;
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err = vx_dev_caps(hdevice, VX_CAPS_KERNEL_BASE_ADDR, &kernel_base_addr);
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if (err != 0)
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return err;
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return vx_copy_to_dev(hdevice, kernel_base_addr, content, size);
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}
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extern int vx_upload_kernel_file(vx_device_h hdevice, const char* filename) {
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std::ifstream ifs(filename);
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if (!ifs) {
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std::cout << "error: " << filename << " not found" << std::endl;
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return -1;
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}
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// read file content
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ifs.seekg(0, ifs.end);
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auto size = ifs.tellg();
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auto content = new char [size];
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ifs.seekg(0, ifs.beg);
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ifs.read(content, size);
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// upload
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int err = vx_upload_kernel_bytes(hdevice, content, size);
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// release buffer
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delete[] content;
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return err;
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}
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///////////////////////////////////////////////////////////////////////////////
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void DeviceConfig::write(uint32_t addr, uint32_t value) {
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data_[addr] = value;
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}
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uint32_t DeviceConfig::read(uint32_t addr) const {
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if (0 == data_.count(addr)) {
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printf("Error: DeviceConfig::read(%d) failed\n", addr);
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}
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return data_.at(addr);
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}
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int dcr_initialize(vx_device_h hdevice) {
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const uint64_t startup_addr(STARTUP_ADDR);
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RT_CHECK(vx_dcr_write(hdevice, VX_DCR_BASE_STARTUP_ADDR0, startup_addr & 0xffffffff), {
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return -1;
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});
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RT_CHECK(vx_dcr_write(hdevice, VX_DCR_BASE_STARTUP_ADDR1, startup_addr >> 32), {
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return -1;
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});
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RT_CHECK(vx_dcr_write(hdevice, VX_DCR_BASE_MPM_CLASS, 0), {
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return -1;
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});
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return 0;
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}
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///////////////////////////////////////////////////////////////////////////////
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static uint64_t get_csr_64(const void* ptr, int addr) {
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auto w_ptr = reinterpret_cast<const uint32_t*>(ptr);
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uint32_t value_lo = w_ptr[addr - VX_CSR_MPM_BASE];
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uint32_t value_hi = w_ptr[addr - VX_CSR_MPM_BASE + 32];
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return (uint64_t(value_hi) << 32) | value_lo;
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}
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extern int vx_dump_perf(vx_device_h hdevice, FILE* stream) {
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int ret = 0;
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uint64_t instrs = 0;
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uint64_t cycles = 0;
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#ifdef PERF_ENABLE
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auto calcRatio = [&](uint64_t part, uint64_t total)->int {
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if (total == 0)
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return 0;
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return int((1.0 - (double(part) / double(total))) * 100);
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};
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auto caclAvgLatency = [&](uint64_t sum, uint64_t requests)->int {
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if (requests == 0)
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return 0;
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return int(double(sum) / double(requests));
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};
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auto calcUtilization = [&](uint64_t count, uint64_t stalls)->int {
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if (count == 0)
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return 0;
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return int((double(count) / double(count + stalls)) * 100);
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};
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auto perf_class = gAutoPerfDump.get_perf_class();
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// PERF: pipeline stalls
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uint64_t ibuffer_stalls = 0;
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uint64_t scoreboard_stalls = 0;
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uint64_t lsu_stalls = 0;
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uint64_t fpu_stalls = 0;
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uint64_t alu_stalls = 0;
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uint64_t sfu_stalls = 0;
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uint64_t ifetches = 0;
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uint64_t loads = 0;
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uint64_t stores = 0;
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uint64_t ifetch_lat = 0;
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uint64_t load_lat = 0;
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// PERF: l2cache
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uint64_t l2cache_reads = 0;
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uint64_t l2cache_writes = 0;
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uint64_t l2cache_read_misses = 0;
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uint64_t l2cache_write_misses = 0;
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uint64_t l2cache_bank_stalls = 0;
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uint64_t l2cache_mshr_stalls = 0;
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// PERF: l3cache
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uint64_t l3cache_reads = 0;
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uint64_t l3cache_writes = 0;
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uint64_t l3cache_read_misses = 0;
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uint64_t l3cache_write_misses = 0;
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uint64_t l3cache_bank_stalls = 0;
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uint64_t l3cache_mshr_stalls = 0;
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// PERF: memory
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uint64_t mem_reads = 0;
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uint64_t mem_writes = 0;
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uint64_t mem_lat = 0;
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#endif
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uint64_t num_cores;
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ret = vx_dev_caps(hdevice, VX_CAPS_NUM_CORES, &num_cores);
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if (ret != 0)
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return ret;
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#ifdef PERF_ENABLE
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uint64_t isa_flags;
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ret = vx_dev_caps(hdevice, VX_CAPS_ISA_FLAGS, &isa_flags);
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if (ret != 0)
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return ret;
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bool icache_enable = isa_flags & VX_ISA_EXT_ICACHE;
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bool dcache_enable = isa_flags & VX_ISA_EXT_DCACHE;
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bool l2cache_enable = isa_flags & VX_ISA_EXT_L2CACHE;
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bool l3cache_enable = isa_flags & VX_ISA_EXT_L3CACHE;
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bool smem_enable = isa_flags & VX_ISA_EXT_SMEM;
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#endif
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std::vector<uint8_t> staging_buf(64* sizeof(uint32_t));
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for (unsigned core_id = 0; core_id < num_cores; ++core_id) {
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uint64_t mpm_mem_addr = IO_CSR_ADDR + core_id * staging_buf.size();
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ret = vx_copy_from_dev(hdevice, staging_buf.data(), mpm_mem_addr, staging_buf.size());
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if (ret != 0)
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return ret;
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#ifdef PERF_ENABLE
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switch (perf_class) {
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case VX_DCR_MPM_CLASS_CORE: {
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// PERF: pipeline
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// ibuffer_stall
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uint64_t ibuffer_stalls_per_core = get_csr_64(staging_buf.data(), VX_CSR_MPM_IBUF_ST);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: ibuffer stalls=%ld\n", core_id, ibuffer_stalls_per_core);
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ibuffer_stalls += ibuffer_stalls_per_core;
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// scoreboard_stall
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uint64_t scoreboard_stalls_per_core = get_csr_64(staging_buf.data(), VX_CSR_MPM_SCRB_ST);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: scoreboard stalls=%ld\n", core_id, scoreboard_stalls_per_core);
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scoreboard_stalls += scoreboard_stalls_per_core;
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// alu_stall
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uint64_t alu_stalls_per_core = get_csr_64(staging_buf.data(), VX_CSR_MPM_ALU_ST);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: alu unit stalls=%ld\n", core_id, alu_stalls_per_core);
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alu_stalls += alu_stalls_per_core;
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// lsu_stall
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uint64_t lsu_stalls_per_core = get_csr_64(staging_buf.data(), VX_CSR_MPM_LSU_ST);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: lsu unit stalls=%ld\n", core_id, lsu_stalls_per_core);
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lsu_stalls += lsu_stalls_per_core;
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// fpu_stall
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uint64_t fpu_stalls_per_core = get_csr_64(staging_buf.data(), VX_CSR_MPM_FPU_ST);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: fpu unit stalls=%ld\n", core_id, fpu_stalls_per_core);
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fpu_stalls += fpu_stalls_per_core;
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// sfu_stall
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uint64_t sfu_stalls_per_core = get_csr_64(staging_buf.data(), VX_CSR_MPM_SFU_ST);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: sfu unit stalls=%ld\n", core_id, sfu_stalls_per_core);
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sfu_stalls += sfu_stalls_per_core;
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// PERF: memory
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// ifetches
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uint64_t ifetches_per_core = get_csr_64(staging_buf.data(), VX_CSR_MPM_LOADS);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: ifetches=%ld\n", core_id, ifetches_per_core);
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ifetches += ifetches_per_core;
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// loads
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uint64_t loads_per_core = get_csr_64(staging_buf.data(), VX_CSR_MPM_LOADS);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: loads=%ld\n", core_id, loads_per_core);
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loads += loads_per_core;
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// stores
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uint64_t stores_per_core = get_csr_64(staging_buf.data(), VX_CSR_MPM_STORES);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: stores=%ld\n", core_id, stores_per_core);
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stores += stores_per_core;
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// ifetch latency
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uint64_t ifetch_lat_per_core = get_csr_64(staging_buf.data(), VX_CSR_MPM_IFETCH_LAT);
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if (num_cores > 1) {
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int mem_avg_lat = caclAvgLatency(ifetch_lat_per_core, ifetches_per_core);
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fprintf(stream, "PERF: core%d: ifetch latency=%d cycles\n", core_id, mem_avg_lat);
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}
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ifetch_lat += ifetch_lat_per_core;
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// load latency
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uint64_t load_lat_per_core = get_csr_64(staging_buf.data(), VX_CSR_MPM_LOAD_LAT);
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if (num_cores > 1) {
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int mem_avg_lat = caclAvgLatency(load_lat_per_core, loads_per_core);
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fprintf(stream, "PERF: core%d: load latency=%d cycles\n", core_id, mem_avg_lat);
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}
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load_lat += load_lat_per_core;
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} break;
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case VX_DCR_MPM_CLASS_MEM: {
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if (smem_enable) {
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// PERF: smem
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uint64_t smem_reads = get_csr_64(staging_buf.data(), VX_CSR_MPM_SMEM_READS);
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uint64_t smem_writes = get_csr_64(staging_buf.data(), VX_CSR_MPM_SMEM_WRITES);
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uint64_t smem_bank_stalls = get_csr_64(staging_buf.data(), VX_CSR_MPM_SMEM_BANK_ST);
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int smem_bank_utilization = calcUtilization(smem_reads + smem_writes, smem_bank_stalls);
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fprintf(stream, "PERF: core%d: smem reads=%ld\n", core_id, smem_reads);
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fprintf(stream, "PERF: core%d: smem writes=%ld\n", core_id, smem_writes);
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fprintf(stream, "PERF: core%d: smem bank stalls=%ld (utilization=%d%%)\n", core_id, smem_bank_stalls, smem_bank_utilization);
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}
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if (icache_enable) {
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// PERF: Icache
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uint64_t icache_reads = get_csr_64(staging_buf.data(), VX_CSR_MPM_ICACHE_READS);
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uint64_t icache_read_misses = get_csr_64(staging_buf.data(), VX_CSR_MPM_ICACHE_MISS_R);
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int icache_read_hit_ratio = calcRatio(icache_read_misses, icache_reads);
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fprintf(stream, "PERF: core%d: icache reads=%ld\n", core_id, icache_reads);
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fprintf(stream, "PERF: core%d: icache read misses=%ld (hit ratio=%d%%)\n", core_id, icache_read_misses, icache_read_hit_ratio);
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}
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if (dcache_enable) {
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// PERF: Dcache
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uint64_t dcache_reads = get_csr_64(staging_buf.data(), VX_CSR_MPM_DCACHE_READS);
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uint64_t dcache_writes = get_csr_64(staging_buf.data(), VX_CSR_MPM_DCACHE_WRITES);
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uint64_t dcache_read_misses = get_csr_64(staging_buf.data(), VX_CSR_MPM_DCACHE_MISS_R);
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uint64_t dcache_write_misses = get_csr_64(staging_buf.data(), VX_CSR_MPM_DCACHE_MISS_W);
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uint64_t dcache_bank_stalls = get_csr_64(staging_buf.data(), VX_CSR_MPM_DCACHE_BANK_ST);
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uint64_t dcache_mshr_stalls = get_csr_64(staging_buf.data(), VX_CSR_MPM_DCACHE_MSHR_ST);
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int dcache_read_hit_ratio = calcRatio(dcache_read_misses, dcache_reads);
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int dcache_write_hit_ratio = calcRatio(dcache_write_misses, dcache_writes);
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int dcache_bank_utilization = calcUtilization(dcache_reads + dcache_writes, dcache_bank_stalls);
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fprintf(stream, "PERF: core%d: dcache reads=%ld\n", core_id, dcache_reads);
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fprintf(stream, "PERF: core%d: dcache writes=%ld\n", core_id, dcache_writes);
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fprintf(stream, "PERF: core%d: dcache read misses=%ld (hit ratio=%d%%)\n", core_id, dcache_read_misses, dcache_read_hit_ratio);
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fprintf(stream, "PERF: core%d: dcache write misses=%ld (hit ratio=%d%%)\n", core_id, dcache_write_misses, dcache_write_hit_ratio);
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fprintf(stream, "PERF: core%d: dcache bank stalls=%ld (utilization=%d%%)\n", core_id, dcache_bank_stalls, dcache_bank_utilization);
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fprintf(stream, "PERF: core%d: dcache mshr stalls=%ld\n", core_id, dcache_mshr_stalls);
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}
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if (l2cache_enable) {
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// PERF: L2cache
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l2cache_reads += get_csr_64(staging_buf.data(), VX_CSR_MPM_L2CACHE_READS);
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l2cache_writes += get_csr_64(staging_buf.data(), VX_CSR_MPM_L2CACHE_WRITES);
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l2cache_read_misses += get_csr_64(staging_buf.data(), VX_CSR_MPM_L2CACHE_MISS_R);
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l2cache_write_misses += get_csr_64(staging_buf.data(), VX_CSR_MPM_L2CACHE_MISS_W);
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l2cache_bank_stalls += get_csr_64(staging_buf.data(), VX_CSR_MPM_L2CACHE_BANK_ST);
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l2cache_mshr_stalls += get_csr_64(staging_buf.data(), VX_CSR_MPM_L2CACHE_MSHR_ST);
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}
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if (0 == core_id) {
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if (l3cache_enable) {
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// PERF: L3cache
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l3cache_reads = get_csr_64(staging_buf.data(), VX_CSR_MPM_L3CACHE_READS);
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l3cache_writes = get_csr_64(staging_buf.data(), VX_CSR_MPM_L3CACHE_WRITES);
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l3cache_read_misses = get_csr_64(staging_buf.data(), VX_CSR_MPM_L3CACHE_MISS_R);
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l3cache_write_misses = get_csr_64(staging_buf.data(), VX_CSR_MPM_L3CACHE_MISS_W);
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l3cache_bank_stalls = get_csr_64(staging_buf.data(), VX_CSR_MPM_L3CACHE_BANK_ST);
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l3cache_mshr_stalls = get_csr_64(staging_buf.data(), VX_CSR_MPM_L3CACHE_MSHR_ST);
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}
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// PERF: memory
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mem_reads = get_csr_64(staging_buf.data(), VX_CSR_MPM_MEM_READS);
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mem_writes = get_csr_64(staging_buf.data(), VX_CSR_MPM_MEM_WRITES);
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mem_lat = get_csr_64(staging_buf.data(), VX_CSR_MPM_MEM_LAT);
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}
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} break;
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default:
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break;
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}
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#endif
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uint64_t instrs_per_core = get_csr_64(staging_buf.data(), VX_CSR_MINSTRET);
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uint64_t cycles_per_core = get_csr_64(staging_buf.data(), VX_CSR_MCYCLE);
|
|
float IPC = (float)(double(instrs_per_core) / double(cycles_per_core));
|
|
if (num_cores > 1) fprintf(stream, "PERF: core%d: instrs=%ld, cycles=%ld, IPC=%f\n", core_id, instrs_per_core, cycles_per_core, IPC);
|
|
instrs += instrs_per_core;
|
|
cycles = std::max<uint64_t>(cycles_per_core, cycles);
|
|
}
|
|
|
|
#ifdef PERF_ENABLE
|
|
switch (perf_class) {
|
|
case VX_DCR_MPM_CLASS_CORE: {
|
|
int ifetch_avg_lat = (int)(double(ifetch_lat) / double(ifetches));
|
|
int load_avg_lat = (int)(double(load_lat) / double(loads));
|
|
fprintf(stream, "PERF: ibuffer stalls=%ld\n", ibuffer_stalls);
|
|
fprintf(stream, "PERF: scoreboard stalls=%ld\n", scoreboard_stalls);
|
|
fprintf(stream, "PERF: alu unit stalls=%ld\n", alu_stalls);
|
|
fprintf(stream, "PERF: lsu unit stalls=%ld\n", lsu_stalls);
|
|
fprintf(stream, "PERF: fpu unit stalls=%ld\n", fpu_stalls);
|
|
fprintf(stream, "PERF: sfu unit stalls=%ld\n", sfu_stalls);
|
|
fprintf(stream, "PERF: ifetches=%ld\n", ifetches);
|
|
fprintf(stream, "PERF: loads=%ld\n", loads);
|
|
fprintf(stream, "PERF: stores=%ld\n", stores);
|
|
fprintf(stream, "PERF: ifetch latency=%d cycles\n", ifetch_avg_lat);
|
|
fprintf(stream, "PERF: load latency=%d cycles\n", load_avg_lat);
|
|
} break;
|
|
case VX_DCR_MPM_CLASS_MEM: {
|
|
if (l2cache_enable) {
|
|
l2cache_reads /= num_cores;
|
|
l2cache_writes /= num_cores;
|
|
l2cache_read_misses /= num_cores;
|
|
l2cache_write_misses /= num_cores;
|
|
l2cache_bank_stalls /= num_cores;
|
|
l2cache_mshr_stalls /= num_cores;
|
|
int l2cache_read_hit_ratio = calcRatio(l2cache_read_misses, l2cache_reads);
|
|
int l2cache_write_hit_ratio = calcRatio(l2cache_write_misses, l2cache_writes);
|
|
int l2cache_bank_utilization = calcUtilization(l2cache_reads + l2cache_writes, l2cache_bank_stalls);
|
|
|
|
fprintf(stream, "PERF: l2cache reads=%ld\n", l2cache_reads);
|
|
fprintf(stream, "PERF: l2cache writes=%ld\n", l2cache_writes);
|
|
fprintf(stream, "PERF: l2cache read misses=%ld (hit ratio=%d%%)\n", l2cache_read_misses, l2cache_read_hit_ratio);
|
|
fprintf(stream, "PERF: l2cache write misses=%ld (hit ratio=%d%%)\n", l2cache_write_misses, l2cache_write_hit_ratio);
|
|
fprintf(stream, "PERF: l2cache bank stalls=%ld (utilization=%d%%)\n", l2cache_bank_stalls, l2cache_bank_utilization);
|
|
fprintf(stream, "PERF: l2cache mshr stalls=%ld\n", l2cache_mshr_stalls);
|
|
}
|
|
|
|
if (l3cache_enable) {
|
|
int l3cache_read_hit_ratio = calcRatio(l3cache_read_misses, l3cache_reads);
|
|
int l3cache_write_hit_ratio = calcRatio(l3cache_write_misses, l3cache_writes);
|
|
int l3cache_bank_utilization = calcUtilization(l3cache_reads + l3cache_writes, l3cache_bank_stalls);
|
|
fprintf(stream, "PERF: l3cache reads=%ld\n", l3cache_reads);
|
|
fprintf(stream, "PERF: l3cache writes=%ld\n", l3cache_writes);
|
|
fprintf(stream, "PERF: l3cache read misses=%ld (hit ratio=%d%%)\n", l3cache_read_misses, l3cache_read_hit_ratio);
|
|
fprintf(stream, "PERF: l3cache write misses=%ld (hit ratio=%d%%)\n", l3cache_write_misses, l3cache_write_hit_ratio);
|
|
fprintf(stream, "PERF: l3cache bank stalls=%ld (utilization=%d%%)\n", l3cache_bank_stalls, l3cache_bank_utilization);
|
|
fprintf(stream, "PERF: l3cache mshr stalls=%ld\n", l3cache_mshr_stalls);
|
|
}
|
|
|
|
int mem_avg_lat = caclAvgLatency(mem_lat, mem_reads);
|
|
fprintf(stream, "PERF: memory requests=%ld (reads=%ld, writes=%ld)\n", (mem_reads + mem_writes), mem_reads, mem_writes);
|
|
fprintf(stream, "PERF: memory latency=%d cycles\n", mem_avg_lat);
|
|
} break;
|
|
default:
|
|
break;
|
|
}
|
|
#endif
|
|
|
|
float IPC = (float)(double(instrs) / double(cycles));
|
|
fprintf(stream, "PERF: instrs=%ld, cycles=%ld, IPC=%f\n", instrs, cycles, IPC);
|
|
|
|
fflush(stream);
|
|
|
|
return 0;
|
|
}
|
|
|
|
extern int vx_perf_counter(vx_device_h hdevice, int counter, int core_id, uint64_t* value) {
|
|
int ret = 0;
|
|
uint64_t num_cores;
|
|
ret = vx_dev_caps(hdevice, VX_CAPS_NUM_CORES, &num_cores);
|
|
if (ret != 0)
|
|
return ret;
|
|
|
|
if (core_id >= (int)num_cores) {
|
|
std::cout << "error: core_id out of range" << std::endl;
|
|
return -1;
|
|
}
|
|
|
|
std::vector<uint8_t> staging_buf(64 * sizeof(uint32_t));
|
|
|
|
uint64_t _value = 0;
|
|
|
|
unsigned i = 0;
|
|
if (core_id != -1) {
|
|
i = core_id;
|
|
num_cores = core_id + 1;
|
|
}
|
|
|
|
for (i = 0; i < num_cores; ++i) {
|
|
uint64_t mpm_mem_addr = IO_CSR_ADDR + i * staging_buf.size();
|
|
ret = vx_copy_from_dev(hdevice, staging_buf.data(), mpm_mem_addr, staging_buf.size());
|
|
if (ret != 0)
|
|
return ret;
|
|
|
|
auto per_core_value = get_csr_64(staging_buf.data(), counter);
|
|
if (counter == VX_CSR_MCYCLE) {
|
|
_value = std::max<uint64_t>(per_core_value, _value);
|
|
} else {
|
|
_value += per_core_value;
|
|
}
|
|
}
|
|
|
|
// output
|
|
*value = _value;
|
|
|
|
return 0;
|
|
}
|