49275 lines
2.4 MiB
49275 lines
2.4 MiB
LD_LIBRARY_PATH=../../sw/simx:/home/blaise/dev/cash/build/lib:/opt/systemc/lib: ./demo -f kernel.bin
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open device connection
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upload program
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Device ready...
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allocate device memory
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allocate shared memory
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populate source buffer values
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upload source buffers
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upload kernel argument
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start device
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wait for completion
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Device running...
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DEBUG ../../../../simX/core.cpp:712: Creating a new thread with PC: 80000000
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DEBUG ../../../../simX/core.cpp:712: Creating a new thread with PC: 80000000
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DEBUG ../../../../simX/core.cpp:712: Creating a new thread with PC: 80000000
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DEBUG ../../../../simX/core.cpp:712: Creating a new thread with PC: 80000000
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DEBUG ../../../../simX/core.cpp:170: ###########################################################
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DEBUG ../../../../simX/core.cpp:174: cycle: 1
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DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
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DEBUG ../../../../simX/core.cpp:750: current PC=0x80000000
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DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x597 into: auipc
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DEBUG ../../../../simX/instruction.cpp:753: AUIPC: r11 <- imm=0x0
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DEBUG ../../../../simX/core.cpp:781: Register state:
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%r 0: 00000000 (0)
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%r 1: 00000000 (0)
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%r 2: 00000000 (0)
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%r 3: 00000000 (0)
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%r 4: 00000000 (0)
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%r 5: 00000000 (0)
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%r 6: 00000000 (0)
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%r 7: 00000000 (0)
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%r 8: 00000000 (0)
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%r 9: 00000000 (0)
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%r10: 00000000 (0)
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%r11: 80000000 (0)
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%r12: 00000000 (0)
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%r13: 00000000 (0)
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%r14: 00000000 (0)
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%r15: 00000000 (0)
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%r16: 00000000 (0)
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%r17: 00000000 (0)
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%r18: 00000000 (0)
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%r19: 00000000 (0)
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%r20: 00000000 (0)
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%r21: 00000000 (0)
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%r22: 00000000 (0)
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%r23: 00000000 (0)
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%r24: 00000000 (0)
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%r25: 00000000 (0)
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%r26: 00000000 (0)
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%r27: 00000000 (0)
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%r28: 00000000 (0)
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%r29: 00000000 (0)
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%r30: 00000000 (0)
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%r31: 00000000 (0)
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DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
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DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
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DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000000
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DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
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DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=-1, trs2=-1
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DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
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DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
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DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
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DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
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DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
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DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
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DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
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DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
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DEBUG ../../../../simX/core.cpp:170: ###########################################################
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DEBUG ../../../../simX/core.cpp:174: cycle: 2
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DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
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DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
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DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000000
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DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
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DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=-1, trs2=-1
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DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
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DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
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DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
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DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
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DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
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DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
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DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
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DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
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DEBUG ../../../../simX/core.cpp:170: ###########################################################
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DEBUG ../../../../simX/core.cpp:174: cycle: 3
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DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
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DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
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DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000000
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DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
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DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=-1, trs2=-1
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DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
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DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
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DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
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DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
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DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
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DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
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DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
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DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
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DEBUG ../../../../simX/core.cpp:170: ###########################################################
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DEBUG ../../../../simX/core.cpp:174: cycle: 4
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DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
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DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
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DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000000
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DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
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DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=-1, trs2=-1
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DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
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DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
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DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
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DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
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DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
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DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
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DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
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DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
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DEBUG ../../../../simX/core.cpp:170: ###########################################################
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DEBUG ../../../../simX/core.cpp:174: cycle: 5
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DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
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DEBUG ../../../../simX/core.cpp:750: current PC=0x80000004
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DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x7c58593 into: i_type
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DEBUG ../../../../simX/instruction.cpp:586: ADDI: r11 <- r11, imm=124
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DEBUG ../../../../simX/core.cpp:781: Register state:
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%r 0: 00000000 (0)
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%r 1: 00000000 (0)
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%r 2: 00000000 (0)
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%r 3: 00000000 (0)
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%r 4: 00000000 (0)
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%r 5: 00000000 (0)
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%r 6: 00000000 (0)
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%r 7: 00000000 (0)
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%r 8: 00000000 (0)
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%r 9: 00000000 (0)
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%r10: 00000000 (0)
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%r11: 8000007c (0)
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%r12: 00000000 (0)
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%r13: 00000000 (0)
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%r14: 00000000 (0)
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%r15: 00000000 (0)
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%r16: 00000000 (0)
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%r17: 00000000 (0)
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%r18: 00000000 (0)
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%r19: 00000000 (0)
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%r20: 00000000 (0)
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%r21: 00000000 (0)
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%r22: 00000000 (0)
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%r23: 00000000 (0)
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%r24: 00000000 (0)
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%r25: 00000000 (0)
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%r26: 00000000 (0)
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%r27: 00000000 (0)
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%r28: 00000000 (0)
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%r29: 00000000 (0)
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%r30: 00000000 (0)
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%r31: 00000000 (0)
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DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
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DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
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DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000004
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DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
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DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=11, trs2=-1
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DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
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DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
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DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
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DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
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DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
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DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
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DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
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DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
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DEBUG ../../../../simX/core.cpp:170: ###########################################################
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DEBUG ../../../../simX/core.cpp:174: cycle: 6
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DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
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DEBUG ../../../../simX/core.cpp:750: current PC=0x80000008
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DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x800513 into: i_type
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DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=8
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DEBUG ../../../../simX/core.cpp:781: Register state:
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%r 0: 00000000 (0)
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%r 1: 00000000 (0)
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%r 2: 00000000 (0)
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%r 3: 00000000 (0)
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%r 4: 00000000 (0)
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%r 5: 00000000 (0)
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%r 6: 00000000 (0)
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%r 7: 00000000 (0)
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%r 8: 00000000 (0)
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%r 9: 00000000 (0)
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%r10: 00000008 (0)
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%r11: 8000007c (0)
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%r12: 00000000 (0)
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%r13: 00000000 (0)
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%r14: 00000000 (0)
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%r15: 00000000 (0)
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%r16: 00000000 (0)
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%r17: 00000000 (0)
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%r18: 00000000 (0)
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%r19: 00000000 (0)
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%r20: 00000000 (0)
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%r21: 00000000 (0)
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%r22: 00000000 (0)
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%r23: 00000000 (0)
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%r24: 00000000 (0)
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%r25: 00000000 (0)
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%r26: 00000000 (0)
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%r27: 00000000 (0)
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%r28: 00000000 (0)
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%r29: 00000000 (0)
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%r30: 00000000 (0)
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%r31: 00000000 (0)
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DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
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DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
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DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000008
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DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
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DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
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DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
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DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
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DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
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DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
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DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
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DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
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DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
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DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
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DEBUG ../../../../simX/core.cpp:170: ###########################################################
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DEBUG ../../../../simX/core.cpp:174: cycle: 7
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DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
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DEBUG ../../../../simX/core.cpp:750: current PC=0x8000000c
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DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb5106b into: gpgpu
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DEBUG ../../../../simX/instruction.cpp:885: WSPAWN: r10, r11
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DEBUG ../../../../simX/instruction.cpp:890: Spawning 4 new warps at PC: 8000007c
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DEBUG ../../../../simX/core.cpp:781: Register state:
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%r 0: 00000000 (0)
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%r 1: 00000000 (0)
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%r 2: 00000000 (0)
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%r 3: 00000000 (0)
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%r 4: 00000000 (0)
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%r 5: 00000000 (0)
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%r 6: 00000000 (0)
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%r 7: 00000000 (0)
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%r 8: 00000000 (0)
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%r 9: 00000000 (0)
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%r10: 00000008 (0)
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%r11: 8000007c (0)
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%r12: 00000000 (0)
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%r13: 00000000 (0)
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%r14: 00000000 (0)
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%r15: 00000000 (0)
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%r16: 00000000 (0)
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%r17: 00000000 (0)
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%r18: 00000000 (0)
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%r19: 00000000 (0)
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%r20: 00000000 (0)
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%r21: 00000000 (0)
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%r22: 00000000 (0)
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%r23: 00000000 (0)
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%r24: 00000000 (0)
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%r25: 00000000 (0)
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%r26: 00000000 (0)
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%r27: 00000000 (0)
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%r28: 00000000 (0)
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%r29: 00000000 (0)
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%r30: 00000000 (0)
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%r31: 00000000 (0)
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DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
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DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
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DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000000c
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DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
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DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=11
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DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
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DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
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DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
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DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
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DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
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DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=1
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DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
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DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
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DEBUG ../../../../simX/core.cpp:170: ###########################################################
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DEBUG ../../../../simX/core.cpp:174: cycle: 8
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DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
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DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
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DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
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DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000000c
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DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
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DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=11
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DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
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DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
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DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
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DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
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DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
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DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=1
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DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
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DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
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DEBUG ../../../../simX/core.cpp:170: ###########################################################
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DEBUG ../../../../simX/core.cpp:174: cycle: 9
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DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
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DEBUG ../../../../simX/core.cpp:750: current PC=0x8000007c
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DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x400513 into: i_type
|
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DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=4
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DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 00000000 (0)
|
|
%r 2: 00000000 (0)
|
|
%r 3: 00000000 (0)
|
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%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
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%r 6: 00000000 (0)
|
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%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
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%r 9: 00000000 (0)
|
|
%r10: 00000004 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
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%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
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DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000007c
|
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DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
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DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
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DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
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DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
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DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
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DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 10
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000007c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
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DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 11
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000007c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 12
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000007c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 13
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000007c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x400513 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 00000000 (0)
|
|
%r 2: 00000000 (0)
|
|
%r 3: 00000000 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 00000000 (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000004 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000007c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 14
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000007c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x400513 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 00000000 (0)
|
|
%r 2: 00000000 (0)
|
|
%r 3: 00000000 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 00000000 (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000004 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000007c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 15
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000010
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x6c000ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=108
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 8000007c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000014 (0)
|
|
%r 2: 00000000 (0)
|
|
%r 3: 00000000 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 00000000 (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000008 (0)
|
|
%r11: 8000007c (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000010
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 16
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000080
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x5006b into: gpgpu
|
|
DEBUG ../../../../simX/instruction.cpp:982: TMC: r10
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 00000000 00000000 00000000 00000000 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000000 00000000 00000000 (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:416: ** warp #1 active threads changed from 1 to 4
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000080
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 17
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000080
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 18
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000080
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 19
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000080
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 20
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000080
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x5006b into: gpgpu
|
|
DEBUG ../../../../simX/instruction.cpp:982: TMC: r10
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 00000000 00000000 00000000 00000000 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000000 00000000 00000000 (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:416: ** warp #2 active threads changed from 1 to 4
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000080
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 21
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000080
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x5006b into: gpgpu
|
|
DEBUG ../../../../simX/instruction.cpp:982: TMC: r10
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 00000000 00000000 00000000 00000000 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000000 00000000 00000000 (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:416: ** warp #3 active threads changed from 1 to 4
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000080
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 22
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000007c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x400513 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000014 (0)
|
|
%r 2: 00000000 (0)
|
|
%r 3: 00000000 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 00000000 (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000004 (0)
|
|
%r11: 8000007c (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000007c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 23
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000080
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x5006b into: gpgpu
|
|
DEBUG ../../../../simX/instruction.cpp:982: TMC: r10
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000014 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 00000000 00000000 00000000 00000000 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 8000007c 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000000 00000000 00000000 (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:416: ** warp #0 active threads changed from 1 to 4
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000080
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 24
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 25
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000084
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x17197 into: auipc
|
|
DEBUG ../../../../simX/instruction.cpp:753: AUIPC: r3 <- imm=0x17
|
|
DEBUG ../../../../simX/instruction.cpp:753: AUIPC: r3 <- imm=0x17
|
|
DEBUG ../../../../simX/instruction.cpp:753: AUIPC: r3 <- imm=0x17
|
|
DEBUG ../../../../simX/instruction.cpp:753: AUIPC: r3 <- imm=0x17
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80017084 80017084 80017084 80017084 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000000 00000000 00000000 (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000084
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=3, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 26
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 1
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000084
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=3, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 27
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000084
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x17197 into: auipc
|
|
DEBUG ../../../../simX/instruction.cpp:753: AUIPC: r3 <- imm=0x17
|
|
DEBUG ../../../../simX/instruction.cpp:753: AUIPC: r3 <- imm=0x17
|
|
DEBUG ../../../../simX/instruction.cpp:753: AUIPC: r3 <- imm=0x17
|
|
DEBUG ../../../../simX/instruction.cpp:753: AUIPC: r3 <- imm=0x17
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80017084 80017084 80017084 80017084 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000000 00000000 00000000 (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000084
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=3, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 28
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000084
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x17197 into: auipc
|
|
DEBUG ../../../../simX/instruction.cpp:753: AUIPC: r3 <- imm=0x17
|
|
DEBUG ../../../../simX/instruction.cpp:753: AUIPC: r3 <- imm=0x17
|
|
DEBUG ../../../../simX/instruction.cpp:753: AUIPC: r3 <- imm=0x17
|
|
DEBUG ../../../../simX/instruction.cpp:753: AUIPC: r3 <- imm=0x17
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80017084 80017084 80017084 80017084 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000000 00000000 00000000 (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000084
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=3, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 29
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000088
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb2418193 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r3 <- r3, imm=4294966052
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r3 <- r3, imm=4294966052
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r3 <- r3, imm=4294966052
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r3 <- r3, imm=4294966052
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000000 00000000 00000000 (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000088
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=3, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 30
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000088
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb2418193 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r3 <- r3, imm=4294966052
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r3 <- r3, imm=4294966052
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r3 <- r3, imm=4294966052
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r3 <- r3, imm=4294966052
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000000 00000000 00000000 (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000088
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=3, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 31
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000088
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb2418193 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r3 <- r3, imm=4294966052
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r3 <- r3, imm=4294966052
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r3 <- r3, imm=4294966052
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r3 <- r3, imm=4294966052
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000000 00000000 00000000 (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000088
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=3, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 32
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000084
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x17197 into: auipc
|
|
DEBUG ../../../../simX/instruction.cpp:753: AUIPC: r3 <- imm=0x17
|
|
DEBUG ../../../../simX/instruction.cpp:753: AUIPC: r3 <- imm=0x17
|
|
DEBUG ../../../../simX/instruction.cpp:753: AUIPC: r3 <- imm=0x17
|
|
DEBUG ../../../../simX/instruction.cpp:753: AUIPC: r3 <- imm=0x17
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000014 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80017084 80017084 80017084 80017084 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 8000007c 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000000 00000000 00000000 (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000084
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=3, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 33
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000008c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x22026f3 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r13=1
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r13=1
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r13=1
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r13=1
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000000 00000000 00000000 (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000008c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 34
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000008c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x22026f3 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r13=2
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r13=2
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r13=2
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r13=2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000000 00000000 00000000 (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000008c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 35
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000008c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x22026f3 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r13=3
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r13=3
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r13=3
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r13=3
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000000 00000000 00000000 (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000008c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 36
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000088
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb2418193 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r3 <- r3, imm=4294966052
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r3 <- r3, imm=4294966052
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r3 <- r3, imm=4294966052
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r3 <- r3, imm=4294966052
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000014 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 8000007c 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000000 00000000 00000000 (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000088
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=3, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 37
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000090
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1a69693 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x1a
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x1a
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x1a
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x1a
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000000 00000000 00000000 (0)
|
|
%r13: 04000000 04000000 04000000 04000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000090
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=13, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 38
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000090
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1a69693 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x1a
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x1a
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x1a
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x1a
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000000 00000000 00000000 (0)
|
|
%r13: 08000000 08000000 08000000 08000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000090
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=13, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 39
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000090
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1a69693 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x1a
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x1a
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x1a
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x1a
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000000 00000000 00000000 (0)
|
|
%r13: 0c000000 0c000000 0c000000 0c000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000090
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=13, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 40
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000008c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x22026f3 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r13=0
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r13=0
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r13=0
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r13=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000014 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 8000007c 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000000 00000000 00000000 (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000008c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 41
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000094
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2002673 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=0
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=1
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=2
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=3
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000001 00000002 00000003 (0)
|
|
%r13: 04000000 04000000 04000000 04000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000094
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 42
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000094
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2002673 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=0
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=1
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=2
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=3
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000001 00000002 00000003 (0)
|
|
%r13: 08000000 08000000 08000000 08000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000094
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 43
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000094
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2002673 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=0
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=1
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=2
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=3
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000001 00000002 00000003 (0)
|
|
%r13: 0c000000 0c000000 0c000000 0c000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000094
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 44
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000090
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1a69693 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x1a
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x1a
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x1a
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x1a
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000014 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 8000007c 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000000 00000000 00000000 (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000090
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=13, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 45
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000098
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xa61593 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r11 <- r12, imm=0xa
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r11 <- r12, imm=0xa
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r11 <- r12, imm=0xa
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r11 <- r12, imm=0xa
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000001 00000002 00000003 (0)
|
|
%r13: 04000000 04000000 04000000 04000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000098
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=12, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 46
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000098
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xa61593 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r11 <- r12, imm=0xa
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r11 <- r12, imm=0xa
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r11 <- r12, imm=0xa
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r11 <- r12, imm=0xa
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000001 00000002 00000003 (0)
|
|
%r13: 08000000 08000000 08000000 08000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000098
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=12, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 47
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000098
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xa61593 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r11 <- r12, imm=0xa
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r11 <- r12, imm=0xa
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r11 <- r12, imm=0xa
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r11 <- r12, imm=0xa
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000001 00000002 00000003 (0)
|
|
%r13: 0c000000 0c000000 0c000000 0c000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000098
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=12, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 48
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000094
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2002673 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=0
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=1
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=2
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r12 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r12=3
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000014 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 8000007c 00000000 00000000 00000000 (0)
|
|
%r12: 00000000 00000001 00000002 00000003 (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000094
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 49
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000009c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x261613 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r12 <- r12, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r12 <- r12, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r12 <- r12, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r12 <- r12, imm=0x2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 04000000 04000000 04000000 04000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000009c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=12, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 50
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000009c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x261613 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r12 <- r12, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r12 <- r12, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r12 <- r12, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r12 <- r12, imm=0x2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 08000000 08000000 08000000 08000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000009c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=12, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 51
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000009c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x261613 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r12 <- r12, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r12 <- r12, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r12 <- r12, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r12 <- r12, imm=0x2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 0c000000 0c000000 0c000000 0c000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000009c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=12, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 52
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000098
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xa61593 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r11 <- r12, imm=0xa
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r11 <- r12, imm=0xa
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r11 <- r12, imm=0xa
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r11 <- r12, imm=0xa
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000014 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000001 00000002 00000003 (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000098
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=12, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 53
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000a0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x6ffff137 into: lui
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r2 <- imm=0x6ffff
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r2 <- imm=0x6ffff
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r2 <- imm=0x6ffff
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r2 <- imm=0x6ffff
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 6ffff000 6ffff000 6ffff000 6ffff000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 04000000 04000000 04000000 04000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000a0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 54
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000a0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x6ffff137 into: lui
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r2 <- imm=0x6ffff
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r2 <- imm=0x6ffff
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r2 <- imm=0x6ffff
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r2 <- imm=0x6ffff
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 6ffff000 6ffff000 6ffff000 6ffff000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 08000000 08000000 08000000 08000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000a0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 55
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000a0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x6ffff137 into: lui
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r2 <- imm=0x6ffff
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r2 <- imm=0x6ffff
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r2 <- imm=0x6ffff
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r2 <- imm=0x6ffff
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 6ffff000 6ffff000 6ffff000 6ffff000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 0c000000 0c000000 0c000000 0c000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000a0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 56
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000009c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x261613 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r12 <- r12, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r12 <- r12, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r12 <- r12, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r12 <- r12, imm=0x2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000014 00000000 00000000 00000000 (0)
|
|
%r 2: 00000000 00000000 00000000 00000000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000009c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=12, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 57
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000a4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x40b10133 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r11
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r11
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r11
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r11
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 6ffff000 6fffec00 6fffe800 6fffe400 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 04000000 04000000 04000000 04000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000a4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 58
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000a4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x40b10133 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r11
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r11
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r11
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r11
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 6ffff000 6fffec00 6fffe800 6fffe400 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 08000000 08000000 08000000 08000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000a4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 59
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000a4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x40b10133 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r11
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r11
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r11
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r11
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 6ffff000 6fffec00 6fffe800 6fffe400 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 0c000000 0c000000 0c000000 0c000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000a4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 60
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000a0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x6ffff137 into: lui
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r2 <- imm=0x6ffff
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r2 <- imm=0x6ffff
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r2 <- imm=0x6ffff
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r2 <- imm=0x6ffff
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000014 00000000 00000000 00000000 (0)
|
|
%r 2: 6ffff000 6ffff000 6ffff000 6ffff000 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000a0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 61
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000a8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x40d10133 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r13
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r13
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r13
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r13
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 6bfff000 6bffec00 6bffe800 6bffe400 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 04000000 04000000 04000000 04000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000a8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=13
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 62
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000a8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x40d10133 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r13
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r13
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r13
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r13
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 67fff000 67ffec00 67ffe800 67ffe400 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 08000000 08000000 08000000 08000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000a8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=13
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 63
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000a8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x40d10133 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r13
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r13
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r13
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r13
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 63fff000 63ffec00 63ffe800 63ffe400 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 0c000000 0c000000 0c000000 0c000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000a8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=13
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 64
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000a4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x40b10133 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r11
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r11
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r11
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r11
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000014 00000000 00000000 00000000 (0)
|
|
%r 2: 6ffff000 6fffec00 6fffe800 6fffe400 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000a4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 65
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000ac
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xc10133 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r2 <- r2, r12
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r2 <- r2, r12
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r2 <- r2, r12
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r2 <- r2, r12
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 6bfff000 6bffec04 6bffe808 6bffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 04000000 04000000 04000000 04000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000ac
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=12
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 66
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000ac
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xc10133 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r2 <- r2, r12
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r2 <- r2, r12
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r2 <- r2, r12
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r2 <- r2, r12
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 67fff000 67ffec04 67ffe808 67ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 08000000 08000000 08000000 08000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000ac
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=12
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 67
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000ac
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xc10133 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r2 <- r2, r12
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r2 <- r2, r12
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r2 <- r2, r12
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r2 <- r2, r12
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 63fff000 63ffec04 63ffe808 63ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 0c000000 0c000000 0c000000 0c000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000ac
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=12
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 68
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000a8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x40d10133 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r13
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r13
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r13
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r2 <- r2, r13
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000014 00000000 00000000 00000000 (0)
|
|
%r 2: 6ffff000 6fffec00 6fffe800 6fffe400 (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000a8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=13
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 69
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000b0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x21026f3 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=1
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=1
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=1
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=1
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 6bfff000 6bffec04 6bffe808 6bffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000b0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 70
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000b0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x21026f3 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=2
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=2
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=2
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 67fff000 67ffec04 67ffe808 67ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000b0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 71
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000b0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x21026f3 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=3
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=3
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=3
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=3
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 63fff000 63ffec04 63ffe808 63ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000b0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 72
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000ac
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xc10133 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r2 <- r2, r12
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r2 <- r2, r12
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r2 <- r2, r12
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r2 <- r2, r12
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000014 00000000 00000000 00000000 (0)
|
|
%r 2: 6ffff000 6fffec04 6fffe808 6fffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000ac
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=12
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 73
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000b4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x68663 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=12
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 6bfff000 6bffec04 6bffe808 6bffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000b4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 74
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000b4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x68663 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=12
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 67fff000 67ffec04 67ffe808 67ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000b4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 75
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000b4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x68663 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=12
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 63fff000 63ffec04 63ffe808 63ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000b4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 76
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000b0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x21026f3 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=0
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=0
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=0
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r13 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r13=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000014 00000000 00000000 00000000 (0)
|
|
%r 2: 6ffff000 6fffec04 6fffe808 6fffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000b0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 77
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000b4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x68663 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 800000c0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000014 00000000 00000000 00000000 (0)
|
|
%r 2: 6ffff000 6fffec04 6fffe808 6fffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000b4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 78
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 79
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000b8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x513 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 6bfff000 6bffec04 6bffe808 6bffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000b8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 80
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 1
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000b8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 81
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000b8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x513 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 67fff000 67ffec04 67ffe808 67ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000b8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 82
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000b8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x513 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 00000000 00000000 00000000 (0)
|
|
%r 2: 63fff000 63ffec04 63ffe808 63ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000b8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 83
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000bc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x5006b into: gpgpu
|
|
DEBUG ../../../../simX/instruction.cpp:982: TMC: r10
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0:(0)
|
|
%r 1:(0)
|
|
%r 2:(0)
|
|
%r 3:(0)
|
|
%r 4:(0)
|
|
%r 5:(0)
|
|
%r 6:(0)
|
|
%r 7:(0)
|
|
%r 8:(0)
|
|
%r 9:(0)
|
|
%r10:(0)
|
|
%r11:(0)
|
|
%r12:(0)
|
|
%r13:(0)
|
|
%r14:(0)
|
|
%r15:(0)
|
|
%r16:(0)
|
|
%r17:(0)
|
|
%r18:(0)
|
|
%r19:(0)
|
|
%r20:(0)
|
|
%r21:(0)
|
|
%r22:(0)
|
|
%r23:(0)
|
|
%r24:(0)
|
|
%r25:(0)
|
|
%r26:(0)
|
|
%r27:(0)
|
|
%r28:(0)
|
|
%r29:(0)
|
|
%r30:(0)
|
|
%r31:(0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:416: ** warp #1 active threads changed from 4 to 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000bc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 84
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000bc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x5006b into: gpgpu
|
|
DEBUG ../../../../simX/instruction.cpp:982: TMC: r10
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0:(0)
|
|
%r 1:(0)
|
|
%r 2:(0)
|
|
%r 3:(0)
|
|
%r 4:(0)
|
|
%r 5:(0)
|
|
%r 6:(0)
|
|
%r 7:(0)
|
|
%r 8:(0)
|
|
%r 9:(0)
|
|
%r10:(0)
|
|
%r11:(0)
|
|
%r12:(0)
|
|
%r13:(0)
|
|
%r14:(0)
|
|
%r15:(0)
|
|
%r16:(0)
|
|
%r17:(0)
|
|
%r18:(0)
|
|
%r19:(0)
|
|
%r20:(0)
|
|
%r21:(0)
|
|
%r22:(0)
|
|
%r23:(0)
|
|
%r24:(0)
|
|
%r25:(0)
|
|
%r26:(0)
|
|
%r27:(0)
|
|
%r28:(0)
|
|
%r29:(0)
|
|
%r30:(0)
|
|
%r31:(0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:416: ** warp #2 active threads changed from 4 to 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000bc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 85
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000bc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x5006b into: gpgpu
|
|
DEBUG ../../../../simX/instruction.cpp:982: TMC: r10
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0:(0)
|
|
%r 1:(0)
|
|
%r 2:(0)
|
|
%r 3:(0)
|
|
%r 4:(0)
|
|
%r 5:(0)
|
|
%r 6:(0)
|
|
%r 7:(0)
|
|
%r 8:(0)
|
|
%r 9:(0)
|
|
%r10:(0)
|
|
%r11:(0)
|
|
%r12:(0)
|
|
%r13:(0)
|
|
%r14:(0)
|
|
%r15:(0)
|
|
%r16:(0)
|
|
%r17:(0)
|
|
%r18:(0)
|
|
%r19:(0)
|
|
%r20:(0)
|
|
%r21:(0)
|
|
%r22:(0)
|
|
%r23:(0)
|
|
%r24:(0)
|
|
%r25:(0)
|
|
%r26:(0)
|
|
%r27:(0)
|
|
%r28:(0)
|
|
%r29:(0)
|
|
%r30:(0)
|
|
%r31:(0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:416: ** warp #3 active threads changed from 4 to 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000bc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 86
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800000c0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000014
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000014 00000000 00000000 00000000 (0)
|
|
%r 2: 6ffff000 6fffec04 6fffe808 6fffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 87
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 88
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 89
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800000c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 90
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 91
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 92
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 93
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 94
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 95
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000014
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x100513 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=1
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=1
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=1
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=1
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000014 00000000 00000000 00000000 (0)
|
|
%r 2: 6ffff000 6fffec04 6fffe808 6fffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000001 00000001 00000001 00000001 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000000 00000000 00000000 00000000 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000014
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 96
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000018
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x5006b into: gpgpu
|
|
DEBUG ../../../../simX/instruction.cpp:982: TMC: r10
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000014 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 00000000 (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:416: ** warp #0 active threads changed from 4 to 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000018
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 97
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 98
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 99
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 100
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 101
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 102
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 103
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000001c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1d818513 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r3, imm=472
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000014 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 00000000 (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000001c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 104
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000020
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x23018613 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r12 <- r3, imm=560
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000014 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 00000000 (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 80016dd8 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000020
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 105
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000024
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x40a60633 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r12 <- r12, r10
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000014 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 00000000 (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000058 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000024
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=12, trs2=10
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 106
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000028
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x593 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r11 <- r0, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000014 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 00000000 (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000058 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000028
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 107
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000002c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x351000ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=2896
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000b7c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 00000000 (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000058 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000002c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 108
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000002c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 109
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 110
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 111
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 112
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 113
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 114
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b7c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf00313 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r6 <- r0, imm=15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000058 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b7c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=6, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 115
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b7c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=6, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 116
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b7c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=6, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 117
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b7c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=6, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 118
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b80
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x50713 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r14 <- r10, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000058 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 80016d80 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b80
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 119
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b80
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 120
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b80
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 121
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b80
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 122
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b84
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2c37e63 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:739: BGEU: r6, r12, imm=60
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000058 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 80016d80 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b84
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=6, trs2=12
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 123
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 124
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 125
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 126
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 127
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 128
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b88
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf77793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:621: ANDI: r15 <- r14, imm=0xf
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000058 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 80016d80 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b88
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 129
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b8c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xa079063 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r15, r0, imm=160
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000058 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 80016d80 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b8c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=15, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 130
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 131
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 132
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 133
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 134
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 135
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 136
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b90
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8059263 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r11, r0, imm=132
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000058 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 80016d80 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b90
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=11, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 137
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 138
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 139
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 140
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 141
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 142
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b94
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xff067693 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:621: ANDI: r13 <- r12, imm=0xfffffff0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000058 (0)
|
|
%r13: 00000050 (0)
|
|
%r14: 80016d80 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b94
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=12, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 143
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b98
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf67613 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:621: ANDI: r12 <- r12, imm=0xf
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 00000050 (0)
|
|
%r14: 80016d80 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b98
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=12, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 144
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b9c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xe686b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r14
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016d80 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b9c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=13, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 145
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000ba0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb72023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r11 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016d80
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016d80 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ba0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 146
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000ba4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb72223 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r11 <- r14, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016d84
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016d80 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ba4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 147
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000ba8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb72423 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r11 <- r14, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016d88
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016d80 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ba8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 148
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bac
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb72623 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r11 <- r14, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016d8c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016d80 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bac
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 149
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bb0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1070713 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r14 <- r14, imm=16
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016d90 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bb0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 150
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bb4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfed766e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:730: BLTU: r14, r13, imm=-20
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000ba0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016d90 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bb4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=13
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 151
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 152
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 153
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 154
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 155
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 156
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 157
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000ba0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb72023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r11 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016d90
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016d90 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ba0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 158
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000ba4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb72223 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r11 <- r14, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016d94
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016d90 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ba4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 159
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000ba8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb72423 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r11 <- r14, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016d98
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016d90 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ba8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 160
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bac
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb72623 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r11 <- r14, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016d9c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016d90 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bac
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 161
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bb0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1070713 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r14 <- r14, imm=16
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016da0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bb0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 162
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bb4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfed766e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:730: BLTU: r14, r13, imm=-20
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000ba0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016da0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bb4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=13
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 163
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 164
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 165
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 166
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 167
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 168
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 169
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000ba0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb72023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r11 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016da0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016da0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ba0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 170
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000ba4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb72223 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r11 <- r14, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016da4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016da0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ba4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 171
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000ba8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb72423 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r11 <- r14, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016da8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016da0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ba8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 172
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bac
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb72623 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r11 <- r14, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016dac
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016da0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bac
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 173
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bb0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1070713 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r14 <- r14, imm=16
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016db0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bb0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 174
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bb4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfed766e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:730: BLTU: r14, r13, imm=-20
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000ba0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016db0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bb4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=13
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 175
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 176
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 177
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 178
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 179
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 180
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 181
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000ba0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb72023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r11 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016db0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016db0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ba0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 182
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000ba4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb72223 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r11 <- r14, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016db4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016db0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ba4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 183
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000ba8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb72423 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r11 <- r14, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016db8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016db0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ba8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 184
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bac
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb72623 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r11 <- r14, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016dbc
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016db0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bac
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 185
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bb0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1070713 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r14 <- r14, imm=16
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016dc0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bb0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 186
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bb4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfed766e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:730: BLTU: r14, r13, imm=-20
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000ba0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016dc0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bb4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=13
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 187
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 188
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 189
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 190
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 191
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 192
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 193
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000ba0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb72023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r11 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016dc0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016dc0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ba0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 194
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000ba4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb72223 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r11 <- r14, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016dc4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016dc0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ba4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 195
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000ba8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb72423 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r11 <- r14, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016dc8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016dc0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ba8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 196
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bac
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb72623 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r11 <- r14, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016dcc
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016dc0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bac
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 197
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bb0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1070713 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r14 <- r14, imm=16
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bb0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 198
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bb4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfed766e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:730: BLTU: r14, r13, imm=-20
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bb4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=13
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 199
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 200
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 201
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 202
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 203
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 204
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 205
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bb8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x61463 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r12, r0, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000bc0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80016dd0 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bb8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 206
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 207
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 208
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 209
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 210
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 211
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bc0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x40c306b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r13 <- r6, r12
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 00000007 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bc0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=6, trs2=12
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 212
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bc0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=6, trs2=12
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 213
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bc0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=6, trs2=12
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 214
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bc0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=6, trs2=12
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 215
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bc4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x269693 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 0000001c (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bc4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=13, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 216
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bc8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x297 into: auipc
|
|
DEBUG ../../../../simX/instruction.cpp:753: AUIPC: r5 <- imm=0x0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 0000001c (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bc8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=5, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 217
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bcc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x5686b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r5
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80000be4 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bcc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=13, trs2=5
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 218
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bcc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=13, trs2=5
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 219
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bd0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xc68067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r13, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000bf0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80000be4 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bd0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=13, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 220
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 221
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 222
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 223
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 224
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 225
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 226
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 227
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bf0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb703a3 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:666: SB: r11 <- r14, imm=7
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016dd7
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80000be4 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bf0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 228
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bf4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb70323 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:666: SB: r11 <- r14, imm=6
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016dd6
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80000be4 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bf4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 229
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bf8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb702a3 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:666: SB: r11 <- r14, imm=5
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016dd5
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80000be4 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bf8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 230
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000bfc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb70223 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:666: SB: r11 <- r14, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016dd4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80000be4 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000bfc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 231
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000c00
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb701a3 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:666: SB: r11 <- r14, imm=3
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016dd3
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80000be4 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000c00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 232
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000c00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 233
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000c00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 234
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000c00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 235
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000c04
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb70123 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:666: SB: r11 <- r14, imm=2
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016dd2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80000be4 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000c04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 236
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000c08
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb700a3 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:666: SB: r11 <- r14, imm=1
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016dd1
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80000be4 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000c08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 237
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000c0c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb70023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:666: SB: r11 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016dd0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80000be4 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000c0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 238
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000c10
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000030
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80016d80 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80000be4 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000c10
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 239
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 240
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 241
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 242
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 243
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 244
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000030
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1517 into: auipc
|
|
DEBUG ../../../../simX/instruction.cpp:753: AUIPC: r10 <- imm=0x1
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80001030 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80000be4 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000030
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 245
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000034
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xa5450513 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r10, imm=4294965844
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000030 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80000a84 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80000be4 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000034
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 246
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000038
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x209000ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=2568
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000a40
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80000a84 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80000be4 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000038
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 247
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 248
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 249
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 250
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 251
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 252
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 253
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a40
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x50593 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r11 <- r10, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80000a84 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 80000be4 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a40
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 254
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a40
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 255
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a40
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 256
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a40
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 257
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a44
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x693 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r13 <- r0, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80000a84 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000008 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a44
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 258
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a48
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x613 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r12 <- r0, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 80000a84 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a48
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 259
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a4c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x513 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a4c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 260
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a50
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x7590206f into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r0 <- imm=12120
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 800039a8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 80016dd0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a50
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 261
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 262
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 263
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 264
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 265
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 266
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800039a8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1c01a703 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r3, imm=448
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016d68
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 800163b0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 800163b0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800039a8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 267
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800039a8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 268
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800039a8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 269
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800039a8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 270
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800039ac
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x14872783 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r15 <- r14, imm=328
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 800164f8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 800163b0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800039ac
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 271
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800039b0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x4078c63 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r15, r0, imm=88
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80003a08
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 800163b0 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800039b0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=15, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 272
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 273
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 274
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 275
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 276
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 277
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 278
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 279
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 280
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 281
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 282
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 283
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a08
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x14c70793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r14, imm=332
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 800163b0 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 284
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 285
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 286
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 287
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a0c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x14f72423 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r15 <- r14, imm=328
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 800164f8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 800163b0 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 288
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a10
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfa5ff06f into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r0 <- imm=-92
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 800039b4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 800163b0 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a10
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 289
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 290
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 291
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 292
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 293
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 294
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 295
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800039b4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x47a703 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016500
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800039b4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 296
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800039b8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1f00813 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r16 <- r0, imm=31
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 0000001f (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800039b8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=16, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 297
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800039bc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x6e84e63 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:712: BLT: r16, r14, imm=124
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 0000001f (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800039bc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=16, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 298
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 299
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 300
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 301
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 302
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 303
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 304
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 305
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800039c0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x271813 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r16 <- r14, imm=0x2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800039c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=16, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 306
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800039c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=16, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 307
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800039c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=16, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 308
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800039c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=16, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 309
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800039c4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2050663 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r10, r0, imm=44
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 800039f0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800039c4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=10, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 310
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 311
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 312
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 313
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 314
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 315
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800039f0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x170713 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r14 <- r14, imm=1
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800039f0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 316
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800039f4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xe7a223 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016500
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800039f4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=15, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 317
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800039f8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x10787b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r15 <- r15, r16
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800039f8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=16
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 318
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800039fc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb7a423 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r11 <- r15, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016504
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800039fc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=15, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 319
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800039fc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=15, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 320
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a00
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x513 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 321
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a04
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 8000003c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 8000003c (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 322
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 323
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 324
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 325
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 326
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 327
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 328
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000003c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2a5000ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=2724
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000ae0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000003c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 329
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 330
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 331
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 332
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 333
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 334
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000ae0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xff010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967280
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ae0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 335
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ae0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 336
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ae0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 337
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ae0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 338
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000ae4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x812423 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r8 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffeff8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ae4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=8
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 339
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000ae8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1212023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r18 <- r2, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffeff0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ae8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=18
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 340
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000aec
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x80016437 into: lui
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r8 <- imm=0xfff80016
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 80016000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000aec
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 341
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000aec
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 342
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000af0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x80016937 into: lui
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r18 <- imm=0xfff80016
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 80016000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 80016000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000af0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 343
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000af4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x3a040793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r8, imm=928
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 80016000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800163a0 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 80016000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000af4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=8, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 344
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000af8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x3a090913 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r18 <- r18, imm=928
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 80016000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800163a0 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800163a0 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000af8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=18, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 345
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000afc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x40f90933 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r18 <- r18, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 80016000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800163a0 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000afc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 346
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b00
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x112623 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffeffc
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 80016000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800163a0 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 347
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 348
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 349
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 350
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b04
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x912223 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r9 <- r2, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffeff4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 80016000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800163a0 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=9
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 351
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b08
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x40295913 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:640: SRAI: r18 <- r18, imm=2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 80016000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800163a0 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=18, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 352
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b0c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2090063 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r18, r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000b2c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 80016000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800163a0 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=18, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 353
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 354
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 355
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 356
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 357
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 358
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 359
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b2c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x80016437 into: lui
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r8 <- imm=0xfff80016
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 80016000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800163a0 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 360
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b30
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x80016937 into: lui
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r18 <- imm=0xfff80016
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 80016000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800163a0 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 80016000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 361
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b34
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x3a040793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r8, imm=928
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 80016000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800163a0 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 80016000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=8, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 362
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b38
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x3a490913 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r18 <- r18, imm=932
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 80016000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800163a0 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800163a4 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=18, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 363
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b3c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x40f90933 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r18 <- r18, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 80016000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800163a0 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000004 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b3c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 364
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b40
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x40295913 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:640: SRAI: r18 <- r18, imm=2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 80016000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800163a0 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000001 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b40
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=18, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 365
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b44
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2090063 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r18, r0, imm=32
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 80016000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800163a0 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000001 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b44
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=18, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 366
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b44
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=18, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 367
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 368
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 369
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 370
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 371
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 372
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 373
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 374
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b48
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x3a040413 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r8 <- r8, imm=928
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 800163a0 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800163a0 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000001 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b48
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=8, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 375
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b4c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x493 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r9 <- r0, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 800163a0 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800163a0 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000001 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b4c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 376
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b50
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x42783 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r15 <- r8, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 800163a0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80000064
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 800163a0 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 80000064 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000001 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b50
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=8, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 377
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b54
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x148493 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r9 <- r9, imm=1
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 800163a0 (0)
|
|
%r 9: 00000001 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 80000064 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000001 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b54
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=9, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 378
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b58
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x440413 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r8 <- r8, imm=4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 800163a4 (0)
|
|
%r 9: 00000001 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 80000064 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000001 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b58
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=8, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 379
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b5c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x780e7 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r1 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000064
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000b60 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 800163a4 (0)
|
|
%r 9: 00000001 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 80000064 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000001 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b5c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 380
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 381
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 382
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 383
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 384
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 385
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 386
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 387
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000064
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r0, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000b60 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 800163a4 (0)
|
|
%r 9: 00000001 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000001 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000064
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 388
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000068
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x78863 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r15, r0, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000078
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000b60 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 800163a4 (0)
|
|
%r 9: 00000001 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000001 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000068
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=15, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 389
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 390
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 391
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 392
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 393
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 394
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 395
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000078
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000b60
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000b60 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 800163a4 (0)
|
|
%r 9: 00000001 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000001 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000078
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 396
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 397
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 398
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 399
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 400
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 401
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b60
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfe9918e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r18, r9, imm=-16
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000b60 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 800163a4 (0)
|
|
%r 9: 00000001 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000001 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b60
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=18, trs2=9
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 402
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 403
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 404
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 405
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 406
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 407
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b64
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xc12083 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffeffc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80000040
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 800163a4 (0)
|
|
%r 9: 00000001 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000001 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b64
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 408
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b68
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x812403 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffeff8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000001 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000001 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b68
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 409
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b6c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x412483 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffeff4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000001 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b6c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 410
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b70
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x12903 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r2, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffeff0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b70
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 411
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b74
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=16
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b74
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 412
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000b78
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000040
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000040 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000b78
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 413
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 414
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 415
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 416
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 417
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 418
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000040
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8000ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000048
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000040
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 419
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 420
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 421
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 422
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 423
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 424
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000048
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x800006b7 into: lui
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r13 <- imm=0xfff80000
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 80000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000048
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 425
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000004c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x80001637 into: lui
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r12 <- imm=0xfff80001
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 80001000 (0)
|
|
%r13: 80000000 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000004c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 426
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000050
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf006c693 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:611: XORI: r13 <- r13, imm=0xffffff00
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 80001000 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000050
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=13, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 427
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000054
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x99860613 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r12 <- r12, imm=4294965656
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 80000a84 (0)
|
|
%r12: 80000998 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000054
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=12, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 428
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000058
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x400593 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r11 <- r0, imm=4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 00000004 (0)
|
|
%r12: 80000998 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000058
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 429
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000005c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x800513 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000008 (0)
|
|
%r11: 00000004 (0)
|
|
%r12: 80000998 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000005c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 430
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000060
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x150006f into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r0 <- imm=2068
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000874
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000008 (0)
|
|
%r11: 00000004 (0)
|
|
%r12: 80000998 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000060
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 431
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 432
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 433
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 434
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 435
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 436
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000874
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xff010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967280
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000008 (0)
|
|
%r11: 00000004 (0)
|
|
%r12: 80000998 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000874
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 437
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000874
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 438
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000874
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 439
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000874
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 440
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000878
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x812423 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r8 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffeff8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000008 (0)
|
|
%r11: 00000004 (0)
|
|
%r12: 80000998 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000878
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=8
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 441
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000087c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x912223 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r9 <- r2, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffeff4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000008 (0)
|
|
%r11: 00000004 (0)
|
|
%r12: 80000998 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000087c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=9
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 442
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000880
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1212023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r18 <- r2, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffeff0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000008 (0)
|
|
%r11: 00000004 (0)
|
|
%r12: 80000998 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000880
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=18
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 443
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000880
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=18
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 444
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000880
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=18
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 445
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000880
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=18
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 446
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000884
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x112623 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffeffc
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000008 (0)
|
|
%r11: 00000004 (0)
|
|
%r12: 80000998 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000884
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 447
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000888
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x20c1ac23 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r12 <- r3, imm=536
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016dc0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000008 (0)
|
|
%r11: 00000004 (0)
|
|
%r12: 80000998 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000888
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=3, trs2=12
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 448
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000088c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x20d1aa23 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r13 <- r3, imm=532
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016dbc
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000008 (0)
|
|
%r11: 00000004 (0)
|
|
%r12: 80000998 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000088c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=3, trs2=13
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 449
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000890
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x22b1a423 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r11 <- r3, imm=552
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016dd0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000008 (0)
|
|
%r11: 00000004 (0)
|
|
%r12: 80000998 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000890
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=3, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 450
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000894
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x100793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r0, imm=1
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000008 (0)
|
|
%r11: 00000004 (0)
|
|
%r12: 80000998 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000001 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000894
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 451
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000898
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xa7fa63 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:739: BGEU: r15, r10, imm=20
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000008 (0)
|
|
%r11: 00000004 (0)
|
|
%r12: 80000998 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000001 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000898
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=15, trs2=10
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 452
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 453
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 454
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 455
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 456
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 457
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 458
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000089c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x800005b7 into: lui
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r11 <- imm=0xfff80000
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000008 (0)
|
|
%r11: 80000000 (0)
|
|
%r12: 80000998 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000001 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000089c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 459
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800008a0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x7f058593 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r11 <- r11, imm=2032
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000008 (0)
|
|
%r11: 800007f0 (0)
|
|
%r12: 80000998 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000001 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008a0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=11, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 460
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800008a4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xe7dff0ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-388
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000720
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 800008a8 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000008 (0)
|
|
%r11: 800007f0 (0)
|
|
%r12: 80000998 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000001 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008a4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 461
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 462
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 463
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 464
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 465
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 466
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 467
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000720
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb5106b into: gpgpu
|
|
DEBUG ../../../../simX/instruction.cpp:885: WSPAWN: r10, r11
|
|
DEBUG ../../../../simX/instruction.cpp:890: Spawning 4 new warps at PC: 800007f0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 800008a8 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000008 (0)
|
|
%r11: 800007f0 (0)
|
|
%r12: 80000998 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000001 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000720
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=1
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 468
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000720
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=1
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 469
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000720
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=1
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 470
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000720
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=1
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 471
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800007f0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2281a503 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r10 <- r3, imm=552
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dd0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 00000000 (0)
|
|
%r 2: 6bfff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 00000000 (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000004 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000001 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800007f0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 472
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800007f0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 473
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800007f0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 474
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800007f0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 475
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800007f0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2281a503 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r10 <- r3, imm=552
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dd0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 00000000 (0)
|
|
%r 2: 67fff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 00000000 (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000004 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000002 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800007f0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 476
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800007f0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2281a503 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r10 <- r3, imm=552
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dd0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 00000000 (0)
|
|
%r 2: 63fff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 00000000 (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000004 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000003 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800007f0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 477
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000724
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 800008a8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 800008a8 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000008 (0)
|
|
%r11: 800007f0 (0)
|
|
%r12: 80000998 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000001 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000724
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 478
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800007f4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xff010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967280
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 00000000 (0)
|
|
%r 2: 6bffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 00000000 (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000004 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000001 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800007f4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 479
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800007f4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xff010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967280
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 00000000 (0)
|
|
%r 2: 67ffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 00000000 (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000004 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000002 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800007f4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 480
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800007f4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xff010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967280
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 00000000 (0)
|
|
%r 2: 63ffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 00000000 (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000004 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000003 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800007f4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 481
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800007f8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x112623 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffeffc
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 00000000 (0)
|
|
%r 2: 6bffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 00000000 (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000004 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000001 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800007f8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 482
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800007f8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x112623 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffeffc
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 00000000 (0)
|
|
%r 2: 67ffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 00000000 (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000004 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000002 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800007f8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 483
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800007f8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x112623 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffeffc
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 00000000 (0)
|
|
%r 2: 63ffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 00000000 (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000004 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000003 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800007f8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 484
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800008a8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2281a583 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r3, imm=552
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dd0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 800008a8 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000008 (0)
|
|
%r11: 00000004 (0)
|
|
%r12: 80000998 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000001 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008a8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 485
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800007fc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf2dff0ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-212
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000728
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000800 (0)
|
|
%r 2: 6bffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 00000000 (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000004 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000001 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800007fc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 486
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800007fc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf2dff0ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-212
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000728
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000800 (0)
|
|
%r 2: 67ffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 00000000 (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000004 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000002 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800007fc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 487
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800007fc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf2dff0ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-212
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000728
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000800 (0)
|
|
%r 2: 63ffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 00000000 (0)
|
|
%r 6: 00000000 (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000004 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 00000000 (0)
|
|
%r13: 00000003 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800007fc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 488
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800008ac
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x58513 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r11, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 800008a8 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000004 (0)
|
|
%r11: 00000004 (0)
|
|
%r12: 80000998 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000001 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008ac
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=11, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 489
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800008b0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xe79ff0ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-392
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000728
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 800008b4 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000004 (0)
|
|
%r11: 00000004 (0)
|
|
%r12: 80000998 (0)
|
|
%r13: 7fffff00 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000001 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008b0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 490
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 491
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000728
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x5006b into: gpgpu
|
|
DEBUG ../../../../simX/instruction.cpp:982: TMC: r10
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000800 00000000 00000000 00000000 (0)
|
|
%r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:416: ** warp #1 active threads changed from 1 to 4
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000728
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 492
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 0 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000728
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x5006b into: gpgpu
|
|
DEBUG ../../../../simX/instruction.cpp:982: TMC: r10
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000800 00000000 00000000 00000000 (0)
|
|
%r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:416: ** warp #2 active threads changed from 1 to 4
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000728
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 493
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000728
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x5006b into: gpgpu
|
|
DEBUG ../../../../simX/instruction.cpp:982: TMC: r10
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000800 00000000 00000000 00000000 (0)
|
|
%r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:416: ** warp #3 active threads changed from 1 to 4
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000728
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 494
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 495
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000728
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x5006b into: gpgpu
|
|
DEBUG ../../../../simX/instruction.cpp:982: TMC: r10
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008b4 00000000 00000000 00000000 (0)
|
|
%r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000001 00000001 00000001 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 00000001 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:416: ** warp #0 active threads changed from 1 to 4
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000728
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 496
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 497
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000072c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000800
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000800 00000000 00000000 00000000 (0)
|
|
%r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000072c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 498
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 0 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000072c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000800
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000800 00000000 00000000 00000000 (0)
|
|
%r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000072c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 499
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000072c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000800
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000800 00000000 00000000 00000000 (0)
|
|
%r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000000 00000000 00000000 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000072c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 500
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 501
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000072c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 800008b4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008b4 00000000 00000000 00000000 (0)
|
|
%r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000004 00000001 00000001 00000001 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 00000001 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000072c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 502
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 503
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000800
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2141a503 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r10 <- r3, imm=532
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dbc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r10 <- r3, imm=532
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dbc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r10 <- r3, imm=532
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dbc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r10 <- r3, imm=532
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dbc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 7fffff00
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000800 00000000 00000000 00000000 (0)
|
|
%r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000800
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 504
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000800
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 505
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000800
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 506
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000800
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 507
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000800
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2141a503 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r10 <- r3, imm=532
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dbc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r10 <- r3, imm=532
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dbc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r10 <- r3, imm=532
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dbc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r10 <- r3, imm=532
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dbc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 7fffff00
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000800 00000000 00000000 00000000 (0)
|
|
%r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000800
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 508
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000800
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2141a503 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r10 <- r3, imm=532
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dbc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r10 <- r3, imm=532
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dbc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r10 <- r3, imm=532
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dbc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r10 <- r3, imm=532
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dbc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 7fffff00
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000800 00000000 00000000 00000000 (0)
|
|
%r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000800
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 509
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800008b4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2141a503 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r10 <- r3, imm=532
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dbc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r10 <- r3, imm=532
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dbc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r10 <- r3, imm=532
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dbc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r10 <- r3, imm=532
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dbc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 7fffff00
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008b4 00000000 00000000 00000000 (0)
|
|
%r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 00000001 00000000 00000000 00000000 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008b4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 510
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008b4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 511
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008b4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 512
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000804
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2181a783 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r15 <- r3, imm=536
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dc0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80000998
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r15 <- r3, imm=536
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dc0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80000998
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r15 <- r3, imm=536
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dc0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80000998
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r15 <- r3, imm=536
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dc0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80000998
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000800 00000000 00000000 00000000 (0)
|
|
%r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000804
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 513
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000804
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 514
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000804
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 515
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000804
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2181a783 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r15 <- r3, imm=536
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dc0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80000998
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r15 <- r3, imm=536
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dc0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80000998
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r15 <- r3, imm=536
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dc0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80000998
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r15 <- r3, imm=536
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dc0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80000998
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000800 00000000 00000000 00000000 (0)
|
|
%r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000804
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 516
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000804
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 517
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000804
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 518
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000804
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2181a783 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r15 <- r3, imm=536
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dc0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80000998
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r15 <- r3, imm=536
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dc0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80000998
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r15 <- r3, imm=536
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dc0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80000998
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r15 <- r3, imm=536
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dc0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80000998
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000800 00000000 00000000 00000000 (0)
|
|
%r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000804
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 519
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000804
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 520
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000804
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 521
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800008b8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2181a783 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r15 <- r3, imm=536
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dc0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80000998
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r15 <- r3, imm=536
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dc0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80000998
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r15 <- r3, imm=536
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dc0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80000998
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r15 <- r3, imm=536
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016dc0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80000998
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008b4 00000000 00000000 00000000 (0)
|
|
%r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008b8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 522
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008b8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 523
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008b8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 524
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000808
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x780e7 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r1 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r1 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r1 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r1 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000998
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000808
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 525
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000808
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 526
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000808
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 527
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000808
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x780e7 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r1 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r1 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r1 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r1 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000998
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000808
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 528
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000808
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 529
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000808
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 530
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000808
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x780e7 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r1 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r1 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r1 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r1 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000998
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000808
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 531
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800008bc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x780e7 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r1 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r1 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r1 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r1 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000998
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c0 800008c0 800008c0 800008c0 (0)
|
|
%r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008bc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 532
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 533
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 534
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 535
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 1
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 536
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000998
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfe010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967264
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967264
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967264
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967264
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000998
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 537
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000998
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 538
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000998
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 539
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000998
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 540
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000998
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfe010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967264
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967264
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967264
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967264
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000998
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 541
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000998
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfe010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967264
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967264
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967264
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967264
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000998
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 542
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000998
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfe010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967264
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967264
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967264
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967264
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c0 800008c0 800008c0 800008c0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000998
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 543
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000099c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x112e23 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffefec
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffec00
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffe804
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffe408
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000099c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 544
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000099c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x112e23 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffefec
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffec00
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffe804
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffe408
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000099c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=9
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 545
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000099c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x112e23 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffefec
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffec00
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffe804
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffe408
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000099c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 546
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000099c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x112e23 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffefec
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffec00
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffe804
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffe408
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c0 800008c0 800008c0 800008c0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000099c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 547
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009a0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x812c23 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffefe8
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffebfc
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffe800
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffe404
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009a0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=8
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=9
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 548
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009a0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x812c23 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffefe8
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffebfc
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffe800
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffe404
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009a0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=8
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 549
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009a0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x812c23 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffefe8
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffebfc
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffe800
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffe404
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009a0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=8
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 550
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009a0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x812c23 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffefe8
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffebfc
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffe800
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffe404
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c0 800008c0 800008c0 800008c0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009a0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=8
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 551
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009a4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x912a23 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffefe4
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffebf8
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffe7fc
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffe400
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009a4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=9
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 552
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009a4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x912a23 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffefe4
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffebf8
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffe7fc
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffe400
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009a4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=9
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 553
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009a4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x912a23 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffefe4
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffebf8
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffe7fc
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffe400
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009a4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=9
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 554
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009a4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x912a23 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffefe4
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffebf8
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffe7fc
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffe400
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c0 800008c0 800008c0 800008c0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009a4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=9
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 555
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009a8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1212823 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffefe0
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffebf4
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffe7f8
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffe3fc
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009a8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=18
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 556
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009a8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1212823 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffefe0
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffebf4
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffe7f8
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffe3fc
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009a8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=18
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 557
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009a8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1212823 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffefe0
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffebf4
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffe7f8
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffe3fc
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009a8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=18
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 558
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009a8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1212823 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffefe0
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffebf4
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffe7f8
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffe3fc
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c0 800008c0 800008c0 800008c0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009a8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=18
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 559
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009ac
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1312623 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffefdc
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffebf0
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffe7f4
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffe3f8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009ac
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=19
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 560
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009ac
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1312623 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffefdc
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffebf0
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffe7f4
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffe3f8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009ac
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=19
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 561
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009ac
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1312623 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffefdc
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffebf0
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffe7f4
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffe3f8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009ac
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=19
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 562
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009ac
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1312623 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffefdc
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffebf0
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffe7f4
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffe3f8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c0 800008c0 800008c0 800008c0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009ac
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=19
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 563
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009b0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1412423 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffefd8
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffebec
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffe7f0
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6bffe3f4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009b0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=20
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 564
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009b0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1412423 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffefd8
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffebec
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffe7f0
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 67ffe3f4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009b0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=20
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 565
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009b0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1412423 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffefd8
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffebec
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffe7f0
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 63ffe3f4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009b0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=20
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 566
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009b0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1412423 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffefd8
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffebec
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffe7f0
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffe3f4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c0 800008c0 800008c0 800008c0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009b0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=20
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 567
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009b4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x50993 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r19 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r19 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r19 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r19 <- r10, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009b4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 568
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009b4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x50993 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r19 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r19 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r19 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r19 <- r10, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009b4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 569
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009b4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x50993 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r19 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r19 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r19 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r19 <- r10, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009b4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 570
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009b4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x50993 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r19 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r19 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r19 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r19 <- r10, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c0 800008c0 800008c0 800008c0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009b4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 571
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009b8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x52a03 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000000
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000000
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000000
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000000
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009b8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 572
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009b8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x52a03 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000000
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000000
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000000
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000000
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009b8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 573
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009b8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x52a03 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000000
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000000
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000000
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000000
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009b8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 574
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009b8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x52a03 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000000
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000000
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000000
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff00
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000000
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c0 800008c0 800008c0 800008c0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009b8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 575
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009b8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 576
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009b8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 577
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009b8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 578
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009b8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 579
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009b8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 580
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009bc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x452483 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r10, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff04
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000200
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r10, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff04
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000200
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r10, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff04
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000200
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r10, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff04
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000200
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009bc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 581
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009bc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 582
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009bc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 583
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009bc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x452483 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r10, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff04
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000200
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r10, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff04
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000200
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r10, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff04
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000200
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r10, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff04
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000200
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009bc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 584
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009bc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 585
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009bc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 586
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009bc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x452483 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r10, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff04
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000200
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r10, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff04
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000200
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r10, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff04
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000200
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r10, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff04
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000200
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009bc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 587
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009bc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 588
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009bc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 589
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009bc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x452483 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r10, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff04
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000200
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r10, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff04
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000200
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r10, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff04
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000200
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r10, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff04
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000200
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c0 800008c0 800008c0 800008c0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009bc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 590
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009bc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 591
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009bc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 592
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009c0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x852903 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r10, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff08
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000400
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r10, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff08
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000400
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r10, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff08
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000400
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r10, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff08
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000400
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 593
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 594
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 595
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 596
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 597
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 598
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009c0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x852903 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r10, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff08
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000400
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r10, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff08
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000400
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r10, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff08
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000400
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r10, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff08
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000400
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 599
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009c0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x852903 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r10, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff08
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000400
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r10, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff08
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000400
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r10, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff08
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000400
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r10, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff08
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000400
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 600
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 601
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009c0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x852903 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r10, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff08
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000400
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r10, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff08
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000400
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r10, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff08
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000400
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r10, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff08
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10000400
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c0 800008c0 800008c0 800008c0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 602
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 603
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 604
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009c4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xd8dff0ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000750
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009c8 800009c8 800009c8 800009c8 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 605
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 606
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 607
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009c4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xd8dff0ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000750
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009c8 800009c8 800009c8 800009c8 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 608
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 609
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 610
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009c4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xd8dff0ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000750
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009c8 800009c8 800009c8 800009c8 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 611
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009c4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xd8dff0ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000750
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009c8 800009c8 800009c8 800009c8 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 612
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 613
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 614
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000750
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2202573 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r10=1
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r10=1
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r10=1
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r10=1
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009c8 800009c8 800009c8 800009c8 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000001 00000001 00000001 00000001 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000750
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 615
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 1
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000750
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 616
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000750
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 617
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000750
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 618
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000750
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2202573 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r10=2
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r10=2
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r10=2
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r10=2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009c8 800009c8 800009c8 800009c8 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000002 00000002 00000002 00000002 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000750
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 619
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000750
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2202573 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r10=3
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r10=3
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r10=3
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r10=3
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009c8 800009c8 800009c8 800009c8 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000003 00000003 00000003 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000750
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 620
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000750
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2202573 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r10=0
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r10=0
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r10=0
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=34
|
|
DEBUG ../../../../simX/instruction.cpp:796: vx_warpNum: r10=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009c8 800009c8 800009c8 800009c8 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000000 00000000 00000000 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000750
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 621
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000754
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 800009c8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009c8 800009c8 800009c8 800009c8 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000001 00000001 00000001 00000001 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000754
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 622
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000754
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 800009c8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009c8 800009c8 800009c8 800009c8 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000002 00000002 00000002 00000002 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000754
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 623
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000754
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 800009c8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009c8 800009c8 800009c8 800009c8 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000003 00000003 00000003 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000754
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 624
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000754
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 800009c8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009c8 800009c8 800009c8 800009c8 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000000 00000000 00000000 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000754
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 625
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 626
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 627
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009c8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x50413 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r8 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r8 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r8 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r8 <- r10, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009c8 800009c8 800009c8 800009c8 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000001 00000001 00000001 00000001 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000001 00000001 00000001 00000001 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 628
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009c8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x50413 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r8 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r8 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r8 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r8 <- r10, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009c8 800009c8 800009c8 800009c8 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000002 00000002 00000002 00000002 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000002 00000002 00000002 00000002 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 629
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009c8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x50413 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r8 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r8 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r8 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r8 <- r10, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009c8 800009c8 800009c8 800009c8 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000003 00000003 00000003 00000003 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000003 00000003 00000003 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 630
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009c8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x50413 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r8 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r8 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r8 <- r10, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r8 <- r10, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009c8 800009c8 800009c8 800009c8 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000000 00000000 00000000 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009c8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 631
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009cc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xd8dff0ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000758
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000001 00000001 00000001 00000001 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000001 00000001 00000001 00000001 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009cc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 632
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009cc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xd8dff0ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000758
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000002 00000002 00000002 00000002 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000002 00000002 00000002 00000002 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009cc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 633
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009cc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xd8dff0ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000758
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000003 00000003 00000003 00000003 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000003 00000003 00000003 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009cc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 634
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009cc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xd8dff0ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-628
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000758
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000000 00000000 00000000 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009cc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 635
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 636
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 637
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000758
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2002573 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=0
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=1
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=2
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=3
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000001 00000001 00000001 00000001 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000758
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 638
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000758
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2002573 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=0
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=1
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=2
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=3
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000002 00000002 00000002 00000002 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000758
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 639
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000758
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2002573 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=0
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=1
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=2
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=3
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000003 00000003 00000003 00000003 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000758
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 640
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000758
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2002573 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=0
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=1
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=2
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:788: vx_threadID: r10=3
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000758
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 641
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000075c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 800009d0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000001 00000001 00000001 00000001 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000001 00000001 00000001 00000001 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000075c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 642
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000075c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 800009d0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000002 00000002 00000002 00000002 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000002 00000002 00000002 00000002 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000075c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 643
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000075c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 800009d0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000003 00000003 00000003 00000003 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000003 00000003 00000003 00000003 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000075c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 644
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000075c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 800009d0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 7fffff00 00000000 00000000 00000000 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000075c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 645
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 646
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 647
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009d0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xc9a683 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r13 <- r19, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff0c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 4
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r13 <- r19, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff0c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 4
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r13 <- r19, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff0c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 4
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r13 <- r19, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff0c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000001 00000001 00000001 00000001 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000004 00000004 00000004 00000004 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009d0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=19, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 648
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009d0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xc9a683 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r13 <- r19, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff0c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 4
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r13 <- r19, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff0c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 4
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r13 <- r19, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff0c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 4
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r13 <- r19, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff0c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000002 00000002 00000002 00000002 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000004 00000004 00000004 00000004 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009d0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=19, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 649
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009d0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xc9a683 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r13 <- r19, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff0c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 4
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r13 <- r19, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff0c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 4
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r13 <- r19, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff0c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 4
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r13 <- r19, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff0c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000003 00000003 00000003 00000003 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000004 00000004 00000004 00000004 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009d0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=19, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 650
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009d0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xc9a683 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r13 <- r19, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff0c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 4
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r13 <- r19, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff0c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 4
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r13 <- r19, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff0c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 4
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r13 <- r19, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 7fffff0c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 00000004 00000004 00000004 00000004 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009d0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=19, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 651
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009d0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=19, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 652
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009d0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=19, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 653
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009d4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x241413 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r8 <- r8, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r8 <- r8, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r8 <- r8, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r8 <- r8, imm=0x2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000004 00000004 00000004 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000004 00000004 00000004 00000004 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009d4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=8, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 654
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009d4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=8, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 655
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009d4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=8, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 656
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009d4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x241413 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r8 <- r8, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r8 <- r8, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r8 <- r8, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r8 <- r8, imm=0x2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000008 00000008 00000008 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000004 00000004 00000004 00000004 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009d4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=8, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 657
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009d4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=8, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 658
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009d4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=8, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 659
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009d4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x241413 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r8 <- r8, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r8 <- r8, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r8 <- r8, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r8 <- r8, imm=0x2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000c 0000000c 0000000c (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000004 00000004 00000004 00000004 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009d4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=8, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 660
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009d4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x241413 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r8 <- r8, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r8 <- r8, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r8 <- r8, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r8 <- r8, imm=0x2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 00000004 00000004 00000004 00000004 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009d4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=8, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 661
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009d8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xa40433 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r8 <- r8, r10
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r8 <- r8, r10
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r8 <- r8, r10
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r8 <- r8, r10
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000004 00000004 00000004 00000004 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009d8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=8, trs2=10
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 662
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009d8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xa40433 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r8 <- r8, r10
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r8 <- r8, r10
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r8 <- r8, r10
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r8 <- r8, r10
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000004 00000004 00000004 00000004 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009d8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=8, trs2=10
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 663
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009d8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xa40433 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r8 <- r8, r10
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r8 <- r8, r10
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r8 <- r8, r10
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r8 <- r8, r10
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000004 00000004 00000004 00000004 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009d8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=8, trs2=10
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 664
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009d8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xa40433 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r8 <- r8, r10
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r8 <- r8, r10
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r8 <- r8, r10
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r8 <- r8, r10
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 00000004 00000004 00000004 00000004 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 80000998 80000998 80000998 80000998 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009d8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=8, trs2=10
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 665
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009dc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2d407b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r15 <- r8, r13
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r15 <- r8, r13
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r15 <- r8, r13
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r15 <- r8, r13
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000004 00000004 00000004 00000004 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000010 00000014 00000018 0000001c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009dc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=8, trs2=13
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 666
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009dc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2d407b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r15 <- r8, r13
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r15 <- r8, r13
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r15 <- r8, r13
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r15 <- r8, r13
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000004 00000004 00000004 00000004 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000020 00000024 00000028 0000002c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009dc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=8, trs2=13
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 667
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009dc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2d407b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r15 <- r8, r13
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r15 <- r8, r13
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r15 <- r8, r13
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r15 <- r8, r13
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000004 00000004 00000004 00000004 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000030 00000034 00000038 0000003c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009dc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=8, trs2=13
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 668
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009dc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2d407b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r15 <- r8, r13
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r15 <- r8, r13
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r15 <- r8, r13
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r15 <- r8, r13
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 00000004 00000004 00000004 00000004 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000004 00000008 0000000c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009dc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=8, trs2=13
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 669
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009e0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x4068063 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=64
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=64
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=64
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=64
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000004 00000004 00000004 00000004 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000010 00000014 00000018 0000001c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009e0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 670
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009e0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x4068063 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=64
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=64
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=64
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=64
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000004 00000004 00000004 00000004 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000020 00000024 00000028 0000002c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009e0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 671
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009e0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 672
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009e0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 673
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009e0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x4068063 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=64
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=64
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=64
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=64
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000004 00000004 00000004 00000004 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000030 00000034 00000038 0000003c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009e0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 674
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009e0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x4068063 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=64
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=64
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=64
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=64
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 00000004 00000004 00000004 00000004 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000004 00000008 0000000c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009e0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 675
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 676
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 677
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009e4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf686b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000014 00000018 0000001c 00000020 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000010 00000014 00000018 0000001c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009e4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=13, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 678
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009e4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf686b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000024 00000028 0000002c 00000030 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000020 00000024 00000028 0000002c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009e4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=13, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 679
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009e4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf686b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000034 00000038 0000003c 00000040 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000030 00000034 00000038 0000003c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009e4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=13, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 680
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009e4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf686b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 00000004 00000008 0000000c 00000010 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000004 00000008 0000000c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009e4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=13, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 681
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009e8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x269693 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000050 00000060 00000070 00000080 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000010 00000014 00000018 0000001c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009e8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=13, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 682
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009e8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x269693 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000090 000000a0 000000b0 000000c0 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000020 00000024 00000028 0000002c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009e8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=13, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 683
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009e8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x269693 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 000000d0 000000e0 000000f0 00000100 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000030 00000034 00000038 0000003c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009e8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=13, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 684
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009e8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x269693 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r13 <- r13, imm=0x2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 00000010 00000020 00000030 00000040 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000004 00000008 0000000c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009e8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=13, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 685
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009ec
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x279793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r15 <- r15, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r15 <- r15, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r15 <- r15, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r15 <- r15, imm=0x2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000050 00000060 00000070 00000080 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000040 00000050 00000060 00000070 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009ec
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 686
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009ec
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x279793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r15 <- r15, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r15 <- r15, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r15 <- r15, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r15 <- r15, imm=0x2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000090 000000a0 000000b0 000000c0 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 00000080 00000090 000000a0 000000b0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009ec
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 687
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009ec
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x279793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r15 <- r15, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r15 <- r15, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r15 <- r15, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r15 <- r15, imm=0x2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 000000d0 000000e0 000000f0 00000100 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 000000c0 000000d0 000000e0 000000f0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009ec
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 688
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009ec
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x279793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r15 <- r15, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r15 <- r15, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r15 <- r15, imm=0x2
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r15 <- r15, imm=0x2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 00000010 00000020 00000030 00000040 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 00000000 00000010 00000020 00000030 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009ec
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 689
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009f0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x14787b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r15 <- r15, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r15 <- r15, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r15 <- r15, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r15 <- r15, r20
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000050 00000060 00000070 00000080 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 10000040 10000050 10000060 10000070 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009f0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=20
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 690
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009f0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x14787b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r15 <- r15, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r15 <- r15, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r15 <- r15, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r15 <- r15, r20
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 00000090 000000a0 000000b0 000000c0 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 10000080 10000090 100000a0 100000b0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009f0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=20
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 691
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009f0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x14787b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r15 <- r15, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r15 <- r15, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r15 <- r15, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r15 <- r15, r20
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 000000d0 000000e0 000000f0 00000100 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 100000c0 100000d0 100000e0 100000f0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009f0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=20
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 692
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009f0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x14787b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r15 <- r15, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r15 <- r15, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r15 <- r15, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r15 <- r15, r20
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 00000010 00000020 00000030 00000040 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 10000000 10000010 10000020 10000030 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009f0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=20
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 693
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009f4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x14686b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r20
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 10000040 10000050 10000060 10000070 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009f4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=13, trs2=20
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 694
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009f4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x14686b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r20
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 10000080 10000090 100000a0 100000b0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009f4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=13, trs2=20
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 695
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009f4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x14686b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r20
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 100000c0 100000d0 100000e0 100000f0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009f4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=13, trs2=20
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 696
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009f4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x14686b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r20
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r13 <- r13, r20
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 10000000 10000010 10000020 10000030 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 10000400 10000400 10000400 10000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009f4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=13, trs2=20
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 697
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009f8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x41490933 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r18 <- r18, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r18 <- r18, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r18 <- r18, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r18 <- r18, r20
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 10000040 10000050 10000060 10000070 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009f8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=18, trs2=20
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 698
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009f8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x41490933 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r18 <- r18, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r18 <- r18, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r18 <- r18, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r18 <- r18, r20
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 10000080 10000090 100000a0 100000b0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009f8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=18, trs2=20
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 699
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009f8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x41490933 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r18 <- r18, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r18 <- r18, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r18 <- r18, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r18 <- r18, r20
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 100000c0 100000d0 100000e0 100000f0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009f8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=18, trs2=20
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 700
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009f8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x41490933 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r18 <- r18, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r18 <- r18, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r18 <- r18, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r18 <- r18, r20
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 10000200 10000200 10000200 10000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 10000000 10000010 10000020 10000030 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009f8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=18, trs2=20
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 701
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009fc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x414484b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r9 <- r9, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r9 <- r9, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r9 <- r9, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r9 <- r9, r20
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 10000040 10000050 10000060 10000070 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009fc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=9, trs2=20
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 702
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009fc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x414484b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r9 <- r9, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r9 <- r9, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r9 <- r9, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r9 <- r9, r20
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 10000080 10000090 100000a0 100000b0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009fc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=9, trs2=20
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 703
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009fc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x414484b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r9 <- r9, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r9 <- r9, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r9 <- r9, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r9 <- r9, r20
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000000 00000000 00000000 00000000 (0)
|
|
%r15: 100000c0 100000d0 100000e0 100000f0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009fc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=9, trs2=20
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 704
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800009fc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x414484b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r9 <- r9, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r9 <- r9, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r9 <- r9, r20
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r9 <- r9, r20
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000001 00000000 00000000 00000000 (0)
|
|
%r15: 10000000 10000010 10000020 10000030 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800009fc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=9, trs2=20
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 705
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a00
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf48733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 10000240 10000250 10000260 10000270 (0)
|
|
%r15: 10000040 10000050 10000060 10000070 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=9, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 706
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=9, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 707
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=9, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 708
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=9, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 709
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a00
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf48733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 10000280 10000290 100002a0 100002b0 (0)
|
|
%r15: 10000080 10000090 100000a0 100000b0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=9, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 710
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a00
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf48733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000400 00000800 00000c00 (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 100002c0 100002d0 100002e0 100002f0 (0)
|
|
%r15: 100000c0 100000d0 100000e0 100000f0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=9, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 711
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a00
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf48733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000004 00000400 00000800 00000c00 (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 10000200 10000210 10000220 10000230 (0)
|
|
%r15: 10000000 10000010 10000020 10000030 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=9, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 712
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a04
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x7a583 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000040
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000050
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 14
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000060
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 18
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000070
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 1c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000010 00000014 00000018 0000001c (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 10000240 10000250 10000260 10000270 (0)
|
|
%r15: 10000040 10000050 10000060 10000070 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 713
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a04
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x7a583 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000080
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 20
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000090
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 24
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000a0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 28
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000b0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 2c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000020 00000024 00000028 0000002c (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 10000280 10000290 100002a0 100002b0 (0)
|
|
%r15: 10000080 10000090 100000a0 100000b0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 714
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a04
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x7a583 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000c0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 30
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000d0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 34
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000e0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 38
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000f0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 3c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000030 00000034 00000038 0000003c (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 100002c0 100002d0 100002e0 100002f0 (0)
|
|
%r15: 100000c0 100000d0 100000e0 100000f0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 715
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a04
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x7a583 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000000
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000010
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 4
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000020
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 8
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000030
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000004 00000008 0000000c (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 10000200 10000210 10000220 10000230 (0)
|
|
%r15: 10000000 10000010 10000020 10000030 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 716
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 717
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 718
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 719
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 720
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 721
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a08
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x72703 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000240
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 10
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000250
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 14
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000260
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 18
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000270
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 1c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000010 00000014 00000018 0000001c (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000010 00000014 00000018 0000001c (0)
|
|
%r15: 10000040 10000050 10000060 10000070 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 722
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 723
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 724
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 725
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 726
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 727
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a08
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x72703 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000280
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 20
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000290
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 24
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002a0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 28
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002b0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 2c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000020 00000024 00000028 0000002c (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000020 00000024 00000028 0000002c (0)
|
|
%r15: 10000080 10000090 100000a0 100000b0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 728
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 729
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 730
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 731
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 732
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 733
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a08
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x72703 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002c0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 30
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002d0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 34
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002e0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 38
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002f0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 3c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000030 00000034 00000038 0000003c (0)
|
|
%r12: 00000000 00000004 00000008 0000000c (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000030 00000034 00000038 0000003c (0)
|
|
%r15: 100000c0 100000d0 100000e0 100000f0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 734
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 735
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 736
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 737
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 738
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 739
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a08
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x72703 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000200
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000210
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 4
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000220
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 8
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000230
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000004 00000008 0000000c (0)
|
|
%r12: 80000998 00000004 00000008 0000000c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000000 00000004 00000008 0000000c (0)
|
|
%r15: 10000000 10000010 10000020 10000030 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 740
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 741
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 742
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 743
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 744
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 745
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a0c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf90633 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000010 00000014 00000018 0000001c (0)
|
|
%r12: 10000440 10000450 10000460 10000470 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000010 00000014 00000018 0000001c (0)
|
|
%r15: 10000040 10000050 10000060 10000070 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 746
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 747
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 748
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 749
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 750
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 751
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a0c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf90633 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000020 00000024 00000028 0000002c (0)
|
|
%r12: 10000480 10000490 100004a0 100004b0 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000020 00000024 00000028 0000002c (0)
|
|
%r15: 10000080 10000090 100000a0 100000b0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 752
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 753
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 754
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 755
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 756
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 757
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a0c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf90633 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000030 00000034 00000038 0000003c (0)
|
|
%r12: 100004c0 100004d0 100004e0 100004f0 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000030 00000034 00000038 0000003c (0)
|
|
%r15: 100000c0 100000d0 100000e0 100000f0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 758
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a0c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf90633 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000004 00000008 0000000c (0)
|
|
%r12: 10000400 10000410 10000420 10000430 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000000 00000004 00000008 0000000c (0)
|
|
%r15: 10000000 10000010 10000020 10000030 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 759
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a10
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x478793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000010 00000014 00000018 0000001c (0)
|
|
%r12: 10000440 10000450 10000460 10000470 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000010 00000014 00000018 0000001c (0)
|
|
%r15: 10000044 10000054 10000064 10000074 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a10
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 760
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a10
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x478793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000020 00000024 00000028 0000002c (0)
|
|
%r12: 10000480 10000490 100004a0 100004b0 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000020 00000024 00000028 0000002c (0)
|
|
%r15: 10000084 10000094 100000a4 100000b4 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a10
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 761
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a10
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x478793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000030 00000034 00000038 0000003c (0)
|
|
%r12: 100004c0 100004d0 100004e0 100004f0 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000030 00000034 00000038 0000003c (0)
|
|
%r15: 100000c4 100000d4 100000e4 100000f4 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a10
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 762
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a10
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x478793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000004 00000008 0000000c (0)
|
|
%r12: 10000400 10000410 10000420 10000430 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000000 00000004 00000008 0000000c (0)
|
|
%r15: 10000004 10000014 10000024 10000034 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a10
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 763
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a14
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2b70733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000010 00000014 00000018 0000001c (0)
|
|
%r12: 10000440 10000450 10000460 10000470 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000100 00000190 00000240 00000310 (0)
|
|
%r15: 10000044 10000054 10000064 10000074 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a14
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 764
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a14
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2b70733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000020 00000024 00000028 0000002c (0)
|
|
%r12: 10000480 10000490 100004a0 100004b0 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000400 00000510 00000640 00000790 (0)
|
|
%r15: 10000084 10000094 100000a4 100000b4 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a14
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 765
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a14
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2b70733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000030 00000034 00000038 0000003c (0)
|
|
%r12: 100004c0 100004d0 100004e0 100004f0 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000900 00000a90 00000c40 00000e10 (0)
|
|
%r15: 100000c4 100000d4 100000e4 100000f4 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a14
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 766
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a14
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2b70733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000004 00000008 0000000c (0)
|
|
%r12: 10000400 10000410 10000420 10000430 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000000 00000010 00000040 00000090 (0)
|
|
%r15: 10000004 10000014 10000024 10000034 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a14
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 767
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a18
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xe62023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000440
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000450
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000460
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000470
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000010 00000014 00000018 0000001c (0)
|
|
%r12: 10000440 10000450 10000460 10000470 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000100 00000190 00000240 00000310 (0)
|
|
%r15: 10000044 10000054 10000064 10000074 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 768
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a18
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xe62023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000480
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000490
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004a0
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004b0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000020 00000024 00000028 0000002c (0)
|
|
%r12: 10000480 10000490 100004a0 100004b0 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000400 00000510 00000640 00000790 (0)
|
|
%r15: 10000084 10000094 100000a4 100000b4 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 769
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 770
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 771
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a18
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xe62023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004c0
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004d0
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004e0
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004f0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000030 00000034 00000038 0000003c (0)
|
|
%r12: 100004c0 100004d0 100004e0 100004f0 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000900 00000a90 00000c40 00000e10 (0)
|
|
%r15: 100000c4 100000d4 100000e4 100000f4 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 772
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a18
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xe62023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000400
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000410
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000420
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000430
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000004 00000008 0000000c (0)
|
|
%r12: 10000400 10000410 10000420 10000430 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000000 00000010 00000040 00000090 (0)
|
|
%r15: 10000004 10000014 10000024 10000034 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 773
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a1c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfef692e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000a00
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000010 00000014 00000018 0000001c (0)
|
|
%r12: 10000440 10000450 10000460 10000470 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000100 00000190 00000240 00000310 (0)
|
|
%r15: 10000044 10000054 10000064 10000074 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a1c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 774
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a1c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfef692e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000a00
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000020 00000024 00000028 0000002c (0)
|
|
%r12: 10000480 10000490 100004a0 100004b0 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000400 00000510 00000640 00000790 (0)
|
|
%r15: 10000084 10000094 100000a4 100000b4 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a1c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 775
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a1c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfef692e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000a00
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000030 00000034 00000038 0000003c (0)
|
|
%r12: 100004c0 100004d0 100004e0 100004f0 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000900 00000a90 00000c40 00000e10 (0)
|
|
%r15: 100000c4 100000d4 100000e4 100000f4 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a1c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 776
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a1c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfef692e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000a00
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000004 00000008 0000000c (0)
|
|
%r12: 10000400 10000410 10000420 10000430 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000000 00000010 00000040 00000090 (0)
|
|
%r15: 10000004 10000014 10000024 10000034 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a1c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 777
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 778
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 779
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a00
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf48733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000010 00000014 00000018 0000001c (0)
|
|
%r12: 10000440 10000450 10000460 10000470 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 10000244 10000254 10000264 10000274 (0)
|
|
%r15: 10000044 10000054 10000064 10000074 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=9, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 780
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a00
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf48733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000020 00000024 00000028 0000002c (0)
|
|
%r12: 10000480 10000490 100004a0 100004b0 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 10000284 10000294 100002a4 100002b4 (0)
|
|
%r15: 10000084 10000094 100000a4 100000b4 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=9, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 781
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a00
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf48733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000030 00000034 00000038 0000003c (0)
|
|
%r12: 100004c0 100004d0 100004e0 100004f0 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 100002c4 100002d4 100002e4 100002f4 (0)
|
|
%r15: 100000c4 100000d4 100000e4 100000f4 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=9, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 782
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a00
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf48733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000000 00000004 00000008 0000000c (0)
|
|
%r12: 10000400 10000410 10000420 10000430 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 10000204 10000214 10000224 10000234 (0)
|
|
%r15: 10000004 10000014 10000024 10000034 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=9, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 783
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a04
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x7a583 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000044
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 11
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000054
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 15
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000064
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 19
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000074
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 1d
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000011 00000015 00000019 0000001d (0)
|
|
%r12: 10000440 10000450 10000460 10000470 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 10000244 10000254 10000264 10000274 (0)
|
|
%r15: 10000044 10000054 10000064 10000074 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 784
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a04
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x7a583 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000084
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 21
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000094
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 25
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000a4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 29
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000b4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 2d
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000021 00000025 00000029 0000002d (0)
|
|
%r12: 10000480 10000490 100004a0 100004b0 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 10000284 10000294 100002a4 100002b4 (0)
|
|
%r15: 10000084 10000094 100000a4 100000b4 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 785
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a04
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x7a583 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000c4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 31
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000d4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 35
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000e4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 39
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000f4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 3d
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000031 00000035 00000039 0000003d (0)
|
|
%r12: 100004c0 100004d0 100004e0 100004f0 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 100002c4 100002d4 100002e4 100002f4 (0)
|
|
%r15: 100000c4 100000d4 100000e4 100000f4 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 786
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a04
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x7a583 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000004
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 1
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000014
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 5
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000024
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 9
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000034
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: d
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000001 00000005 00000009 0000000d (0)
|
|
%r12: 10000400 10000410 10000420 10000430 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 10000204 10000214 10000224 10000234 (0)
|
|
%r15: 10000004 10000014 10000024 10000034 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 787
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 788
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 789
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a08
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x72703 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000244
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 11
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000254
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 15
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000264
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 19
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000274
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 1d
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000011 00000015 00000019 0000001d (0)
|
|
%r12: 10000440 10000450 10000460 10000470 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000011 00000015 00000019 0000001d (0)
|
|
%r15: 10000044 10000054 10000064 10000074 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 790
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 791
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 792
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a08
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x72703 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000284
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 21
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000294
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 25
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002a4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 29
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002b4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 2d
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000021 00000025 00000029 0000002d (0)
|
|
%r12: 10000480 10000490 100004a0 100004b0 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000021 00000025 00000029 0000002d (0)
|
|
%r15: 10000084 10000094 100000a4 100000b4 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 793
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 794
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 795
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a08
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x72703 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002c4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 31
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002d4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 35
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002e4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 39
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002f4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 3d
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000031 00000035 00000039 0000003d (0)
|
|
%r12: 100004c0 100004d0 100004e0 100004f0 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000031 00000035 00000039 0000003d (0)
|
|
%r15: 100000c4 100000d4 100000e4 100000f4 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 796
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 797
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 798
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a08
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x72703 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000204
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 1
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000214
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 5
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000224
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 9
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000234
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: d
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000001 00000005 00000009 0000000d (0)
|
|
%r12: 10000400 10000410 10000420 10000430 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000001 00000005 00000009 0000000d (0)
|
|
%r15: 10000004 10000014 10000024 10000034 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 799
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 800
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 801
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a0c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf90633 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000011 00000015 00000019 0000001d (0)
|
|
%r12: 10000444 10000454 10000464 10000474 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000011 00000015 00000019 0000001d (0)
|
|
%r15: 10000044 10000054 10000064 10000074 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 802
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 803
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 804
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a0c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf90633 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000021 00000025 00000029 0000002d (0)
|
|
%r12: 10000484 10000494 100004a4 100004b4 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000021 00000025 00000029 0000002d (0)
|
|
%r15: 10000084 10000094 100000a4 100000b4 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 805
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 806
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 807
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a0c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf90633 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000031 00000035 00000039 0000003d (0)
|
|
%r12: 100004c4 100004d4 100004e4 100004f4 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000031 00000035 00000039 0000003d (0)
|
|
%r15: 100000c4 100000d4 100000e4 100000f4 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 808
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a0c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf90633 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000001 00000005 00000009 0000000d (0)
|
|
%r12: 10000404 10000414 10000424 10000434 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000001 00000005 00000009 0000000d (0)
|
|
%r15: 10000004 10000014 10000024 10000034 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 809
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a10
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x478793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000011 00000015 00000019 0000001d (0)
|
|
%r12: 10000444 10000454 10000464 10000474 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000011 00000015 00000019 0000001d (0)
|
|
%r15: 10000048 10000058 10000068 10000078 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a10
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 810
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a10
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x478793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000021 00000025 00000029 0000002d (0)
|
|
%r12: 10000484 10000494 100004a4 100004b4 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000021 00000025 00000029 0000002d (0)
|
|
%r15: 10000088 10000098 100000a8 100000b8 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a10
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 811
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a10
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x478793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000031 00000035 00000039 0000003d (0)
|
|
%r12: 100004c4 100004d4 100004e4 100004f4 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000031 00000035 00000039 0000003d (0)
|
|
%r15: 100000c8 100000d8 100000e8 100000f8 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a10
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 812
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a10
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x478793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000001 00000005 00000009 0000000d (0)
|
|
%r12: 10000404 10000414 10000424 10000434 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000001 00000005 00000009 0000000d (0)
|
|
%r15: 10000008 10000018 10000028 10000038 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a10
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 813
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a14
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2b70733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000011 00000015 00000019 0000001d (0)
|
|
%r12: 10000444 10000454 10000464 10000474 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000121 000001b9 00000271 00000349 (0)
|
|
%r15: 10000048 10000058 10000068 10000078 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a14
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 814
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a14
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2b70733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000021 00000025 00000029 0000002d (0)
|
|
%r12: 10000484 10000494 100004a4 100004b4 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000441 00000559 00000691 000007e9 (0)
|
|
%r15: 10000088 10000098 100000a8 100000b8 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a14
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 815
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a14
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2b70733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000031 00000035 00000039 0000003d (0)
|
|
%r12: 100004c4 100004d4 100004e4 100004f4 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000961 00000af9 00000cb1 00000e89 (0)
|
|
%r15: 100000c8 100000d8 100000e8 100000f8 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a14
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 816
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a14
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2b70733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000001 00000005 00000009 0000000d (0)
|
|
%r12: 10000404 10000414 10000424 10000434 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000001 00000019 00000051 000000a9 (0)
|
|
%r15: 10000008 10000018 10000028 10000038 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a14
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 817
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a18
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xe62023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000444
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000454
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000464
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000474
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000011 00000015 00000019 0000001d (0)
|
|
%r12: 10000444 10000454 10000464 10000474 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000121 000001b9 00000271 00000349 (0)
|
|
%r15: 10000048 10000058 10000068 10000078 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 818
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a18
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xe62023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000484
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000494
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004a4
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004b4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000021 00000025 00000029 0000002d (0)
|
|
%r12: 10000484 10000494 100004a4 100004b4 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000441 00000559 00000691 000007e9 (0)
|
|
%r15: 10000088 10000098 100000a8 100000b8 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 819
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 820
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 821
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a18
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xe62023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004c4
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004d4
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004e4
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004f4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000031 00000035 00000039 0000003d (0)
|
|
%r12: 100004c4 100004d4 100004e4 100004f4 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000961 00000af9 00000cb1 00000e89 (0)
|
|
%r15: 100000c8 100000d8 100000e8 100000f8 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 822
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a18
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xe62023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000404
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000414
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000424
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000434
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000001 00000005 00000009 0000000d (0)
|
|
%r12: 10000404 10000414 10000424 10000434 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000001 00000019 00000051 000000a9 (0)
|
|
%r15: 10000008 10000018 10000028 10000038 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 823
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a1c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfef692e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000a00
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000011 00000015 00000019 0000001d (0)
|
|
%r12: 10000444 10000454 10000464 10000474 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000121 000001b9 00000271 00000349 (0)
|
|
%r15: 10000048 10000058 10000068 10000078 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a1c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 824
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a1c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfef692e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000a00
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000021 00000025 00000029 0000002d (0)
|
|
%r12: 10000484 10000494 100004a4 100004b4 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000441 00000559 00000691 000007e9 (0)
|
|
%r15: 10000088 10000098 100000a8 100000b8 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a1c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 825
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a1c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfef692e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000a00
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000031 00000035 00000039 0000003d (0)
|
|
%r12: 100004c4 100004d4 100004e4 100004f4 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000961 00000af9 00000cb1 00000e89 (0)
|
|
%r15: 100000c8 100000d8 100000e8 100000f8 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a1c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 826
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a1c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfef692e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000a00
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000001 00000005 00000009 0000000d (0)
|
|
%r12: 10000404 10000414 10000424 10000434 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000001 00000019 00000051 000000a9 (0)
|
|
%r15: 10000008 10000018 10000028 10000038 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a1c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 827
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 828
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 829
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a00
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf48733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000011 00000015 00000019 0000001d (0)
|
|
%r12: 10000444 10000454 10000464 10000474 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 10000248 10000258 10000268 10000278 (0)
|
|
%r15: 10000048 10000058 10000068 10000078 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=9, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 830
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a00
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf48733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000021 00000025 00000029 0000002d (0)
|
|
%r12: 10000484 10000494 100004a4 100004b4 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 10000288 10000298 100002a8 100002b8 (0)
|
|
%r15: 10000088 10000098 100000a8 100000b8 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=9, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 831
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a00
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf48733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000031 00000035 00000039 0000003d (0)
|
|
%r12: 100004c4 100004d4 100004e4 100004f4 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 100002c8 100002d8 100002e8 100002f8 (0)
|
|
%r15: 100000c8 100000d8 100000e8 100000f8 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=9, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 832
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a00
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf48733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000001 00000005 00000009 0000000d (0)
|
|
%r12: 10000404 10000414 10000424 10000434 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 10000208 10000218 10000228 10000238 (0)
|
|
%r15: 10000008 10000018 10000028 10000038 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=9, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 833
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a04
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x7a583 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000048
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 12
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000058
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 16
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000068
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 1a
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000078
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 1e
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000012 00000016 0000001a 0000001e (0)
|
|
%r12: 10000444 10000454 10000464 10000474 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 10000248 10000258 10000268 10000278 (0)
|
|
%r15: 10000048 10000058 10000068 10000078 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 834
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a04
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x7a583 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000088
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 22
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000098
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 26
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000a8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 2a
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000b8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 2e
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000022 00000026 0000002a 0000002e (0)
|
|
%r12: 10000484 10000494 100004a4 100004b4 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 10000288 10000298 100002a8 100002b8 (0)
|
|
%r15: 10000088 10000098 100000a8 100000b8 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 835
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a04
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x7a583 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000c8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 32
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000d8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 36
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000e8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 3a
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000f8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 3e
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000032 00000036 0000003a 0000003e (0)
|
|
%r12: 100004c4 100004d4 100004e4 100004f4 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 100002c8 100002d8 100002e8 100002f8 (0)
|
|
%r15: 100000c8 100000d8 100000e8 100000f8 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 836
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a04
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x7a583 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000008
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 2
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000018
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 6
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000028
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: a
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000038
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: e
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000002 00000006 0000000a 0000000e (0)
|
|
%r12: 10000404 10000414 10000424 10000434 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 10000208 10000218 10000228 10000238 (0)
|
|
%r15: 10000008 10000018 10000028 10000038 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 837
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 838
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 839
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a08
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x72703 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000248
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 12
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000258
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 16
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000268
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 1a
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000278
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 1e
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000012 00000016 0000001a 0000001e (0)
|
|
%r12: 10000444 10000454 10000464 10000474 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000012 00000016 0000001a 0000001e (0)
|
|
%r15: 10000048 10000058 10000068 10000078 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 840
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 841
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 842
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a08
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x72703 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000288
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 22
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000298
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 26
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002a8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 2a
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002b8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 2e
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000022 00000026 0000002a 0000002e (0)
|
|
%r12: 10000484 10000494 100004a4 100004b4 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000022 00000026 0000002a 0000002e (0)
|
|
%r15: 10000088 10000098 100000a8 100000b8 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 843
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 844
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 845
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a08
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x72703 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002c8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 32
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002d8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 36
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002e8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 3a
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002f8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 3e
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000032 00000036 0000003a 0000003e (0)
|
|
%r12: 100004c4 100004d4 100004e4 100004f4 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000032 00000036 0000003a 0000003e (0)
|
|
%r15: 100000c8 100000d8 100000e8 100000f8 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 846
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 847
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 848
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a08
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x72703 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000208
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 2
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000218
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 6
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000228
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: a
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 10000238
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: e
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000002 00000006 0000000a 0000000e (0)
|
|
%r12: 10000404 10000414 10000424 10000434 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000002 00000006 0000000a 0000000e (0)
|
|
%r15: 10000008 10000018 10000028 10000038 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 849
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 850
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 851
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a0c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf90633 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000012 00000016 0000001a 0000001e (0)
|
|
%r12: 10000448 10000458 10000468 10000478 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000012 00000016 0000001a 0000001e (0)
|
|
%r15: 10000048 10000058 10000068 10000078 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 852
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 853
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 854
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a0c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf90633 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000022 00000026 0000002a 0000002e (0)
|
|
%r12: 10000488 10000498 100004a8 100004b8 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000022 00000026 0000002a 0000002e (0)
|
|
%r15: 10000088 10000098 100000a8 100000b8 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 855
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 856
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 857
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a0c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf90633 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000032 00000036 0000003a 0000003e (0)
|
|
%r12: 100004c8 100004d8 100004e8 100004f8 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000032 00000036 0000003a 0000003e (0)
|
|
%r15: 100000c8 100000d8 100000e8 100000f8 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 858
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a0c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf90633 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000002 00000006 0000000a 0000000e (0)
|
|
%r12: 10000408 10000418 10000428 10000438 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000002 00000006 0000000a 0000000e (0)
|
|
%r15: 10000008 10000018 10000028 10000038 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 859
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a10
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x478793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000012 00000016 0000001a 0000001e (0)
|
|
%r12: 10000448 10000458 10000468 10000478 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000012 00000016 0000001a 0000001e (0)
|
|
%r15: 1000004c 1000005c 1000006c 1000007c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a10
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 860
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a10
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x478793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000022 00000026 0000002a 0000002e (0)
|
|
%r12: 10000488 10000498 100004a8 100004b8 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000022 00000026 0000002a 0000002e (0)
|
|
%r15: 1000008c 1000009c 100000ac 100000bc (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a10
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 861
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a10
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x478793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000032 00000036 0000003a 0000003e (0)
|
|
%r12: 100004c8 100004d8 100004e8 100004f8 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000032 00000036 0000003a 0000003e (0)
|
|
%r15: 100000cc 100000dc 100000ec 100000fc (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a10
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 862
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a10
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x478793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000002 00000006 0000000a 0000000e (0)
|
|
%r12: 10000408 10000418 10000428 10000438 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000002 00000006 0000000a 0000000e (0)
|
|
%r15: 1000000c 1000001c 1000002c 1000003c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a10
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 863
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a14
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2b70733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000012 00000016 0000001a 0000001e (0)
|
|
%r12: 10000448 10000458 10000468 10000478 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000144 000001e4 000002a4 00000384 (0)
|
|
%r15: 1000004c 1000005c 1000006c 1000007c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a14
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 864
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a14
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2b70733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000022 00000026 0000002a 0000002e (0)
|
|
%r12: 10000488 10000498 100004a8 100004b8 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000484 000005a4 000006e4 00000844 (0)
|
|
%r15: 1000008c 1000009c 100000ac 100000bc (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a14
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 865
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a14
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2b70733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000032 00000036 0000003a 0000003e (0)
|
|
%r12: 100004c8 100004d8 100004e8 100004f8 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 000009c4 00000b64 00000d24 00000f04 (0)
|
|
%r15: 100000cc 100000dc 100000ec 100000fc (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a14
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 866
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a14
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2b70733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000002 00000006 0000000a 0000000e (0)
|
|
%r12: 10000408 10000418 10000428 10000438 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000004 00000024 00000064 000000c4 (0)
|
|
%r15: 1000000c 1000001c 1000002c 1000003c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a14
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 867
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a18
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xe62023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000448
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000458
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000468
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000478
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000012 00000016 0000001a 0000001e (0)
|
|
%r12: 10000448 10000458 10000468 10000478 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000144 000001e4 000002a4 00000384 (0)
|
|
%r15: 1000004c 1000005c 1000006c 1000007c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 868
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a18
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xe62023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000488
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000498
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004a8
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004b8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000022 00000026 0000002a 0000002e (0)
|
|
%r12: 10000488 10000498 100004a8 100004b8 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000484 000005a4 000006e4 00000844 (0)
|
|
%r15: 1000008c 1000009c 100000ac 100000bc (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 869
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 870
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 871
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a18
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xe62023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004c8
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004d8
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004e8
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004f8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000032 00000036 0000003a 0000003e (0)
|
|
%r12: 100004c8 100004d8 100004e8 100004f8 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 000009c4 00000b64 00000d24 00000f04 (0)
|
|
%r15: 100000cc 100000dc 100000ec 100000fc (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 872
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a18
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xe62023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000408
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000418
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000428
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 10000438
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000002 00000006 0000000a 0000000e (0)
|
|
%r12: 10000408 10000418 10000428 10000438 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000004 00000024 00000064 000000c4 (0)
|
|
%r15: 1000000c 1000001c 1000002c 1000003c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 873
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a1c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfef692e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000a00
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000012 00000016 0000001a 0000001e (0)
|
|
%r12: 10000448 10000458 10000468 10000478 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000144 000001e4 000002a4 00000384 (0)
|
|
%r15: 1000004c 1000005c 1000006c 1000007c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a1c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 874
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a1c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfef692e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000a00
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000022 00000026 0000002a 0000002e (0)
|
|
%r12: 10000488 10000498 100004a8 100004b8 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000484 000005a4 000006e4 00000844 (0)
|
|
%r15: 1000008c 1000009c 100000ac 100000bc (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a1c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 875
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a1c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfef692e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000a00
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000032 00000036 0000003a 0000003e (0)
|
|
%r12: 100004c8 100004d8 100004e8 100004f8 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 000009c4 00000b64 00000d24 00000f04 (0)
|
|
%r15: 100000cc 100000dc 100000ec 100000fc (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a1c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 876
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a1c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfef692e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000a00
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000002 00000006 0000000a 0000000e (0)
|
|
%r12: 10000408 10000418 10000428 10000438 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000004 00000024 00000064 000000c4 (0)
|
|
%r15: 1000000c 1000001c 1000002c 1000003c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a1c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 877
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 878
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 879
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a00
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf48733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000012 00000016 0000001a 0000001e (0)
|
|
%r12: 10000448 10000458 10000468 10000478 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 1000024c 1000025c 1000026c 1000027c (0)
|
|
%r15: 1000004c 1000005c 1000006c 1000007c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=9, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 880
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a00
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf48733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000022 00000026 0000002a 0000002e (0)
|
|
%r12: 10000488 10000498 100004a8 100004b8 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 1000028c 1000029c 100002ac 100002bc (0)
|
|
%r15: 1000008c 1000009c 100000ac 100000bc (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=9, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 881
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a00
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf48733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000032 00000036 0000003a 0000003e (0)
|
|
%r12: 100004c8 100004d8 100004e8 100004f8 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 100002cc 100002dc 100002ec 100002fc (0)
|
|
%r15: 100000cc 100000dc 100000ec 100000fc (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=9, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 882
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a00
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf48733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r14 <- r9, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000002 00000006 0000000a 0000000e (0)
|
|
%r12: 10000408 10000418 10000428 10000438 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 1000020c 1000021c 1000022c 1000023c (0)
|
|
%r15: 1000000c 1000001c 1000002c 1000003c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=9, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 883
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a04
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x7a583 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 1000004c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 13
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 1000005c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 17
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 1000006c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 1b
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 1000007c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 1f
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000013 00000017 0000001b 0000001f (0)
|
|
%r12: 10000448 10000458 10000468 10000478 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 1000024c 1000025c 1000026c 1000027c (0)
|
|
%r15: 1000004c 1000005c 1000006c 1000007c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 884
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a04
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x7a583 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 1000008c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 23
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 1000009c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 27
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000ac
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 2b
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000bc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 2f
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000023 00000027 0000002b 0000002f (0)
|
|
%r12: 10000488 10000498 100004a8 100004b8 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 1000028c 1000029c 100002ac 100002bc (0)
|
|
%r15: 1000008c 1000009c 100000ac 100000bc (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 885
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a04
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x7a583 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000cc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 33
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000dc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 37
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000ec
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 3b
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100000fc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 3f
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000033 00000037 0000003b 0000003f (0)
|
|
%r12: 100004c8 100004d8 100004e8 100004f8 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 100002cc 100002dc 100002ec 100002fc (0)
|
|
%r15: 100000cc 100000dc 100000ec 100000fc (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 886
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a04
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x7a583 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 1000000c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 3
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 1000001c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 7
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 1000002c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: b
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r11 <- r15, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 1000003c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: f
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 10000408 10000418 10000428 10000438 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 1000020c 1000021c 1000022c 1000023c (0)
|
|
%r15: 1000000c 1000001c 1000002c 1000003c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 887
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 888
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 889
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a08
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x72703 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 1000024c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 13
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 1000025c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 17
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 1000026c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 1b
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 1000027c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 1f
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000013 00000017 0000001b 0000001f (0)
|
|
%r12: 10000448 10000458 10000468 10000478 (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000013 00000017 0000001b 0000001f (0)
|
|
%r15: 1000004c 1000005c 1000006c 1000007c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 890
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 891
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 892
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a08
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x72703 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 1000028c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 23
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 1000029c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 27
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002ac
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 2b
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002bc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 2f
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000023 00000027 0000002b 0000002f (0)
|
|
%r12: 10000488 10000498 100004a8 100004b8 (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000023 00000027 0000002b 0000002f (0)
|
|
%r15: 1000008c 1000009c 100000ac 100000bc (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 893
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 894
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 895
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a08
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x72703 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002cc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 33
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002dc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 37
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002ec
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 3b
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 100002fc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 3f
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000033 00000037 0000003b 0000003f (0)
|
|
%r12: 100004c8 100004d8 100004e8 100004f8 (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000033 00000037 0000003b 0000003f (0)
|
|
%r15: 100000cc 100000dc 100000ec 100000fc (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 896
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 897
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 898
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a08
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x72703 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 1000020c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 3
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 1000021c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 7
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 1000022c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: b
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r14, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 1000023c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: f
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 10000408 10000418 10000428 10000438 (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000003 00000007 0000000b 0000000f (0)
|
|
%r15: 1000000c 1000001c 1000002c 1000003c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 899
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 900
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 901
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a0c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf90633 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000013 00000017 0000001b 0000001f (0)
|
|
%r12: 1000044c 1000045c 1000046c 1000047c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000013 00000017 0000001b 0000001f (0)
|
|
%r15: 1000004c 1000005c 1000006c 1000007c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 902
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 903
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 904
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a0c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf90633 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000023 00000027 0000002b 0000002f (0)
|
|
%r12: 1000048c 1000049c 100004ac 100004bc (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000023 00000027 0000002b 0000002f (0)
|
|
%r15: 1000008c 1000009c 100000ac 100000bc (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 905
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 906
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 907
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a0c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf90633 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000033 00000037 0000003b 0000003f (0)
|
|
%r12: 100004cc 100004dc 100004ec 100004fc (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000033 00000037 0000003b 0000003f (0)
|
|
%r15: 100000cc 100000dc 100000ec 100000fc (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 908
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a0c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf90633 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r12 <- r18, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000003 00000007 0000000b 0000000f (0)
|
|
%r15: 1000000c 1000001c 1000002c 1000003c (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=12, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 909
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a10
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x478793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000013 00000017 0000001b 0000001f (0)
|
|
%r12: 1000044c 1000045c 1000046c 1000047c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000013 00000017 0000001b 0000001f (0)
|
|
%r15: 10000050 10000060 10000070 10000080 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a10
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 910
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a10
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x478793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000023 00000027 0000002b 0000002f (0)
|
|
%r12: 1000048c 1000049c 100004ac 100004bc (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 00000023 00000027 0000002b 0000002f (0)
|
|
%r15: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a10
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 911
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a10
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x478793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000033 00000037 0000003b 0000003f (0)
|
|
%r12: 100004cc 100004dc 100004ec 100004fc (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000033 00000037 0000003b 0000003f (0)
|
|
%r15: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a10
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 912
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a10
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x478793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000003 00000007 0000000b 0000000f (0)
|
|
%r15: 10000010 10000020 10000030 10000040 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a10
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 913
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a14
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2b70733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000013 00000017 0000001b 0000001f (0)
|
|
%r12: 1000044c 1000045c 1000046c 1000047c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000169 00000211 000002d9 000003c1 (0)
|
|
%r15: 10000050 10000060 10000070 10000080 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a14
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 914
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a14
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2b70733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000023 00000027 0000002b 0000002f (0)
|
|
%r12: 1000048c 1000049c 100004ac 100004bc (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 000004c9 000005f1 00000739 000008a1 (0)
|
|
%r15: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a14
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 915
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a14
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2b70733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000033 00000037 0000003b 0000003f (0)
|
|
%r12: 100004cc 100004dc 100004ec 100004fc (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000a29 00000bd1 00000d99 00000f81 (0)
|
|
%r15: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a14
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 916
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a14
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2b70733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/instruction.cpp:392: MUL: r14 <- r14, r11
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000009 00000031 00000079 000000e1 (0)
|
|
%r15: 10000010 10000020 10000030 10000040 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a14
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=14, trs2=11
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 917
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a18
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xe62023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 1000044c
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 1000045c
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 1000046c
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 1000047c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000013 00000017 0000001b 0000001f (0)
|
|
%r12: 1000044c 1000045c 1000046c 1000047c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000169 00000211 000002d9 000003c1 (0)
|
|
%r15: 10000050 10000060 10000070 10000080 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 918
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a18
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xe62023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 1000048c
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 1000049c
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004ac
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004bc
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000023 00000027 0000002b 0000002f (0)
|
|
%r12: 1000048c 1000049c 100004ac 100004bc (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 000004c9 000005f1 00000739 000008a1 (0)
|
|
%r15: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 919
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 920
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 921
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a18
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xe62023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004cc
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004dc
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004ec
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 100004fc
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000033 00000037 0000003b 0000003f (0)
|
|
%r12: 100004cc 100004dc 100004ec 100004fc (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000a29 00000bd1 00000d99 00000f81 (0)
|
|
%r15: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 922
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a18
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xe62023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 1000040c
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 1000041c
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 1000042c
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r14 <- r12, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 1000043c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000009 00000031 00000079 000000e1 (0)
|
|
%r15: 10000010 10000020 10000030 10000040 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=12, trs2=14
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 923
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a1c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfef692e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000013 00000017 0000001b 0000001f (0)
|
|
%r12: 1000044c 1000045c 1000046c 1000047c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000169 00000211 000002d9 000003c1 (0)
|
|
%r15: 10000050 10000060 10000070 10000080 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a1c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 924
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a1c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfef692e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000023 00000027 0000002b 0000002f (0)
|
|
%r12: 1000048c 1000049c 100004ac 100004bc (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 000004c9 000005f1 00000739 000008a1 (0)
|
|
%r15: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a1c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 925
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a1c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfef692e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000033 00000037 0000003b 0000003f (0)
|
|
%r12: 100004cc 100004dc 100004ec 100004fc (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000a29 00000bd1 00000d99 00000f81 (0)
|
|
%r15: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a1c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 926
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a1c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfef692e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r13, r15, imm=-28
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800009d0 800009d0 800009d0 800009d0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000009 00000031 00000079 000000e1 (0)
|
|
%r15: 10000010 10000020 10000030 10000040 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a1c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 927
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 928
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 929
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a20
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1c12083 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffefec
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 8000080c
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffec00
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 8000080c
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffe804
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 8000080c
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffe408
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 8000080c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000004 00000005 00000006 00000007 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000013 00000017 0000001b 0000001f (0)
|
|
%r12: 1000044c 1000045c 1000046c 1000047c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000169 00000211 000002d9 000003c1 (0)
|
|
%r15: 10000050 10000060 10000070 10000080 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a20
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 930
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a20
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1c12083 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffefec
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 8000080c
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffec00
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 8000080c
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffe804
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 8000080c
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffe408
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 8000080c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000008 00000009 0000000a 0000000b (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000023 00000027 0000002b 0000002f (0)
|
|
%r12: 1000048c 1000049c 100004ac 100004bc (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 000004c9 000005f1 00000739 000008a1 (0)
|
|
%r15: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a20
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 931
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a20
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1c12083 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffefec
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 8000080c
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffec00
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 8000080c
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffe804
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 8000080c
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffe408
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 8000080c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 0000000c 0000000d 0000000e 0000000f (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000033 00000037 0000003b 0000003f (0)
|
|
%r12: 100004cc 100004dc 100004ec 100004fc (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000a29 00000bd1 00000d99 00000f81 (0)
|
|
%r15: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a20
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 932
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a20
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1c12083 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffefec
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 800008c0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffec00
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 800008c0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffe804
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 800008c0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffe408
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 800008c0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c0 800008c0 800008c0 800008c0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000001 00000002 00000003 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000009 00000031 00000079 000000e1 (0)
|
|
%r15: 10000010 10000020 10000030 10000040 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a20
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 933
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a20
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 934
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a20
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 935
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a20
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 936
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a20
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 937
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a20
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 938
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a20
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 939
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a20
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 940
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a20
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 941
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a20
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 942
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a20
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 943
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a20
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 944
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a24
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1812403 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffefe8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffebfc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffe800
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffe404
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000013 00000017 0000001b 0000001f (0)
|
|
%r12: 1000044c 1000045c 1000046c 1000047c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000169 00000211 000002d9 000003c1 (0)
|
|
%r15: 10000050 10000060 10000070 10000080 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 945
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 946
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 947
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 948
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 949
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 950
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 951
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 952
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 953
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 954
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 955
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 956
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a24
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1812403 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffefe8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffebfc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffe800
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffe404
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000023 00000027 0000002b 0000002f (0)
|
|
%r12: 1000048c 1000049c 100004ac 100004bc (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 000004c9 000005f1 00000739 000008a1 (0)
|
|
%r15: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 957
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 958
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 959
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 960
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 961
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 962
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 963
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 964
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 965
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 966
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 967
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 968
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a24
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1812403 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffefe8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffebfc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffe800
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffe404
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000033 00000037 0000003b 0000003f (0)
|
|
%r12: 100004cc 100004dc 100004ec 100004fc (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000a29 00000bd1 00000d99 00000f81 (0)
|
|
%r15: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 969
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 970
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 971
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 972
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 973
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 974
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a24
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1812403 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffefe8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffebfc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffe800
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffe404
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c0 800008c0 800008c0 800008c0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000200 00000200 00000200 00000200 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000009 00000031 00000079 000000e1 (0)
|
|
%r15: 10000010 10000020 10000030 10000040 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 975
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 976
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 977
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 978
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 979
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 980
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 981
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 982
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 983
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 984
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 985
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a24
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 986
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a28
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1412483 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffefe4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffebf8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffe7fc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffe400
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000013 00000017 0000001b 0000001f (0)
|
|
%r12: 1000044c 1000045c 1000046c 1000047c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000169 00000211 000002d9 000003c1 (0)
|
|
%r15: 10000050 10000060 10000070 10000080 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 987
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 988
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 989
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 990
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 991
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 992
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 993
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 994
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 995
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 996
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 997
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 998
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a28
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1412483 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffefe4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffebf8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffe7fc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffe400
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000023 00000027 0000002b 0000002f (0)
|
|
%r12: 1000048c 1000049c 100004ac 100004bc (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 000004c9 000005f1 00000739 000008a1 (0)
|
|
%r15: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 999
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1000
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1001
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a28
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1412483 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffefe4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffebf8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffe7fc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffe400
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000033 00000037 0000003b 0000003f (0)
|
|
%r12: 100004cc 100004dc 100004ec 100004fc (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000a29 00000bd1 00000d99 00000f81 (0)
|
|
%r15: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1002
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1003
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1004
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1005
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1006
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1007
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1008
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1009
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1010
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1011
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1012
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1013
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a28
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1412483 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffefe4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffebf8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffe7fc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffe400
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c0 800008c0 800008c0 800008c0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000009 00000031 00000079 000000e1 (0)
|
|
%r15: 10000010 10000020 10000030 10000040 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000400 00000400 00000400 00000400 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1014
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1015
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1016
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1017
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1018
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1019
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1020
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1021
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1022
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1023
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1024
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a28
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1025
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a2c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1012903 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffefe0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffebf4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffe7f8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffe3fc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000013 00000017 0000001b 0000001f (0)
|
|
%r12: 1000044c 1000045c 1000046c 1000047c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000169 00000211 000002d9 000003c1 (0)
|
|
%r15: 10000050 10000060 10000070 10000080 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1026
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1027
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1028
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1029
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1030
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1031
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1032
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1033
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1034
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1035
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1036
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1037
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a2c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1012903 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffefe0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffebf4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffe7f8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffe3fc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000023 00000027 0000002b 0000002f (0)
|
|
%r12: 1000048c 1000049c 100004ac 100004bc (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 000004c9 000005f1 00000739 000008a1 (0)
|
|
%r15: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1038
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1039
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1040
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1041
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1042
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1043
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1044
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1045
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1046
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1047
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1048
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1049
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a2c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1012903 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffefe0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffebf4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffe7f8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffe3fc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000033 00000037 0000003b 0000003f (0)
|
|
%r12: 100004cc 100004dc 100004ec 100004fc (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000a29 00000bd1 00000d99 00000f81 (0)
|
|
%r15: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1050
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1051
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1052
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a2c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1012903 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffefe0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffebf4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffe7f8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffe3fc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c0 800008c0 800008c0 800008c0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000009 00000031 00000079 000000e1 (0)
|
|
%r15: 10000010 10000020 10000030 10000040 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 7fffff00 7fffff00 7fffff00 7fffff00 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1053
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1054
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1055
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1056
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1057
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1058
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1059
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1060
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1061
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1062
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1063
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a2c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1064
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a30
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xc12983 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffefdc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffebf0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffe7f4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffe3f8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000013 00000017 0000001b 0000001f (0)
|
|
%r12: 1000044c 1000045c 1000046c 1000047c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000169 00000211 000002d9 000003c1 (0)
|
|
%r15: 10000050 10000060 10000070 10000080 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1065
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1066
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1067
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1068
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1069
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1070
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1071
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1072
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1073
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1074
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1075
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1076
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a30
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xc12983 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffefdc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffebf0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffe7f4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffe3f8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000023 00000027 0000002b 0000002f (0)
|
|
%r12: 1000048c 1000049c 100004ac 100004bc (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 000004c9 000005f1 00000739 000008a1 (0)
|
|
%r15: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1077
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1078
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1079
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1080
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1081
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1082
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1083
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1084
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1085
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1086
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1087
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1088
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a30
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xc12983 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffefdc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffebf0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffe7f4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffe3f8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000033 00000037 0000003b 0000003f (0)
|
|
%r12: 100004cc 100004dc 100004ec 100004fc (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000a29 00000bd1 00000d99 00000f81 (0)
|
|
%r15: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1089
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1090
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1091
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1092
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1093
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1094
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a30
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xc12983 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffefdc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffebf0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffe7f4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r19 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffe3f8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c0 800008c0 800008c0 800008c0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000009 00000031 00000079 000000e1 (0)
|
|
%r15: 10000010 10000020 10000030 10000040 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 10000000 10000000 10000000 10000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1095
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1096
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1097
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1098
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1099
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1100
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1101
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1102
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1103
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1104
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1105
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a30
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1106
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a34
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x812a03 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffefd8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffebec
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffe7f0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffe3f4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 6bffefd0 6bffebe4 6bffe7e8 6bffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000013 00000017 0000001b 0000001f (0)
|
|
%r12: 1000044c 1000045c 1000046c 1000047c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000169 00000211 000002d9 000003c1 (0)
|
|
%r15: 10000050 10000060 10000070 10000080 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1107
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1108
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1109
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1110
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1111
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1112
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1113
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1114
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1115
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1116
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1117
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1118
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a34
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x812a03 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffefd8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffebec
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffe7f0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffe3f4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 67ffefd0 67ffebe4 67ffe7e8 67ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000023 00000027 0000002b 0000002f (0)
|
|
%r12: 1000048c 1000049c 100004ac 100004bc (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 000004c9 000005f1 00000739 000008a1 (0)
|
|
%r15: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1119
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1120
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1121
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1122
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1123
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1124
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1125
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1126
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1127
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1128
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1129
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1130
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a34
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x812a03 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffefd8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffebec
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffe7f0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffe3f4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 63ffefd0 63ffebe4 63ffe7e8 63ffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000033 00000037 0000003b 0000003f (0)
|
|
%r12: 100004cc 100004dc 100004ec 100004fc (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000a29 00000bd1 00000d99 00000f81 (0)
|
|
%r15: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1131
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1132
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1133
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1134
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1135
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1136
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a34
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x812a03 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffefd8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffebec
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffe7f0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffe3f4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c0 800008c0 800008c0 800008c0 (0)
|
|
%r 2: 6fffefd0 6fffebe4 6fffe7e8 6fffe3ec (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000009 00000031 00000079 000000e1 (0)
|
|
%r15: 10000010 10000020 10000030 10000040 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1137
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1138
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1139
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1140
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1141
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1142
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1143
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1144
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1145
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1146
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1147
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a34
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1148
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a38
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=32
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000013 00000017 0000001b 0000001f (0)
|
|
%r12: 1000044c 1000045c 1000046c 1000047c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000169 00000211 000002d9 000003c1 (0)
|
|
%r15: 10000050 10000060 10000070 10000080 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1149
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1150
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1151
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1152
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1153
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1154
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1155
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1156
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1157
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1158
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1159
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1160
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a38
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=32
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000023 00000027 0000002b 0000002f (0)
|
|
%r12: 1000048c 1000049c 100004ac 100004bc (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 000004c9 000005f1 00000739 000008a1 (0)
|
|
%r15: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1161
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1162
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1163
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1164
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1165
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1166
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1167
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1168
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1169
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1170
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1171
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1172
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a38
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=32
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000033 00000037 0000003b 0000003f (0)
|
|
%r12: 100004cc 100004dc 100004ec 100004fc (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000a29 00000bd1 00000d99 00000f81 (0)
|
|
%r15: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1173
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a38
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=32
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c0 800008c0 800008c0 800008c0 (0)
|
|
%r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000009 00000031 00000079 000000e1 (0)
|
|
%r15: 10000010 10000020 10000030 10000040 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a38
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1174
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a3c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 8000080c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000013 00000017 0000001b 0000001f (0)
|
|
%r12: 1000044c 1000045c 1000046c 1000047c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000169 00000211 000002d9 000003c1 (0)
|
|
%r15: 10000050 10000060 10000070 10000080 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a3c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1175
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a3c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 8000080c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000023 00000027 0000002b 0000002f (0)
|
|
%r12: 1000048c 1000049c 100004ac 100004bc (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 000004c9 000005f1 00000739 000008a1 (0)
|
|
%r15: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a3c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1176
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a3c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 8000080c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 8000080c 8000080c 8000080c 8000080c (0)
|
|
%r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000033 00000037 0000003b 0000003f (0)
|
|
%r12: 100004cc 100004dc 100004ec 100004fc (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000a29 00000bd1 00000d99 00000f81 (0)
|
|
%r15: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a3c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1177
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a3c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 800008c0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c0 800008c0 800008c0 800008c0 (0)
|
|
%r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000009 00000031 00000079 000000e1 (0)
|
|
%r15: 10000010 10000020 10000030 10000040 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a3c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1178
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1179
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1180
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000080c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf3dff0ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-196
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-196
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-196
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-196
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000748
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000810 80000810 80000810 80000810 (0)
|
|
%r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000013 00000017 0000001b 0000001f (0)
|
|
%r12: 1000044c 1000045c 1000046c 1000047c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000169 00000211 000002d9 000003c1 (0)
|
|
%r15: 10000050 10000060 10000070 10000080 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000080c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1181
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 0 1
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000080c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf3dff0ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-196
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-196
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-196
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-196
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000748
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000810 80000810 80000810 80000810 (0)
|
|
%r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000023 00000027 0000002b 0000002f (0)
|
|
%r12: 1000048c 1000049c 100004ac 100004bc (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 000004c9 000005f1 00000739 000008a1 (0)
|
|
%r15: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000080c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1182
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000080c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf3dff0ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-196
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-196
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-196
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-196
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000748
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000810 80000810 80000810 80000810 (0)
|
|
%r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000033 00000037 0000003b 0000003f (0)
|
|
%r12: 100004cc 100004dc 100004ec 100004fc (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000a29 00000bd1 00000d99 00000f81 (0)
|
|
%r15: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000080c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1183
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800008c0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xe89ff0ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-376
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-376
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-376
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-376
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000748
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c4 800008c4 800008c4 800008c4 (0)
|
|
%r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000001 00000002 00000003 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000009 00000031 00000079 000000e1 (0)
|
|
%r15: 10000010 10000020 10000030 10000040 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1184
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1185
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1186
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008c0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1187
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1188
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000748
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2102573 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=2
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=2
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=2
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000810 80000810 80000810 80000810 (0)
|
|
%r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000002 00000002 00000002 00000002 (0)
|
|
%r11: 00000023 00000027 0000002b 0000002f (0)
|
|
%r12: 1000048c 1000049c 100004ac 100004bc (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 000004c9 000005f1 00000739 000008a1 (0)
|
|
%r15: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000748
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1189
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000748
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2102573 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=3
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=3
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=3
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=3
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000810 80000810 80000810 80000810 (0)
|
|
%r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000003 00000003 00000003 00000003 (0)
|
|
%r11: 00000033 00000037 0000003b 0000003f (0)
|
|
%r12: 100004cc 100004dc 100004ec 100004fc (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000a29 00000bd1 00000d99 00000f81 (0)
|
|
%r15: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000748
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1190
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000748
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2102573 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=1
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=1
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=1
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=1
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000810 80000810 80000810 80000810 (0)
|
|
%r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000001 00000001 00000001 00000001 (0)
|
|
%r11: 00000013 00000017 0000001b 0000001f (0)
|
|
%r12: 1000044c 1000045c 1000046c 1000047c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000169 00000211 000002d9 000003c1 (0)
|
|
%r15: 10000050 10000060 10000070 10000080 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000748
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1191
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000074c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000810
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000810 80000810 80000810 80000810 (0)
|
|
%r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000002 00000002 00000002 00000002 (0)
|
|
%r11: 00000023 00000027 0000002b 0000002f (0)
|
|
%r12: 1000048c 1000049c 100004ac 100004bc (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 000004c9 000005f1 00000739 000008a1 (0)
|
|
%r15: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000074c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1192
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 1 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000074c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000810
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000810 80000810 80000810 80000810 (0)
|
|
%r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000003 00000003 00000003 00000003 (0)
|
|
%r11: 00000033 00000037 0000003b 0000003f (0)
|
|
%r12: 100004cc 100004dc 100004ec 100004fc (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000a29 00000bd1 00000d99 00000f81 (0)
|
|
%r15: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000074c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1193
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000748
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2102573 into: SYS
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=0
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=0
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=0
|
|
DEBUG ../../../../simX/instruction.cpp:781: SYS_INST: r10 <- r0, imm=33
|
|
DEBUG ../../../../simX/instruction.cpp:792: vx_warpID: r10=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c4 800008c4 800008c4 800008c4 (0)
|
|
%r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000000 00000000 00000000 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000009 00000031 00000079 000000e1 (0)
|
|
%r15: 10000010 10000020 10000030 10000040 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000748
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1194
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000074c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000810
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000810 80000810 80000810 80000810 (0)
|
|
%r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000001 00000001 00000001 00000001 (0)
|
|
%r11: 00000013 00000017 0000001b 0000001f (0)
|
|
%r12: 1000044c 1000045c 1000046c 1000047c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000169 00000211 000002d9 000003c1 (0)
|
|
%r15: 10000050 10000060 10000070 10000080 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000074c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1195
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000074c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 800008c4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c4 800008c4 800008c4 800008c4 (0)
|
|
%r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000000 00000000 00000000 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000009 00000031 00000079 000000e1 (0)
|
|
%r15: 10000010 10000020 10000030 10000040 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000074c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1196
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1197
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 0 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000810
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xc12083 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffeffc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffec10
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: ddccbbaa
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffe814
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: ddccbbaa
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 67ffe418
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: ddccbbaa
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000002 00000002 00000002 00000002 (0)
|
|
%r11: 00000023 00000027 0000002b 0000002f (0)
|
|
%r12: 1000048c 1000049c 100004ac 100004bc (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 000004c9 000005f1 00000739 000008a1 (0)
|
|
%r15: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000810
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=9
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1198
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000810
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xc12083 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffeffc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffec10
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: ddccbbaa
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffe814
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: ddccbbaa
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 63ffe418
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: ddccbbaa
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000003 00000003 00000003 00000003 (0)
|
|
%r11: 00000033 00000037 0000003b 0000003f (0)
|
|
%r12: 100004cc 100004dc 100004ec 100004fc (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000a29 00000bd1 00000d99 00000f81 (0)
|
|
%r15: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000810
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1199
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000814
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x153513 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:601: SLTIU: r10 <- r10, imm=1
|
|
DEBUG ../../../../simX/instruction.cpp:601: SLTIU: r10 <- r10, imm=1
|
|
DEBUG ../../../../simX/instruction.cpp:601: SLTIU: r10 <- r10, imm=1
|
|
DEBUG ../../../../simX/instruction.cpp:601: SLTIU: r10 <- r10, imm=1
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000000 00000000 00000000 (0)
|
|
%r11: 00000023 00000027 0000002b 0000002f (0)
|
|
%r12: 1000048c 1000049c 100004ac 100004bc (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 000004c9 000005f1 00000739 000008a1 (0)
|
|
%r15: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000814
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1200
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000814
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x153513 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:601: SLTIU: r10 <- r10, imm=1
|
|
DEBUG ../../../../simX/instruction.cpp:601: SLTIU: r10 <- r10, imm=1
|
|
DEBUG ../../../../simX/instruction.cpp:601: SLTIU: r10 <- r10, imm=1
|
|
DEBUG ../../../../simX/instruction.cpp:601: SLTIU: r10 <- r10, imm=1
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000000 00000000 00000000 (0)
|
|
%r11: 00000033 00000037 0000003b 0000003f (0)
|
|
%r12: 100004cc 100004dc 100004ec 100004fc (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000a29 00000bd1 00000d99 00000f81 (0)
|
|
%r15: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000814
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1201
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000814
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1202
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000814
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1203
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000814
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1204
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000814
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1205
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000814
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1206
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000814
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1207
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000814
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1208
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000814
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1209
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800008c4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x812403 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffeff8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffec0c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: ddccbbaa
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffe810
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: ddccbbaa
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffe414
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: ddccbbaa
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 800008c4 800008c4 800008c4 800008c4 (0)
|
|
%r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000000 00000000 00000000 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000009 00000031 00000079 000000e1 (0)
|
|
%r15: 10000010 10000020 10000030 10000040 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008c4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=6
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1210
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000810
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xc12083 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffeffc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffec10
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: ddccbbaa
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffe814
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: ddccbbaa
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6bffe418
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: ddccbbaa
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000001 00000001 00000001 00000001 (0)
|
|
%r11: 00000013 00000017 0000001b 0000001f (0)
|
|
%r12: 1000044c 1000045c 1000046c 1000047c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000169 00000211 000002d9 000003c1 (0)
|
|
%r15: 10000050 10000060 10000070 10000080 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000810
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=12
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1211
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000818
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=16
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 2: 67fff000 67ffec14 67ffe818 67ffe41c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000000 00000000 00000000 (0)
|
|
%r11: 00000023 00000027 0000002b 0000002f (0)
|
|
%r12: 1000048c 1000049c 100004ac 100004bc (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 000004c9 000005f1 00000739 000008a1 (0)
|
|
%r15: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000818
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1212
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000818
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1213
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000818
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1214
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000818
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1215
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000818
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1216
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000818
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1217
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000818
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1218
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000818
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1219
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000818
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1220
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000818
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1221
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000818
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=16
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 2: 63fff000 63ffec14 63ffe818 63ffe41c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000000 00000000 00000000 (0)
|
|
%r11: 00000033 00000037 0000003b 0000003f (0)
|
|
%r12: 100004cc 100004dc 100004ec 100004fc (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000a29 00000bd1 00000d99 00000f81 (0)
|
|
%r15: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000818
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1222
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000818
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1223
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000818
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1224
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000818
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1225
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000818
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1226
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000818
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1227
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800008c8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xc12083 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffeffc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80000044
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffec10
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: ddccbbaa
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffe814
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: ddccbbaa
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffe418
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: ddccbbaa
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000044 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000000 00000000 00000000 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000009 00000031 00000079 000000e1 (0)
|
|
%r15: 10000010 10000020 10000030 10000040 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008c8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1228
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000814
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x153513 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:601: SLTIU: r10 <- r10, imm=1
|
|
DEBUG ../../../../simX/instruction.cpp:601: SLTIU: r10 <- r10, imm=1
|
|
DEBUG ../../../../simX/instruction.cpp:601: SLTIU: r10 <- r10, imm=1
|
|
DEBUG ../../../../simX/instruction.cpp:601: SLTIU: r10 <- r10, imm=1
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000000 00000000 00000000 (0)
|
|
%r11: 00000013 00000017 0000001b 0000001f (0)
|
|
%r12: 1000044c 1000045c 1000046c 1000047c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000169 00000211 000002d9 000003c1 (0)
|
|
%r15: 10000050 10000060 10000070 10000080 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000814
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1229
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000081c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf0dff06f into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r0 <- imm=-244
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r0 <- imm=-244
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r0 <- imm=-244
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r0 <- imm=-244
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000728
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 2: 67fff000 67ffec14 67ffe818 67ffe41c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000000 00000000 00000000 (0)
|
|
%r11: 00000023 00000027 0000002b 0000002f (0)
|
|
%r12: 1000048c 1000049c 100004ac 100004bc (0)
|
|
%r13: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r14: 000004c9 000005f1 00000739 000008a1 (0)
|
|
%r15: 10000090 100000a0 100000b0 100000c0 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000081c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1230
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 1 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000081c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1231
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 1 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000081c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1232
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 1 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000081c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1233
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 1 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000081c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1234
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 1 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000081c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1235
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 1 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000081c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1236
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 1 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000081c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1237
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 1 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000081c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1238
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 1 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000081c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1239
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 1 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000081c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf0dff06f into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r0 <- imm=-244
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r0 <- imm=-244
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r0 <- imm=-244
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r0 <- imm=-244
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000728
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 2: 63fff000 63ffec14 63ffe818 63ffe41c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000000 00000000 00000000 (0)
|
|
%r11: 00000033 00000037 0000003b 0000003f (0)
|
|
%r12: 100004cc 100004dc 100004ec 100004fc (0)
|
|
%r13: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r14: 00000a29 00000bd1 00000d99 00000f81 (0)
|
|
%r15: 100000d0 100000e0 100000f0 10000100 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000081c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1240
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800008cc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x412483 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffeff4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffec08
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: ddccbbaa
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffe80c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: ddccbbaa
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffe410
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: ddccbbaa
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000044 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 9: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r10: 00000000 00000000 00000000 00000000 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000009 00000031 00000079 000000e1 (0)
|
|
%r15: 10000010 10000020 10000030 10000040 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008cc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1241
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000818
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=16
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 2: 6bfff000 6bffec14 6bffe818 6bffe41c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000000 00000000 00000000 (0)
|
|
%r11: 00000013 00000017 0000001b 0000001f (0)
|
|
%r12: 1000044c 1000045c 1000046c 1000047c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000169 00000211 000002d9 000003c1 (0)
|
|
%r15: 10000050 10000060 10000070 10000080 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000818
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1242
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800008d0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x12903 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r2, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffeff0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r2, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffec04
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: ddccbbaa
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r2, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffe808
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: ddccbbaa
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r2, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffe40c
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: ddccbbaa
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000044 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 9: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r10: 00000000 00000000 00000000 00000000 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000009 00000031 00000079 000000e1 (0)
|
|
%r15: 10000010 10000020 10000030 10000040 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008d0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1243
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:645: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008d0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1244
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000081c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf0dff06f into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r0 <- imm=-244
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r0 <- imm=-244
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r0 <- imm=-244
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r0 <- imm=-244
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000728
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 2: 6bfff000 6bffec14 6bffe818 6bffe41c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 00000000 00000000 00000000 00000000 (0)
|
|
%r 6: 00000000 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 00000000 00000000 00000000 (0)
|
|
%r 9: 00000000 00000000 00000000 00000000 (0)
|
|
%r10: 00000000 00000000 00000000 00000000 (0)
|
|
%r11: 00000013 00000017 0000001b 0000001f (0)
|
|
%r12: 1000044c 1000045c 1000046c 1000047c (0)
|
|
%r13: 10000050 10000060 10000070 10000080 (0)
|
|
%r14: 00000169 00000211 000002d9 000003c1 (0)
|
|
%r15: 10000050 10000060 10000070 10000080 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 00000000 00000000 00000000 (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000081c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1245
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000728
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x5006b into: gpgpu
|
|
DEBUG ../../../../simX/instruction.cpp:982: TMC: r10
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0:(0)
|
|
%r 1:(0)
|
|
%r 2:(0)
|
|
%r 3:(0)
|
|
%r 4:(0)
|
|
%r 5:(0)
|
|
%r 6:(0)
|
|
%r 7:(0)
|
|
%r 8:(0)
|
|
%r 9:(0)
|
|
%r10:(0)
|
|
%r11:(0)
|
|
%r12:(0)
|
|
%r13:(0)
|
|
%r14:(0)
|
|
%r15:(0)
|
|
%r16:(0)
|
|
%r17:(0)
|
|
%r18:(0)
|
|
%r19:(0)
|
|
%r20:(0)
|
|
%r21:(0)
|
|
%r22:(0)
|
|
%r23:(0)
|
|
%r24:(0)
|
|
%r25:(0)
|
|
%r26:(0)
|
|
%r27:(0)
|
|
%r28:(0)
|
|
%r29:(0)
|
|
%r30:(0)
|
|
%r31:(0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:416: ** warp #2 active threads changed from 4 to 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000728
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1246
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000728
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x5006b into: gpgpu
|
|
DEBUG ../../../../simX/instruction.cpp:982: TMC: r10
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0:(0)
|
|
%r 1:(0)
|
|
%r 2:(0)
|
|
%r 3:(0)
|
|
%r 4:(0)
|
|
%r 5:(0)
|
|
%r 6:(0)
|
|
%r 7:(0)
|
|
%r 8:(0)
|
|
%r 9:(0)
|
|
%r10:(0)
|
|
%r11:(0)
|
|
%r12:(0)
|
|
%r13:(0)
|
|
%r14:(0)
|
|
%r15:(0)
|
|
%r16:(0)
|
|
%r17:(0)
|
|
%r18:(0)
|
|
%r19:(0)
|
|
%r20:(0)
|
|
%r21:(0)
|
|
%r22:(0)
|
|
%r23:(0)
|
|
%r24:(0)
|
|
%r25:(0)
|
|
%r26:(0)
|
|
%r27:(0)
|
|
%r28:(0)
|
|
%r29:(0)
|
|
%r30:(0)
|
|
%r31:(0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:416: ** warp #3 active threads changed from 4 to 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000728
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1247
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800008d4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x153513 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:601: SLTIU: r10 <- r10, imm=1
|
|
DEBUG ../../../../simX/instruction.cpp:601: SLTIU: r10 <- r10, imm=1
|
|
DEBUG ../../../../simX/instruction.cpp:601: SLTIU: r10 <- r10, imm=1
|
|
DEBUG ../../../../simX/instruction.cpp:601: SLTIU: r10 <- r10, imm=1
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000044 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 2: 6fffeff0 6fffec04 6fffe808 6fffe40c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 9: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r10: 00000001 00000001 00000001 00000001 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000009 00000031 00000079 000000e1 (0)
|
|
%r15: 10000010 10000020 10000030 10000040 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008d4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1248
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800008d8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=16
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000044 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 2: 6ffff000 6fffec14 6fffe818 6fffe41c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 9: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r10: 00000001 00000001 00000001 00000001 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000009 00000031 00000079 000000e1 (0)
|
|
%r15: 10000010 10000020 10000030 10000040 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008d8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1249
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800008dc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xe4dff06f into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r0 <- imm=-436
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r0 <- imm=-436
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r0 <- imm=-436
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r0 <- imm=-436
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000728
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 00000000 00000000 00000000 (0)
|
|
%r 1: 80000044 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 2: 6ffff000 6fffec14 6fffe818 6fffe41c (0)
|
|
%r 3: 80016ba8 80016ba8 80016ba8 80016ba8 (0)
|
|
%r 4: 00000000 00000000 00000000 00000000 (0)
|
|
%r 5: 80000bc8 00000000 00000000 00000000 (0)
|
|
%r 6: 0000000f 00000000 00000000 00000000 (0)
|
|
%r 7: 00000000 00000000 00000000 00000000 (0)
|
|
%r 8: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r 9: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r10: 00000001 00000001 00000001 00000001 (0)
|
|
%r11: 00000003 00000007 0000000b 0000000f (0)
|
|
%r12: 1000040c 1000041c 1000042c 1000043c (0)
|
|
%r13: 10000010 10000020 10000030 10000040 (0)
|
|
%r14: 00000009 00000031 00000079 000000e1 (0)
|
|
%r15: 10000010 10000020 10000030 10000040 (0)
|
|
%r16: 00000000 00000000 00000000 00000000 (0)
|
|
%r17: 00000000 00000000 00000000 00000000 (0)
|
|
%r18: 00000000 ddccbbaa ddccbbaa ddccbbaa (0)
|
|
%r19: 00000000 00000000 00000000 00000000 (0)
|
|
%r20: 00000000 00000000 00000000 00000000 (0)
|
|
%r21: 00000000 00000000 00000000 00000000 (0)
|
|
%r22: 00000000 00000000 00000000 00000000 (0)
|
|
%r23: 00000000 00000000 00000000 00000000 (0)
|
|
%r24: 00000000 00000000 00000000 00000000 (0)
|
|
%r25: 00000000 00000000 00000000 00000000 (0)
|
|
%r26: 00000000 00000000 00000000 00000000 (0)
|
|
%r27: 00000000 00000000 00000000 00000000 (0)
|
|
%r28: 00000000 00000000 00000000 00000000 (0)
|
|
%r29: 00000000 00000000 00000000 00000000 (0)
|
|
%r30: 00000000 00000000 00000000 00000000 (0)
|
|
%r31: 00000000 00000000 00000000 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800008dc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1250
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 1 1
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000728
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x5006b into: gpgpu
|
|
DEBUG ../../../../simX/instruction.cpp:982: TMC: r10
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0:(0)
|
|
%r 1:(0)
|
|
%r 2:(0)
|
|
%r 3:(0)
|
|
%r 4:(0)
|
|
%r 5:(0)
|
|
%r 6:(0)
|
|
%r 7:(0)
|
|
%r 8:(0)
|
|
%r 9:(0)
|
|
%r10:(0)
|
|
%r11:(0)
|
|
%r12:(0)
|
|
%r13:(0)
|
|
%r14:(0)
|
|
%r15:(0)
|
|
%r16:(0)
|
|
%r17:(0)
|
|
%r18:(0)
|
|
%r19:(0)
|
|
%r20:(0)
|
|
%r21:(0)
|
|
%r22:(0)
|
|
%r23:(0)
|
|
%r24:(0)
|
|
%r25:(0)
|
|
%r26:(0)
|
|
%r27:(0)
|
|
%r28:(0)
|
|
%r29:(0)
|
|
%r30:(0)
|
|
%r31:(0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:416: ** warp #1 active threads changed from 4 to 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000728
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1251
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 0 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1252
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1253
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1254
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 1 1 1 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1255
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 1 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000728
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x5006b into: gpgpu
|
|
DEBUG ../../../../simX/instruction.cpp:982: TMC: r10
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000003 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:416: ** warp #0 active threads changed from 4 to 1
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000728
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1256
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1257
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1258
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1259
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1260
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1261
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x8000072c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000044
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000003 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=8000072c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1262
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1263
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1264
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1265
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1266
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1267
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000044
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2110006f into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r0 <- imm=2576
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000a54
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6ffff000 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000003 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000044
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1268
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1269
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1270
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1271
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1272
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1273
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a54
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xff010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967280
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000003 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a54
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1274
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a58
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x593 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r11 <- r0, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a58
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=11, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1275
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a5c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x812423 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r8 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffeff8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a5c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=8
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1276
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a60
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x112623 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffeffc
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a60
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1277
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a64
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x50413 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r8 <- r10, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000044 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a64
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1278
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a68
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x7d9020ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=12248
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80003a40
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a68
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1279
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1280
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1281
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1282
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1283
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1284
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a40
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfd010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967248
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a40
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1285
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a40
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1286
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a40
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1287
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a40
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1288
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a44
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1412c23 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r20 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffefd8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a44
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=20
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1289
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a48
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1c01aa03 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r3, imm=448
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016d68
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 800163b0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a48
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1290
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a4c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x3212023 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r18 <- r2, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffefe0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a4c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=18
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1291
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a4c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=18
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1292
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a50
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2112623 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=44
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffefec
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a50
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1293
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a54
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x148a2903 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r20, imm=328
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 800164f8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 800164fc
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a54
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=20, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1294
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a58
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2812423 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r8 <- r2, imm=40
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffefe8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a58
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=8
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1295
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a5c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2912223 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r9 <- r2, imm=36
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffefe4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a5c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=9
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1296
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a60
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1312e23 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r19 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffefdc
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a60
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=19
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1297
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a64
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1512a23 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r21 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffefd4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a64
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=21
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1298
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a68
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1612823 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r22 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffefd0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a68
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=22
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1299
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a6c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1712623 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r23 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffefcc
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a6c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=23
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1300
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a70
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1812423 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r24 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffefc8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a70
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=24
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1301
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a74
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x4090063 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r18, r0, imm=64
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a74
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=18, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1302
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1303
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1304
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1305
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1306
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1307
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a78
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x50b13 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r22 <- r10, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a78
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=22, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1308
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a7c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x58b93 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r23 <- r11, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a7c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=23, rs1=11, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1309
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a80
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x100a93 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r21 <- r0, imm=1
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a80
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=21, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1310
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a80
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=21, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1311
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a80
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=21, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1312
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a80
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=21, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1313
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a84
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfff00993 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r19 <- r0, imm=4294967295
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a84
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1314
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a88
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x492483 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r18, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016500
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 1
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000001 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a88
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=18, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1315
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a8c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfff48413 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r8 <- r9, imm=4294967295
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000001 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a8c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=9, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1316
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a90
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2044263 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:712: BLT: r8, r0, imm=36
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000001 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a90
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=8, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1317
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1318
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1319
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1320
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1321
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1322
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1323
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1324
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a94
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x249493 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:626: SLLI: r9 <- r9, imm=0x2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000004 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a94
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=9, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1325
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a98
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x9904b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:486: ADDI: r9 <- r18, r9
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a98
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=18, trs2=9
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1326
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003a9c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x40b8463 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r23, r0, imm=72
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80003ae4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 10000010 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003a9c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=23, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1327
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1328
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1329
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1330
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1331
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1332
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1333
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003ae4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x492783 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r15 <- r18, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016500
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 1
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 10000010 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 00000001 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003ae4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=18, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1334
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003ae4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=18, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1335
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003ae4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=18, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1336
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003ae4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=18, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1337
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003ae8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x44a683 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r13 <- r9, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016504
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80000a84
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 00000001 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003ae8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=13, rs1=9, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1338
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003aec
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfff78793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=4294967295
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003aec
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1339
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003af0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x4878e63 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r15, r8, imm=92
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80003b4c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003af0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=15, trs2=8
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1340
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1341
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1342
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1343
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1344
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1345
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1346
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003b4c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x892223 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r8 <- r18, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 80016500
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003b4c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=18, trs2=8
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1347
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003b4c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=18, trs2=8
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1348
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003b4c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=18, trs2=8
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1349
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003b4c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=18, trs2=8
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1350
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003b50
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfa9ff06f into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r0 <- imm=-88
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80003af8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003b50
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1351
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1352
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1353
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1354
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1355
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1356
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003af8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfa0688e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r13, r0, imm=-80
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003af8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=13, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1357
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1358
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1359
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1360
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1361
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1362
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003afc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x18892783 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r15 <- r18, imm=392
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016684
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000009 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003afc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=18, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1363
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003b00
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8a9733 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:492: SLLI: r14 <- r21, r8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003b00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=21, trs2=8
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1364
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003b00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=21, trs2=8
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1365
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003b00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=21, trs2=8
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1366
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003b00
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=21, trs2=8
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1367
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003b04
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x492c03 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r24 <- r18, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016500
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003b04
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=24, rs1=18, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1368
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003b08
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf777b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:532: ANDI: r15 <- r14, r15
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003b08
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=14, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1369
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003b0c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2079263 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r15, r0, imm=36
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003b0c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=15, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1370
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1371
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1372
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1373
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1374
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1375
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1376
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003b10
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x680e7 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r1 <- r13, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000a84
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003b10
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=13, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1377
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1378
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1379
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1380
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1381
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1382
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a84
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xff010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=4294967280
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefb0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a84
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1383
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a84
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1384
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a84
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1385
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a84
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1386
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a88
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x812423 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r8 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffefb8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefb0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a88
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=8
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1387
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a8c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x800167b7 into: lui
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r15 <- imm=0xfff80016
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefb0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 80016000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a8c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1388
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a90
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x80016437 into: lui
|
|
DEBUG ../../../../simX/instruction.cpp:749: LUI: r8 <- imm=0xfff80016
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefb0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 80016000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 80016000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a90
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1389
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a90
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1390
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a94
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x3a440413 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r8 <- r8, imm=932
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefb0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 800163a4 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 80016000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a94
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=8, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1391
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a98
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x3a478793 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r15 <- r15, imm=932
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefb0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 800163a4 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 800163a4 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a98
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1392
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a9c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x408787b3 into: r_type
|
|
DEBUG ../../../../simX/instruction.cpp:482: SUBI: r15 <- r15, r8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefb0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 800163a4 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a9c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=8
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1393
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a9c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=15, trs2=8
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1394
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000aa0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x912223 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r9 <- r2, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffefb4
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefb0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 800163a4 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000aa0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=9
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1395
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000aa4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x112623 into: store
|
|
DEBUG ../../../../simX/instruction.cpp:676: SD: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:683: STORE MEM ADDRESS: 6fffefbc
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefb0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 800163a4 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000aa4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1396
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000aa4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=2, trs2=1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=1
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1397
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000aa8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x4027d493 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:640: SRAI: r9 <- r15, imm=2
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefb0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 800163a4 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000aa8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=15, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1398
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000aac
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2048063 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r9, r0, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000acc
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefb0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 800163a4 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000aac
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=9, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1399
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1400
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1401
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1402
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1403
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1404
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1405
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000acc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xc12083 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffefbc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80003b14
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefb0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 800163a4 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000acc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1406
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000acc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1407
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000acc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1408
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000acc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1409
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000ad0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x812403 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffefb8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefb0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ad0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1410
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000ad4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x412483 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffefb4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80016500
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefb0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ad4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1411
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000ad8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=16
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000ad8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1412
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000adc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80003b14
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000001 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000adc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1413
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1414
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1415
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1416
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1417
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1418
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003b14
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x492703 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r14 <- r18, imm=4
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016500
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003b14
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=14, rs1=18, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1419
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003b18
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x148a2783 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r15 <- r20, imm=328
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 800164f8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 800164fc
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003b18
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=20, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1420
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003b1c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1871463 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r14, r24, imm=8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003b1c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=14, trs2=24
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1421
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1422
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1423
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1424
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1425
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1426
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003b20
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xf8f904e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r18, r15, imm=-120
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80003aa8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000000 (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003b20
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=18, trs2=15
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1427
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1428
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1429
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1430
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1431
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1432
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003aa8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xfff40413 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r8 <- r8, imm=4294967295
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: ffffffff (0)
|
|
%r 9: 80016500 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003aa8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=8, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1433
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003aa8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=8, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1434
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003aa8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=8, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1435
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003aa8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=8, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1436
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003aac
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xffc48493 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r9 <- r9, imm=4294967292
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: ffffffff (0)
|
|
%r 9: 800164fc (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003aac
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=9, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1437
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003ab0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xff3416e3 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:703: BNE: r8, r19, imm=-20
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80003b14 (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: ffffffff (0)
|
|
%r 9: 800164fc (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003ab0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=8, trs2=19
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1438
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1439
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1440
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1441
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1442
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1443
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003ab4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2c12083 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r1 <- r2, imm=44
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffefec
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 80000a6c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: ffffffff (0)
|
|
%r 9: 800164fc (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003ab4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1444
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003ab8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2812403 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r8 <- r2, imm=40
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffefe8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 1
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 800164fc (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003ab8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=8, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1445
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003abc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2412483 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r9 <- r2, imm=36
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffefe4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 800164fc (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003abc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=9, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1446
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003ac0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x2012903 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r18 <- r2, imm=32
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffefe0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: ffffffff (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003ac0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1447
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003ac0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1448
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003ac0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1449
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003ac0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=18, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1450
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003ac4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1c12983 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r19 <- r2, imm=28
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffefdc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 800163b0 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003ac4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=19, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1451
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003ac8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1812a03 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r20 <- r2, imm=24
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffefd8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000001 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003ac8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=20, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1452
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003acc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1412a83 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r21 <- r2, imm=20
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffefd4
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000001 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003acc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=21, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1453
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003ad0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1012b03 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r22 <- r2, imm=16
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffefd0
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003ad0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=22, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1454
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003ad4
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xc12b83 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r23 <- r2, imm=12
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffefcc
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003ad4
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=23, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1455
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003ad8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x812c03 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r24 <- r2, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 6fffefc8
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffefc0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003ad8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=24, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1456
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003adc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x3010113 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r2 <- r2, imm=48
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003adc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=2, rs1=2, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1457
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80003ae0
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x8067 into: jalr
|
|
DEBUG ../../../../simX/instruction.cpp:769: JALR: r0 <- r1, imm=0
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000a6c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80003ae0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1458
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1459
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1460
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1461
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1462
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1463
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a6c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x1c01a503 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r10 <- r3, imm=448
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 80016d68
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 800163b0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 800163b0 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 800164fc (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a6c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1464
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a6c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1465
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a6c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1466
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a6c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=3, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1467
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a70
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x3c52783 into: load
|
|
DEBUG ../../../../simX/instruction.cpp:560: LDI: r15 <- r10, imm=60
|
|
DEBUG ../../../../simX/instruction.cpp:578: LOAD MEM ADDRESS: 800163ec
|
|
DEBUG ../../../../simX/instruction.cpp:579: LOAD MEM DATA: 0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 800163b0 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a70
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=15, rs1=10, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=1
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1468
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a74
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x78463 into: branch
|
|
DEBUG ../../../../simX/instruction.cpp:694: BEQ: r15, r0, imm=8
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000a7c
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 800163b0 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a74
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=15, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1469
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1470
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1471
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1472
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1473
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1474
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:593: Execute: srcs not ready!
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1475
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1476
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1477
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1478
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a7c
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x40513 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r8, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a6c (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a7c
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=8, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1479
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000a80
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0xb59ff0ef into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r1 <- imm=-1192
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 800005d8
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a84 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000001 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a80
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1480
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a80
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1481
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a80
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1482
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000a80
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1483
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1484
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1485
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1486
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1487
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1488
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800005d8
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x513 into: i_type
|
|
DEBUG ../../../../simX/instruction.cpp:586: ADDI: r10 <- r0, imm=0
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a84 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800005d8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=3
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1489
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800005d8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=2
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1490
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800005d8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=1
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1491
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800005d8
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=10, rs1=0, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1492
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x800005dc
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x14c0006f into: jal
|
|
DEBUG ../../../../simX/instruction.cpp:757: JAL: r0 <- imm=332
|
|
DEBUG ../../../../simX/instruction.cpp:2278: Next PC: 80000728
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0: 00000000 (0)
|
|
%r 1: 80000a84 (0)
|
|
%r 2: 6fffeff0 (0)
|
|
%r 3: 80016ba8 (0)
|
|
%r 4: 00000000 (0)
|
|
%r 5: 80000bc8 (0)
|
|
%r 6: 0000000f (0)
|
|
%r 7: 00000000 (0)
|
|
%r 8: 00000001 (0)
|
|
%r 9: 00000000 (0)
|
|
%r10: 00000000 (0)
|
|
%r11: 00000000 (0)
|
|
%r12: 1000040c (0)
|
|
%r13: 80000a84 (0)
|
|
%r14: 00000000 (0)
|
|
%r15: 00000000 (0)
|
|
%r16: 00000000 (0)
|
|
%r17: 00000000 (0)
|
|
%r18: 00000000 (0)
|
|
%r19: 00000000 (0)
|
|
%r20: 00000000 (0)
|
|
%r21: 00000000 (0)
|
|
%r22: 00000000 (0)
|
|
%r23: 00000000 (0)
|
|
%r24: 00000000 (0)
|
|
%r25: 00000000 (0)
|
|
%r26: 00000000 (0)
|
|
%r27: 00000000 (0)
|
|
%r28: 00000000 (0)
|
|
%r29: 00000000 (0)
|
|
%r30: 00000000 (0)
|
|
%r31: 00000000 (0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=800005dc
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1493
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1494
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1495
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1496
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1497
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 1 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1498
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:750: current PC=0x80000728
|
|
DEBUG ../../../../simX/enc.cpp:324: Decoded instr 0x5006b into: gpgpu
|
|
DEBUG ../../../../simX/instruction.cpp:982: TMC: r10
|
|
DEBUG ../../../../simX/core.cpp:781: Register state:
|
|
%r 0:(0)
|
|
%r 1:(0)
|
|
%r 2:(0)
|
|
%r 3:(0)
|
|
%r 4:(0)
|
|
%r 5:(0)
|
|
%r 6:(0)
|
|
%r 7:(0)
|
|
%r 8:(0)
|
|
%r 9:(0)
|
|
%r10:(0)
|
|
%r11:(0)
|
|
%r12:(0)
|
|
%r13:(0)
|
|
%r14:(0)
|
|
%r15:(0)
|
|
%r16:(0)
|
|
%r17:(0)
|
|
%r18:(0)
|
|
%r19:(0)
|
|
%r20:(0)
|
|
%r21:(0)
|
|
%r22:(0)
|
|
%r23:(0)
|
|
%r24:(0)
|
|
%r25:(0)
|
|
%r26:(0)
|
|
%r27:(0)
|
|
%r28:(0)
|
|
%r29:(0)
|
|
%r30:(0)
|
|
%r31:(0)
|
|
DEBUG ../../../../simX/core.cpp:790: Thread mask: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:416: ** warp #0 active threads changed from 1 to 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=1
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=80000728
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=0, rs1=10, trs2=0
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=1
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1499
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1500
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=2
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1501
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=3
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
|
|
DEBUG ../../../../simX/core.cpp:174: cycle: 1502
|
|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=0
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
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DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
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DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
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|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
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|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
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|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
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|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
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|
DEBUG ../../../../simX/core.cpp:170: ###########################################################
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|
DEBUG ../../../../simX/core.cpp:174: cycle: 1503
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|
DEBUG ../../../../simX/core.cpp:176: stalled warps: 1 0 0 0
|
|
DEBUG ../../../../simX/core.cpp:83: Fetch: valid=0
|
|
DEBUG ../../../../simX/core.cpp:84: Fetch: PC=0
|
|
DEBUG ../../../../simX/core.cpp:85: Fetch: wid=1
|
|
DEBUG ../../../../simX/core.cpp:86: Fetch: rd=-1, rs1=-1, trs2=-1
|
|
DEBUG ../../../../simX/core.cpp:87: Fetch: is_lw=0
|
|
DEBUG ../../../../simX/core.cpp:88: Fetch: is_sw=0
|
|
DEBUG ../../../../simX/core.cpp:89: Fetch: fetch_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:90: Fetch: mem_stall_cycles=0
|
|
DEBUG ../../../../simX/core.cpp:91: Fetch: stall_warp=0
|
|
DEBUG ../../../../simX/core.cpp:92: Fetch: wspawn=0
|
|
DEBUG ../../../../simX/core.cpp:93: Fetch: stalled=0
|
|
DEBUG ../../../../simX/core.cpp:437: active threads: 0 0 0 0 0 0 0 0
|
|
Device ready...
|
|
download destination buffer
|
|
verify result
|
|
cleanup
|
|
Device shutdown...
|
|
FAILED!
|
|
Makefile:55: recipe for target 'run-simx' failed
|
|
make: *** [run-simx] Error 64
|