d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
652 lines
13 KiB
Systemverilog
652 lines
13 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`ifndef VX_CONFIG_VH
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`define VX_CONFIG_VH
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`ifndef MIN
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`define MIN(x, y) (((x) < (y)) ? (x) : (y))
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`endif
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`ifndef MAX
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`define MAX(x, y) (((x) > (y)) ? (x) : (y))
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`endif
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`ifndef CLAMP
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`define CLAMP(x, lo, hi) (((x) > (hi)) ? (hi) : (((x) < (lo)) ? (lo) : (x)))
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`endif
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`ifndef UP
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`define UP(x) (((x) != 0) ? (x) : 1)
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`endif
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///////////////////////////////////////////////////////////////////////////////
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// 32 bit XLEN as default.
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`ifndef XLEN_32
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`ifndef XLEN_64
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`define XLEN_32
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`endif
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`endif
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`ifdef XLEN_64
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`define XLEN 64
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`endif
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`ifdef XLEN_32
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`define XLEN 32
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`endif
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`ifndef NUM_CLUSTERS
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`define NUM_CLUSTERS 1
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`endif
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`ifndef NUM_CORES
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`define NUM_CORES 1
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`endif
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`ifndef NUM_WARPS
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`define NUM_WARPS 4
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`endif
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`ifndef NUM_THREADS
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`define NUM_THREADS 4
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`endif
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`ifndef NUM_BARRIERS
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`define NUM_BARRIERS 4
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`endif
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`ifndef SOCKET_SIZE
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`define SOCKET_SIZE `MIN(4, `NUM_CORES)
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`endif
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`ifdef L2_ENABLE
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`define L2_ENABLED 1
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`else
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`define L2_ENABLED 0
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`endif
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`ifdef L3_ENABLE
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`define L3_ENABLED 1
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`else
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`define L3_ENABLED 0
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`endif
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`ifdef L1_DISABLE
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`define ICACHE_DISABLE
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`define DCACHE_DISABLE
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`endif
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`ifndef MEM_BLOCK_SIZE
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`define MEM_BLOCK_SIZE 64
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`endif
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`ifndef MEM_ADDR_WIDTH
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`ifdef XLEN_64
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`define MEM_ADDR_WIDTH 48
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`else
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`define MEM_ADDR_WIDTH 32
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`endif
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`endif
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`ifndef L1_LINE_SIZE
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`ifdef L1_DISABLE
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`define L1_LINE_SIZE ((`L2_ENABLED || `L3_ENABLED) ? 4 : `MEM_BLOCK_SIZE)
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`else
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`define L1_LINE_SIZE ((`L2_ENABLED || `L3_ENABLED) ? 16 : `MEM_BLOCK_SIZE)
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`endif
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`endif
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`ifdef XLEN_64
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`ifndef STARTUP_ADDR
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`define STARTUP_ADDR 64'h180000000
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`endif
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`ifndef STACK_BASE_ADDR
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`define STACK_BASE_ADDR 64'h1FF000000
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`endif
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`else
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`ifndef STARTUP_ADDR
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`define STARTUP_ADDR 32'h80000000
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`endif
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`ifndef STACK_BASE_ADDR
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`define STACK_BASE_ADDR 32'hFF000000
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`endif
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`endif
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`ifndef SMEM_BASE_ADDR
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`define SMEM_BASE_ADDR `STACK_BASE_ADDR
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`endif
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`ifndef SMEM_LOG_SIZE
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`define SMEM_LOG_SIZE 14
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`endif
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`ifndef IO_BASE_ADDR
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`define IO_BASE_ADDR (`SMEM_BASE_ADDR + (1 << `SMEM_LOG_SIZE))
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`endif
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`ifndef IO_COUT_ADDR
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`define IO_COUT_ADDR `IO_BASE_ADDR
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`endif
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`define IO_COUT_SIZE `MEM_BLOCK_SIZE
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`ifndef IO_CSR_ADDR
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`define IO_CSR_ADDR (`IO_COUT_ADDR + `IO_COUT_SIZE)
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`endif
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`define IO_CSR_SIZE (4 * 64 * `NUM_CORES * `NUM_CLUSTERS)
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`ifndef STACK_LOG2_SIZE
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`define STACK_LOG2_SIZE 13
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`endif
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`define STACK_SIZE (1 << `STACK_LOG2_SIZE)
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`define RESET_DELAY 8
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`ifndef STALL_TIMEOUT
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`define STALL_TIMEOUT (100000 * (1 ** (`L2_ENABLED + `L3_ENABLED)))
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`endif
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`ifndef FPU_FPNEW
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`ifndef FPU_DSP
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`ifndef FPU_DPI
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`ifdef SYNTHESIS
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`define FPU_DSP
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`else
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`define FPU_DPI
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`endif
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`endif
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`endif
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`endif
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`ifndef SYNTHESIS
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`ifndef DPI_DISABLE
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`define IMUL_DPI
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`define IDIV_DPI
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`endif
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`endif
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`ifndef DEBUG_LEVEL
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`define DEBUG_LEVEL 3
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`endif
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// ISA Extensions /////////////////////////////////////////////////////////////
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`ifndef EXT_M_DISABLE
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`define EXT_M_ENABLE
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`endif
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`ifndef EXT_F_DISABLE
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`define EXT_F_ENABLE
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`endif
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`ifdef EXT_D_ENABLE
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`define FLEN_64
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`else
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`define FLEN_32
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`endif
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`ifdef FLEN_64
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`define FLEN 64
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`endif
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`ifdef FLEN_32
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`define FLEN 32
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`endif
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`ifdef XLEN_64
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`ifdef FLEN_32
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`define FPU_RV64F
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`endif
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`endif
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`define ISA_STD_A 0
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`define ISA_STD_C 2
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`define ISA_STD_D 3
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`define ISA_STD_E 4
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`define ISA_STD_F 5
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`define ISA_STD_H 7
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`define ISA_STD_I 8
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`define ISA_STD_N 13
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`define ISA_STD_Q 16
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`define ISA_STD_S 18
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`define ISA_STD_U 20
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`define ISA_EXT_TEX 0
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`define ISA_EXT_RASTER 1
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`define ISA_EXT_ROP 2
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`ifdef EXT_A_ENABLE
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`define EXT_A_ENABLED 1
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`else
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`define EXT_A_ENABLED 0
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`endif
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`ifdef EXT_C_ENABLE
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`define EXT_C_ENABLED 1
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`else
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`define EXT_C_ENABLED 0
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`endif
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`ifdef EXT_D_ENABLE
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`define EXT_D_ENABLED 1
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`else
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`define EXT_D_ENABLED 0
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`endif
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`ifdef EXT_F_ENABLE
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`define EXT_F_ENABLED 1
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`else
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`define EXT_F_ENABLED 0
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`endif
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`ifdef EXT_M_ENABLE
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`define EXT_M_ENABLED 1
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`else
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`define EXT_M_ENABLED 0
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`endif
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`define ISA_X_ENABLED 0
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`define MISA_EXT 0
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`define MISA_STD (`EXT_A_ENABLED << 0) /* A - Atomic Instructions extension */ \
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| (0 << 1) /* B - Tentatively reserved for Bit operations extension */ \
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| (`EXT_C_ENABLED << 2) /* C - Compressed extension */ \
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| (`EXT_D_ENABLED << 3) /* D - Double precsision floating-point extension */ \
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| (0 << 4) /* E - RV32E base ISA */ \
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| (`EXT_F_ENABLED << 5) /* F - Single precsision floating-point extension */ \
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| (0 << 6) /* G - Additional standard extensions present */ \
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| (0 << 7) /* H - Hypervisor mode implemented */ \
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| (1 << 8) /* I - RV32I/64I/128I base ISA */ \
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| (0 << 9) /* J - Reserved */ \
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| (0 << 10) /* K - Reserved */ \
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| (0 << 11) /* L - Tentatively reserved for Bit operations extension */ \
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| (`EXT_M_ENABLED << 12) /* M - Integer Multiply/Divide extension */ \
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| (0 << 13) /* N - User level interrupts supported */ \
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| (0 << 14) /* O - Reserved */ \
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| (0 << 15) /* P - Tentatively reserved for Packed-SIMD extension */ \
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| (0 << 16) /* Q - Quad-precision floating-point extension */ \
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| (0 << 17) /* R - Reserved */ \
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| (0 << 18) /* S - Supervisor mode implemented */ \
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| (0 << 19) /* T - Tentatively reserved for Transactional Memory extension */ \
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| (1 << 20) /* U - User mode implemented */ \
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| (0 << 21) /* V - Tentatively reserved for Vector extension */ \
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| (0 << 22) /* W - Reserved */ \
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| (`ISA_X_ENABLED << 23) /* X - Non-standard extensions present */ \
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| (0 << 24) /* Y - Reserved */ \
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| (0 << 25) /* Z - Reserved */
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// Device identification //////////////////////////////////////////////////////
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`define VENDOR_ID 0
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`define ARCHITECTURE_ID 0
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`define IMPLEMENTATION_ID 0
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// Pipeline Configuration /////////////////////////////////////////////////////
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// Issue width
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`ifndef ISSUE_WIDTH
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`define ISSUE_WIDTH `MIN(`NUM_WARPS, 4)
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`endif
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// Number of ALU units
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`ifndef NUM_ALU_LANES
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`define NUM_ALU_LANES `UP(`NUM_THREADS / 2)
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`endif
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`ifndef NUM_ALU_BLOCKS
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`define NUM_ALU_BLOCKS `UP(`ISSUE_WIDTH / 1)
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`endif
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// Number of FPU units
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`ifndef NUM_FPU_LANES
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`define NUM_FPU_LANES `UP(`NUM_THREADS / 2)
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`endif
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`ifndef NUM_FPU_BLOCKS
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`define NUM_FPU_BLOCKS `UP(`ISSUE_WIDTH / 1)
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`endif
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// Number of LSU units
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`ifndef NUM_LSU_LANES
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`define NUM_LSU_LANES `MIN(`NUM_THREADS, 4)
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`endif
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// Number of SFU units
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`ifndef NUM_SFU_LANES
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`define NUM_SFU_LANES `MIN(`NUM_THREADS, 4)
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`endif
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// Size of Instruction Buffer
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`ifndef IBUF_SIZE
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`define IBUF_SIZE (2 * (`NUM_WARPS / `ISSUE_WIDTH))
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`endif
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// Size of LSU Request Queue
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`ifndef LSUQ_SIZE
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`define LSUQ_SIZE (2 * (`NUM_THREADS / `NUM_LSU_LANES))
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`endif
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// LSU Duplicate Address Check
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`ifdef LSU_DUP
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`define LSU_DUP_ENABLED 1
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`else
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`define LSU_DUP_ENABLED 0
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`endif
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`ifdef GBAR_ENABLE
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`define GBAR_ENABLED 1
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`else
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`define GBAR_ENABLED 0
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`endif
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`ifndef LATENCY_IMUL
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`ifdef VIVADO
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`define LATENCY_IMUL 4
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`endif
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`ifdef QUARTUS
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`define LATENCY_IMUL 3
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`endif
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`ifndef LATENCY_IMUL
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`define LATENCY_IMUL 4
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`endif
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`endif
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// Floating-Point Units ///////////////////////////////////////////////////////
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// Size of FPU Request Queue
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`ifndef FPU_REQ_QUEUE_SIZE
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`define FPU_REQ_QUEUE_SIZE (2 * (`NUM_THREADS / `NUM_FPU_LANES))
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`endif
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// FNCP Latency
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`ifndef LATENCY_FNCP
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`define LATENCY_FNCP 2
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`endif
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// FMA Latency
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`ifndef LATENCY_FMA
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`ifdef FPU_DPI
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`define LATENCY_FMA 4
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`endif
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`ifdef FPU_FPNEW
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`define LATENCY_FMA 4
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`endif
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`ifdef FPU_DSP
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`ifdef QUARTUS
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`define LATENCY_FMA 4
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`endif
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`ifdef VIVADO
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`define LATENCY_FMA 16
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`endif
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`ifndef LATENCY_FMA
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`define LATENCY_FMA 4
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`endif
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`endif
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`endif
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// FDIV Latency
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`ifndef LATENCY_FDIV
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`ifdef FPU_DPI
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`define LATENCY_FDIV 15
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`endif
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`ifdef FPU_FPNEW
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`define LATENCY_FDIV 16
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`endif
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`ifdef FPU_DSP
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`ifdef QUARTUS
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`define LATENCY_FDIV 15
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`endif
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`ifdef VIVADO
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`define LATENCY_FDIV 28
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`endif
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`ifndef LATENCY_FDIV
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`define LATENCY_FDIV 16
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`endif
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`endif
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`endif
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// FSQRT Latency
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`ifndef LATENCY_FSQRT
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`ifdef FPU_DPI
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`define LATENCY_FSQRT 10
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`endif
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`ifdef FPU_FPNEW
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`define LATENCY_FSQRT 16
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`endif
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`ifdef FPU_DSP
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`ifdef QUARTUS
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`define LATENCY_FSQRT 10
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`endif
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`ifdef VIVADO
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`define LATENCY_FSQRT 28
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`endif
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`ifndef LATENCY_FSQRT
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`define LATENCY_FSQRT 16
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`endif
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`endif
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`endif
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// FCVT Latency
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`ifndef LATENCY_FCVT
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`define LATENCY_FCVT 5
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`endif
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// Icache Configurable Knobs //////////////////////////////////////////////////
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// Cache Enable
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`ifndef ICACHE_DISABLE
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`define ICACHE_ENABLE
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`endif
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`ifdef ICACHE_ENABLE
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`define ICACHE_ENABLED 1
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`else
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`define ICACHE_ENABLED 0
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`define NUM_ICACHES 0
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`endif
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// Number of Cache Units
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`ifndef NUM_ICACHES
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`define NUM_ICACHES `UP(`NUM_CORES / 4)
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`endif
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// Cache Size
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`ifndef ICACHE_SIZE
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`define ICACHE_SIZE 16384
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`endif
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// Core Response Queue Size
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`ifndef ICACHE_CRSQ_SIZE
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`define ICACHE_CRSQ_SIZE 2
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`endif
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// Miss Handling Register Size
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`ifndef ICACHE_MSHR_SIZE
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`define ICACHE_MSHR_SIZE 16
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`endif
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// Memory Request Queue Size
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`ifndef ICACHE_MREQ_SIZE
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`define ICACHE_MREQ_SIZE 4
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`endif
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// Memory Response Queue Size
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`ifndef ICACHE_MRSQ_SIZE
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`define ICACHE_MRSQ_SIZE 0
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`endif
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// Number of Associative Ways
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`ifndef ICACHE_NUM_WAYS
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`define ICACHE_NUM_WAYS 2
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`endif
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// Dcache Configurable Knobs //////////////////////////////////////////////////
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// Cache Enable
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`ifndef DCACHE_DISABLE
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`define DCACHE_ENABLE
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`endif
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`ifdef DCACHE_ENABLE
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`define DCACHE_ENABLED 1
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`else
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`define DCACHE_ENABLED 0
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`define NUM_DCACHES 0
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`define DCACHE_NUM_BANKS 1
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`endif
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// Number of Cache Units
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`ifndef NUM_DCACHES
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`define NUM_DCACHES `UP(`NUM_CORES / 4)
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`endif
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// Cache Size
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`ifndef DCACHE_SIZE
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`define DCACHE_SIZE 16384
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`endif
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// Number of Banks
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`ifndef DCACHE_NUM_BANKS
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`define DCACHE_NUM_BANKS (`NUM_LSU_LANES)
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`endif
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// Core Response Queue Size
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`ifndef DCACHE_CRSQ_SIZE
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`define DCACHE_CRSQ_SIZE 2
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`endif
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// Miss Handling Register Size
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`ifndef DCACHE_MSHR_SIZE
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`define DCACHE_MSHR_SIZE 16
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`endif
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// Memory Request Queue Size
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`ifndef DCACHE_MREQ_SIZE
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`define DCACHE_MREQ_SIZE 4
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`endif
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// Memory Response Queue Size
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`ifndef DCACHE_MRSQ_SIZE
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`define DCACHE_MRSQ_SIZE 0
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`endif
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// Number of Associative Ways
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`ifndef DCACHE_NUM_WAYS
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`define DCACHE_NUM_WAYS 2
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`endif
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// SM Configurable Knobs //////////////////////////////////////////////////////
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`ifndef SM_DISABLE
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`define SM_ENABLE
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`endif
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`ifdef SM_ENABLE
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`define SM_ENABLED 1
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`else
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`define SM_ENABLED 0
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`define SMEM_NUM_BANKS 1
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`endif
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// Number of Banks
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`ifndef SMEM_NUM_BANKS
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`define SMEM_NUM_BANKS (`NUM_LSU_LANES)
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`endif
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// L2cache Configurable Knobs /////////////////////////////////////////////////
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// Cache Size
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`ifndef L2_CACHE_SIZE
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`ifdef ALTERA_S10
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`define L2_CACHE_SIZE 2097152
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`else
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`define L2_CACHE_SIZE 1048576
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`endif
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`endif
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// Number of Banks
|
|
`ifndef L2_NUM_BANKS
|
|
`define L2_NUM_BANKS 2
|
|
`endif
|
|
|
|
// Core Response Queue Size
|
|
`ifndef L2_CRSQ_SIZE
|
|
`define L2_CRSQ_SIZE 2
|
|
`endif
|
|
|
|
// Miss Handling Register Size
|
|
`ifndef L2_MSHR_SIZE
|
|
`define L2_MSHR_SIZE 16
|
|
`endif
|
|
|
|
// Memory Request Queue Size
|
|
`ifndef L2_MREQ_SIZE
|
|
`define L2_MREQ_SIZE 4
|
|
`endif
|
|
|
|
// Memory Response Queue Size
|
|
`ifndef L2_MRSQ_SIZE
|
|
`define L2_MRSQ_SIZE 0
|
|
`endif
|
|
|
|
// Number of Associative Ways
|
|
`ifndef L2_NUM_WAYS
|
|
`define L2_NUM_WAYS 4
|
|
`endif
|
|
|
|
// L3cache Configurable Knobs /////////////////////////////////////////////////
|
|
|
|
// Cache Size
|
|
`ifndef L3_CACHE_SIZE
|
|
`ifdef ALTERA_S10
|
|
`define L3_CACHE_SIZE 2097152
|
|
`else
|
|
`define L3_CACHE_SIZE 1048576
|
|
`endif
|
|
`endif
|
|
|
|
// Number of Banks
|
|
`ifndef L3_NUM_BANKS
|
|
`define L3_NUM_BANKS `MIN(4, `NUM_CLUSTERS)
|
|
`endif
|
|
|
|
// Core Response Queue Size
|
|
`ifndef L3_CRSQ_SIZE
|
|
`define L3_CRSQ_SIZE 2
|
|
`endif
|
|
|
|
// Miss Handling Register Size
|
|
`ifndef L3_MSHR_SIZE
|
|
`define L3_MSHR_SIZE 16
|
|
`endif
|
|
|
|
// Memory Request Queue Size
|
|
`ifndef L3_MREQ_SIZE
|
|
`define L3_MREQ_SIZE 4
|
|
`endif
|
|
|
|
// Memory Response Queue Size
|
|
`ifndef L3_MRSQ_SIZE
|
|
`define L3_MRSQ_SIZE 0
|
|
`endif
|
|
|
|
// Number of Associative Ways
|
|
`ifndef L3_NUM_WAYS
|
|
`define L3_NUM_WAYS 4
|
|
`endif
|
|
|
|
`endif // VX_CONFIG_VH
|