d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
118 lines
3.5 KiB
Systemverilog
118 lines
3.5 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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// Fast encoder using parallel prefix computation
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// Adapted from BaseJump STL: http://bjump.org/data_out.html
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`TRACING_OFF
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module VX_onehot_encoder #(
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parameter N = 1,
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parameter REVERSE = 0,
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parameter MODEL = 1,
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parameter LN = `LOG2UP(N)
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) (
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input wire [N-1:0] data_in,
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output wire [LN-1:0] data_out,
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output wire valid_out
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);
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if (N == 1) begin
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assign data_out = data_in;
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assign valid_out = data_in;
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end else if (N == 2) begin
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assign data_out = data_in[!REVERSE];
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assign valid_out = (| data_in);
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end else if (MODEL == 1) begin
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localparam M = 1 << LN;
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`IGNORE_UNOPTFLAT_BEGIN
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wire [LN-1:0][M-1:0] addr;
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wire [LN:0][M-1:0] v;
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`IGNORE_UNOPTFLAT_END
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// base case, also handle padding for non-power of two inputs
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assign v[0] = REVERSE ? (M'(data_in) << (M - N)) : M'(data_in);
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for (genvar lvl = 1; lvl < (LN+1); ++lvl) begin
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localparam SN = 1 << (LN - lvl);
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localparam SI = M / SN;
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localparam SW = lvl;
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for (genvar s = 0; s < SN; ++s) begin
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`IGNORE_UNOPTFLAT_BEGIN
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wire [1:0] vs = {v[lvl-1][s*SI+(SI>>1)], v[lvl-1][s*SI]};
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`IGNORE_UNOPTFLAT_END
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assign v[lvl][s*SI] = (| vs);
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if (lvl == 1) begin
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assign addr[lvl-1][s*SI +: SW] = vs[!REVERSE];
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end else begin
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assign addr[lvl-1][s*SI +: SW] = {
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vs[!REVERSE],
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addr[lvl-2][s*SI +: SW-1] | addr[lvl-2][s*SI+(SI>>1) +: SW-1]
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};
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end
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end
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end
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assign data_out = addr[LN-1][LN-1:0];
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assign valid_out = v[LN][0];
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end else if (MODEL == 2 && REVERSE == 0) begin
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for (genvar j = 0; j < LN; ++j) begin
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wire [N-1:0] mask;
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for (genvar i = 0; i < N; ++i) begin
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assign mask[i] = i[j];
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end
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assign data_out[j] = | (mask & data_in);
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end
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assign valid_out = (| data_in);
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end else begin
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reg [LN-1:0] index_r;
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if (REVERSE != 0) begin
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always @(*) begin
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index_r = 'x;
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for (integer i = N-1; i >= 0; --i) begin
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if (data_in[i]) begin
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index_r = LN'(N-1-i);
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end
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end
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end
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end else begin
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always @(*) begin
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index_r = 'x;
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for (integer i = 0; i < N; ++i) begin
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if (data_in[i]) begin
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index_r = LN'(i);
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end
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end
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end
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end
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assign data_out = index_r;
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assign valid_out = (| data_in);
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end
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endmodule
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`TRACING_ON
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