131 lines
4.7 KiB
Verilog
131 lines
4.7 KiB
Verilog
`include "VX_define.vh"
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module VX_avs_wrapper #(
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parameter AVS_DATAW = 1,
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parameter AVS_ADDRW = 1,
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parameter AVS_BURSTW = 1,
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parameter AVS_BANKS = 1,
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parameter REQ_TAGW = 1,
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parameter RD_QUEUE_SIZE = 1,
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parameter AVS_BYTEENW = (AVS_DATAW / 8),
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parameter RD_QUEUE_ADDRW= $clog2(RD_QUEUE_SIZE+1),
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parameter AVS_BANKS_BITS= $clog2(AVS_BANKS)
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) (
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input wire clk,
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input wire reset,
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// AVS bus
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output wire [AVS_DATAW-1:0] avs_writedata,
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input wire [AVS_DATAW-1:0] avs_readdata,
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output wire [AVS_ADDRW-1:0] avs_address,
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input wire avs_waitrequest,
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output wire avs_write,
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output wire avs_read,
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output wire [AVS_BYTEENW-1:0] avs_byteenable,
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output wire [AVS_BURSTW-1:0] avs_burstcount,
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input avs_readdatavalid,
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output wire [AVS_BANKS_BITS-1:0] avs_bankselect,
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// DRAM request
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input wire dram_req_valid,
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input wire dram_req_rw,
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input wire [AVS_BYTEENW-1:0] dram_req_byteen,
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input wire [AVS_ADDRW-1:0] dram_req_addr,
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input wire [AVS_DATAW-1:0] dram_req_data,
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input wire [REQ_TAGW-1:0] dram_req_tag,
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output wire dram_req_ready,
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// DRAM response
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output wire dram_rsp_valid,
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output wire [AVS_DATAW-1:0] dram_rsp_data,
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output wire [REQ_TAGW-1:0] dram_rsp_tag,
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input wire dram_rsp_ready
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);
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reg [AVS_BANKS_BITS-1:0] avs_bankselect_r;
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reg [AVS_BURSTW-1:0] avs_burstcount_r;
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wire avs_reqq_push = dram_req_valid && dram_req_ready && !dram_req_rw;
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wire avs_reqq_pop = dram_rsp_valid && dram_rsp_ready;
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wire avs_rspq_push = avs_readdatavalid;
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wire avs_rspq_pop = avs_reqq_pop;
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wire avs_rspq_empty;
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reg [RD_QUEUE_ADDRW-1:0] avs_pending_reads;
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wire [RD_QUEUE_ADDRW-1:0] avs_pending_reads_n;
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assign avs_pending_reads_n = avs_pending_reads
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+ RD_QUEUE_ADDRW'((avs_reqq_push && !avs_rspq_pop) ? 1 :
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(avs_rspq_pop && !avs_reqq_push) ? -1 : 0);
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always @(posedge clk) begin
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if (reset) begin
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avs_burstcount_r <= 1;
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avs_bankselect_r <= 0;
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avs_pending_reads <= 0;
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end else begin
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avs_pending_reads <= avs_pending_reads_n;
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end
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end
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VX_generic_queue #(
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.DATAW (REQ_TAGW),
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.SIZE (RD_QUEUE_SIZE),
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.BUFFERED (1)
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) rd_req_queue (
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.clk (clk),
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.reset (reset),
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.push (avs_reqq_push),
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.pop (avs_reqq_pop),
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.data_in (dram_req_tag),
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.data_out (dram_rsp_tag),
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`UNUSED_PIN (empty),
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`UNUSED_PIN (full),
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`UNUSED_PIN (size)
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);
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VX_generic_queue #(
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.DATAW (AVS_DATAW),
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.SIZE (RD_QUEUE_SIZE),
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.BUFFERED (1)
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) rd_rsp_queue (
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.clk (clk),
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.reset (reset),
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.push (avs_rspq_push),
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.pop (avs_rspq_pop),
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.data_in (avs_readdata),
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.data_out (dram_rsp_data),
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.empty (avs_rspq_empty),
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`UNUSED_PIN (full),
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`UNUSED_PIN (size)
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);
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wire rsp_queue_ready = (avs_pending_reads != RD_QUEUE_SIZE);
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assign avs_read = dram_req_valid && !dram_req_rw && rsp_queue_ready;
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assign avs_write = dram_req_valid && dram_req_rw && rsp_queue_ready;
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assign avs_address = dram_req_addr;
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assign avs_byteenable = dram_req_byteen;
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assign avs_writedata = dram_req_data;
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assign dram_req_ready = !avs_waitrequest && rsp_queue_ready;
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assign avs_burstcount = avs_burstcount_r;
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assign avs_bankselect = avs_bankselect_r;
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assign dram_rsp_valid = !avs_rspq_empty;
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`ifdef DBG_PRINT_AVS
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always @(posedge clk) begin
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if (dram_req_valid && dram_req_ready) begin
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if (dram_req_rw)
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$display("%t: AVS Wr Req: addr=%0h, byteen=%0h, tag=%0h, data=%0h", $time, `TO_FULL_ADDR(dram_req_addr), dram_req_byteen, dram_req_tag, dram_req_data);
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else
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$display("%t: AVS Rd Req: addr=%0h, byteen=%0h, tag=%0h, pending=%0d", $time, `TO_FULL_ADDR(dram_req_addr), dram_req_byteen, dram_req_tag, avs_pending_reads_n);
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end
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if (dram_rsp_valid && dram_rsp_ready) begin
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$display("%t: AVS Rd Rsp: tag=%0h, data=%0h, pending=%0d", $time, dram_rsp_tag, dram_rsp_data, avs_pending_reads_n);
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end
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end
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`endif
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endmodule |