Blaise Tine 4bbd7bf408 performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

2020-12-19 02:45:06 -08:00

..

vlsim

performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

2020-12-19 02:45:06 -08:00

Makefile

fixed register file initialization to zero synthesis inference

2020-12-10 00:27:56 -08:00

vortex_afu.h

adding support for verilator-driven AFU driver: vlsim

2020-09-08 13:05:26 -04:00

vortex.cpp

merging perf counters

2020-12-08 21:02:39 -08:00

vx_scope.cpp

cache req datapath optimizations

2020-12-08 02:58:08 -08:00

vx_scope.h

fixed register file initialization to zero synthesis inference

2020-12-10 00:27:56 -08:00