c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
380 lines
15 KiB
Systemverilog
380 lines
15 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`ifndef VX_TRACE_VH
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`define VX_TRACE_VH
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`ifndef SYNTHESIS
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`include "VX_define.vh"
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task trace_ex_type(input int level, input [`EX_BITS-1:0] ex_type);
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case (ex_type)
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`EX_ALU: `TRACE(level, ("ALU"));
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`EX_LSU: `TRACE(level, ("LSU"));
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`EX_FPU: `TRACE(level, ("FPU"));
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`EX_SFU: `TRACE(level, ("SFU"));
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default: `TRACE(level, ("?"));
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endcase
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endtask
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task trace_ex_op(input int level,
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input [`EX_BITS-1:0] ex_type,
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input [`INST_OP_BITS-1:0] op_type,
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input [`INST_MOD_BITS-1:0] op_mod,
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`UNUSED_ARG(input [`NR_BITS-1:0] rd),
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`UNUSED_ARG(input [`NR_BITS-1:0] rs2),
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input use_imm,
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`UNUSED_ARG(input [`XLEN-1:0] imm)
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);
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`ifdef FLEN_64
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logic fdst_d = imm[0];
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`else
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logic fdst_d = 0;
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`endif
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`ifdef XLEN_64
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logic fcvt_l = imm[1];
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`else
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logic fcvt_l = 0;
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`endif
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`ifdef EXT_F_ENABLE
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logic rd_float = 1'(rd >> 5) || 1'(rs2 >> 5);
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`else
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logic rd_float = 0;
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`endif
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case (ex_type)
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`EX_ALU: begin
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if (`INST_ALU_IS_BR(op_mod)) begin
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case (`INST_BR_BITS'(op_type))
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`INST_BR_EQ: `TRACE(level, ("BEQ"));
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`INST_BR_NE: `TRACE(level, ("BNE"));
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`INST_BR_LT: `TRACE(level, ("BLT"));
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`INST_BR_GE: `TRACE(level, ("BGE"));
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`INST_BR_LTU: `TRACE(level, ("BLTU"));
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`INST_BR_GEU: `TRACE(level, ("BGEU"));
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`INST_BR_JAL: `TRACE(level, ("JAL"));
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`INST_BR_JALR: `TRACE(level, ("JALR"));
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`INST_BR_ECALL: `TRACE(level, ("ECALL"));
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`INST_BR_EBREAK:`TRACE(level, ("EBREAK"));
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`INST_BR_URET: `TRACE(level, ("URET"));
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`INST_BR_SRET: `TRACE(level, ("SRET"));
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`INST_BR_MRET: `TRACE(level, ("MRET"));
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default: `TRACE(level, ("?"));
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endcase
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end else if (`INST_ALU_IS_M(op_mod)) begin
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if (`INST_ALU_IS_W(op_mod)) begin
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case (`INST_M_BITS'(op_type))
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`INST_M_MUL: `TRACE(level, ("MULW"));
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`INST_M_DIV: `TRACE(level, ("DIVW"));
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`INST_M_DIVU: `TRACE(level, ("DIVUW"));
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`INST_M_REM: `TRACE(level, ("REMW"));
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`INST_M_REMU: `TRACE(level, ("REMUW"));
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default: `TRACE(level, ("?"));
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endcase
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end else begin
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case (`INST_M_BITS'(op_type))
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`INST_M_MUL: `TRACE(level, ("MUL"));
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`INST_M_MULH: `TRACE(level, ("MULH"));
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`INST_M_MULHSU:`TRACE(level, ("MULHSU"));
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`INST_M_MULHU: `TRACE(level, ("MULHU"));
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`INST_M_DIV: `TRACE(level, ("DIV"));
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`INST_M_DIVU: `TRACE(level, ("DIVU"));
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`INST_M_REM: `TRACE(level, ("REM"));
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`INST_M_REMU: `TRACE(level, ("REMU"));
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default: `TRACE(level, ("?"));
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endcase
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end
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end else begin
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if (`INST_ALU_IS_W(op_mod)) begin
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if (use_imm) begin
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case (`INST_ALU_BITS'(op_type))
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`INST_ALU_ADD: `TRACE(level, ("ADDIW"));
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`INST_ALU_SLL: `TRACE(level, ("SLLIW"));
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`INST_ALU_SRL: `TRACE(level, ("SRLIW"));
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`INST_ALU_SRA: `TRACE(level, ("SRAIW"));
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default: `TRACE(level, ("?"));
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endcase
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end else begin
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case (`INST_ALU_BITS'(op_type))
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`INST_ALU_ADD: `TRACE(level, ("ADDW"));
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`INST_ALU_SUB: `TRACE(level, ("SUBW"));
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`INST_ALU_SLL: `TRACE(level, ("SLLW"));
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`INST_ALU_SRL: `TRACE(level, ("SRLW"));
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`INST_ALU_SRA: `TRACE(level, ("SRAW"));
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default: `TRACE(level, ("?"));
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endcase
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end
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end else begin
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if (use_imm) begin
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case (`INST_ALU_BITS'(op_type))
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`INST_ALU_ADD: `TRACE(level, ("ADDI"));
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`INST_ALU_SLL: `TRACE(level, ("SLLI"));
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`INST_ALU_SRL: `TRACE(level, ("SRLI"));
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`INST_ALU_SRA: `TRACE(level, ("SRAI"));
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`INST_ALU_SLT: `TRACE(level, ("SLTI"));
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`INST_ALU_SLTU: `TRACE(level, ("SLTIU"));
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`INST_ALU_XOR: `TRACE(level, ("XORI"));
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`INST_ALU_OR: `TRACE(level, ("ORI"));
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`INST_ALU_AND: `TRACE(level, ("ANDI"));
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`INST_ALU_LUI: `TRACE(level, ("LUI"));
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`INST_ALU_AUIPC: `TRACE(level, ("AUIPC"));
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default: `TRACE(level, ("?"));
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endcase
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end else begin
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case (`INST_ALU_BITS'(op_type))
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`INST_ALU_ADD: `TRACE(level, ("ADD"));
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`INST_ALU_SUB: `TRACE(level, ("SUB"));
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`INST_ALU_SLL: `TRACE(level, ("SLL"));
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`INST_ALU_SRL: `TRACE(level, ("SRL"));
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`INST_ALU_SRA: `TRACE(level, ("SRA"));
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`INST_ALU_SLT: `TRACE(level, ("SLT"));
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`INST_ALU_SLTU: `TRACE(level, ("SLTU"));
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`INST_ALU_XOR: `TRACE(level, ("XOR"));
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`INST_ALU_OR: `TRACE(level, ("OR"));
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`INST_ALU_AND: `TRACE(level, ("AND"));
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default: `TRACE(level, ("?"));
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endcase
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end
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end
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end
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end
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`EX_LSU: begin
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if (rd_float) begin
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case (`INST_LSU_BITS'(op_type))
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`INST_LSU_LW: `TRACE(level, ("FLW"));
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`INST_LSU_LD: `TRACE(level, ("FLD"));
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`INST_LSU_SW: `TRACE(level, ("FSW"));
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`INST_LSU_SD: `TRACE(level, ("FSD"));
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default: `TRACE(level, ("?"));
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endcase
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end else begin
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case (`INST_LSU_BITS'(op_type))
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`INST_LSU_LB: `TRACE(level, ("LB"));
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`INST_LSU_LH: `TRACE(level, ("LH"));
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`INST_LSU_LW: `TRACE(level, ("LW"));
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`INST_LSU_LD: `TRACE(level, ("LD"));
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`INST_LSU_LBU:`TRACE(level, ("LBU"));
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`INST_LSU_LHU:`TRACE(level, ("LHU"));
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`INST_LSU_LWU:`TRACE(level, ("LWU"));
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`INST_LSU_SB: `TRACE(level, ("SB"));
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`INST_LSU_SH: `TRACE(level, ("SH"));
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`INST_LSU_SW: `TRACE(level, ("SW"));
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`INST_LSU_SD: `TRACE(level, ("SD"));
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`INST_LSU_FENCE:`TRACE(level,("FENCE"));
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default: `TRACE(level, ("?"));
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endcase
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end
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end
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`EX_FPU: begin
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case (`INST_FPU_BITS'(op_type))
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`INST_FPU_ADD: begin
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if (fdst_d)
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`TRACE(level, ("FADD.D"));
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else
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`TRACE(level, ("FADD.S"));
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end
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`INST_FPU_SUB: begin
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if (fdst_d)
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`TRACE(level, ("FSUB.D"));
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else
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`TRACE(level, ("FSUB.S"));
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end
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`INST_FPU_MUL: begin
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if (fdst_d)
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`TRACE(level, ("FMUL.D"));
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else
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`TRACE(level, ("FMUL.S"));
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end
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`INST_FPU_DIV: begin
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if (fdst_d)
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`TRACE(level, ("FDIV.D"));
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else
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`TRACE(level, ("FDIV.S"));
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end
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`INST_FPU_SQRT: begin
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if (fdst_d)
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`TRACE(level, ("FSQRT.D"));
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else
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`TRACE(level, ("FSQRT.S"));
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end
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`INST_FPU_MADD: begin
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if (fdst_d)
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`TRACE(level, ("FMADD.D"));
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else
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`TRACE(level, ("FMADD.S"));
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end
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`INST_FPU_MSUB: begin
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if (fdst_d)
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`TRACE(level, ("FMSUB.D"));
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else
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`TRACE(level, ("FMSUB.S"));
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end
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`INST_FPU_NMADD: begin
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if (fdst_d)
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`TRACE(level, ("FNMADD.D"));
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else
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`TRACE(level, ("FNMADD.S"));
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end
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`INST_FPU_NMSUB: begin
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if (fdst_d)
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`TRACE(level, ("FNMSUB.D"));
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else
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`TRACE(level, ("FNMSUB.S"));
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end
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`INST_FPU_CMP: begin
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if (fdst_d) begin
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case (op_mod[1:0])
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0: `TRACE(level, ("FLE.D"));
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1: `TRACE(level, ("FLT.D"));
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2: `TRACE(level, ("FEQ.D"));
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default: `TRACE(level, ("?"));
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endcase
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end else begin
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case (op_mod[1:0])
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0: `TRACE(level, ("FLE.S"));
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1: `TRACE(level, ("FLT.S"));
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2: `TRACE(level, ("FEQ.S"));
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default: `TRACE(level, ("?"));
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endcase
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end
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end
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`INST_FPU_F2F: begin
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if (fdst_d) begin
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`TRACE(level, ("FCVT.D.S"));
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end else begin
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`TRACE(level, ("FCVT.S.D"));
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end
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end
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`INST_FPU_F2I: begin
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if (fdst_d) begin
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if (fcvt_l) begin
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`TRACE(level, ("FCVT.L.D"));
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end else begin
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`TRACE(level, ("FCVT.W.D"));
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end
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end else begin
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if (fcvt_l) begin
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`TRACE(level, ("FCVT.L.S"));
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end else begin
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`TRACE(level, ("FCVT.W.S"));
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end
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end
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end
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`INST_FPU_F2U: begin
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if (fdst_d) begin
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if (fcvt_l) begin
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`TRACE(level, ("FCVT.LU.D"));
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end else begin
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`TRACE(level, ("FCVT.WU.D"));
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end
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end else begin
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if (fcvt_l) begin
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`TRACE(level, ("FCVT.LU.S"));
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end else begin
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`TRACE(level, ("FCVT.WU.S"));
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end
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end
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end
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`INST_FPU_I2F: begin
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if (fdst_d) begin
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if (fcvt_l) begin
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`TRACE(level, ("FCVT.D.L"));
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end else begin
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`TRACE(level, ("FCVT.D.W"));
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end
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end else begin
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if (fcvt_l) begin
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`TRACE(level, ("FCVT.S.L"));
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end else begin
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`TRACE(level, ("FCVT.S.W"));
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end
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end
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end
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`INST_FPU_U2F: begin
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if (fdst_d) begin
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if (fcvt_l) begin
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`TRACE(level, ("FCVT.D.LU"));
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end else begin
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`TRACE(level, ("FCVT.D.WU"));
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end
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end else begin
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if (fcvt_l) begin
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`TRACE(level, ("FCVT.S.LU"));
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end else begin
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`TRACE(level, ("FCVT.S.WU"));
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end
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end
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end
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`INST_FPU_MISC: begin
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if (fdst_d) begin
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case (op_mod)
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0: `TRACE(level, ("FSGNJ.D"));
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1: `TRACE(level, ("FSGNJN.D"));
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2: `TRACE(level, ("FSGNJX.D"));
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3: `TRACE(level, ("FCLASS.D"));
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4: `TRACE(level, ("FMV.X.D"));
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5: `TRACE(level, ("FMV.D.X"));
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6: `TRACE(level, ("FMIN.D"));
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7: `TRACE(level, ("FMAX.D"));
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endcase
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end else begin
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case (op_mod)
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0: `TRACE(level, ("FSGNJ.S"));
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1: `TRACE(level, ("FSGNJN.S"));
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2: `TRACE(level, ("FSGNJX.S"));
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3: `TRACE(level, ("FCLASS.S"));
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4: `TRACE(level, ("FMV.X.S"));
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5: `TRACE(level, ("FMV.S.X"));
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6: `TRACE(level, ("FMIN.S"));
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7: `TRACE(level, ("FMAX.S"));
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endcase
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end
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end
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default: `TRACE(level, ("?"));
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endcase
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end
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`EX_SFU: begin
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case (`INST_SFU_BITS'(op_type))
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`INST_SFU_TMC: `TRACE(level, ("TMC"));
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`INST_SFU_WSPAWN:`TRACE(level, ("WSPAWN"));
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`INST_SFU_SPLIT: `TRACE(level, ("SPLIT"));
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`INST_SFU_JOIN: `TRACE(level, ("JOIN"));
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`INST_SFU_BAR: `TRACE(level, ("BAR"));
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`INST_SFU_PRED: `TRACE(level, ("PRED"));
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`INST_SFU_CSRRW: begin if (use_imm) `TRACE(level, ("CSRRWI")); else `TRACE(level, ("CSRRW")); end
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`INST_SFU_CSRRS: begin if (use_imm) `TRACE(level, ("CSRRSI")); else `TRACE(level, ("CSRRS")); end
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`INST_SFU_CSRRC: begin if (use_imm) `TRACE(level, ("CSRRCI")); else `TRACE(level, ("CSRRC")); end
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default: `TRACE(level, ("?"));
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endcase
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end
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default: `TRACE(level, ("?"));
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endcase
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endtask
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task trace_base_dcr(input int level, input [`VX_DCR_ADDR_WIDTH-1:0] addr);
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case (addr)
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`VX_DCR_BASE_STARTUP_ADDR0: `TRACE(level, ("STARTUP_ADDR0"));
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`VX_DCR_BASE_STARTUP_ADDR1: `TRACE(level, ("STARTUP_ADDR1"));
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`VX_DCR_BASE_MPM_CLASS: `TRACE(level, ("MPM_CLASS"));
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default: `TRACE(level, ("?"));
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endcase
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endtask
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`endif
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`endif // VX_TRACE_VH
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