44 lines
1.0 KiB
Makefile
44 lines
1.0 KiB
Makefile
PARAM += -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DWORD_SIZE=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4
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# control RTL debug print states
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DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
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-DDBG_PRINT_CORE_DCACHE \
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-DDBG_PRINT_CACHE_BANK \
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-DDBG_PRINT_CACHE_SNP \
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-DDBG_PRINT_CACHE_MSRQ \
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-DDBG_PRINT_DRAM \
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-DDBG_PRINT_OPAE
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#DBG_PRINT=$(DBG_PRINT_FLAGS)
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INCLUDE = -I../../rtl/ -I../../rtl/cache -I../../rtl/libs
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SRCS = cache_sim.cpp
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all: build
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CF += -std=c++11 -fms-extensions -I../..
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VF += --language 1800-2009 --assert -Wall --trace #-Wpedantic
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VF += -Wno-DECLFILENAME
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VF += --x-initial unique
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VF += -exe $(SRCS) $(INCLUDE)
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DBG += -DVCD_OUTPUT $(DBG_PRINT)
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gen:
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verilator $(VF) -DNDEBUG -cc VX_cache.v $(PARAM) -CFLAGS '$(CF) -DNDEBUG $(PARAM)' --exe $(SRCS)
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build: gen
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(cd obj_dir && make -j -f VVX_cache.mk)
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run: build
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(cd obj_dir && ./VVX_cache)
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clean:
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rm -rf obj_dir
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