64 lines
2.0 KiB
Systemverilog
64 lines
2.0 KiB
Systemverilog
// Copyright 2024 blaise
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// A pipelined elastic buffer operates at full bandwidth where push can happen if the buffer is not empty but is going empty
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// It has the following benefits:
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// + Full-bandwidth throughput
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// + use only one register for storage
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// + data_out is fully registered
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// It has the following limitations:
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// + ready_in and ready_out are coupled
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_pipe_buffer #(
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parameter DATAW = 1,
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parameter PASSTHRU = 0
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) (
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input wire clk,
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input wire reset,
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input wire valid_in,
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output wire ready_in,
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input wire [DATAW-1:0] data_in,
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output wire [DATAW-1:0] data_out,
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input wire ready_out,
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output wire valid_out
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);
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if (PASSTHRU != 0) begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign ready_in = ready_out;
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assign valid_out = valid_in;
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assign data_out = data_in;
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end else begin
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wire stall = valid_out && ~ready_out;
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VX_pipe_register #(
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.DATAW (1 + DATAW),
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.RESETW (1)
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) pipe_register (
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.clk (clk),
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.reset (reset),
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.enable (~stall),
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.data_in ({valid_in, data_in}),
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.data_out ({valid_out, data_out})
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);
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assign ready_in = ~stall;
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end
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endmodule
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`TRACING_ON
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