48 lines
2.2 KiB
Verilog
48 lines
2.2 KiB
Verilog
`include "VX_define.vh"
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module VX_dcache_arb (
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input wire io_select,
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// Core request
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VX_cache_core_req_if core_req_if,
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// Dcache request
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VX_cache_core_req_if core_dcache_req_if,
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// I/O request
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VX_cache_core_req_if core_io_req_if,
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// Dcache response
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VX_cache_core_rsp_if core_dcache_rsp_if,
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// I/O response
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VX_cache_core_rsp_if core_io_rsp_if,
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// Core response
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VX_cache_core_rsp_if core_rsp_if
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);
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assign core_dcache_req_if.core_req_valid = core_req_if.core_req_valid & {`NUM_THREADS{~io_select}};
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assign core_dcache_req_if.core_req_rw = core_req_if.core_req_rw;
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assign core_dcache_req_if.core_req_byteen = core_req_if.core_req_byteen;
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assign core_dcache_req_if.core_req_addr = core_req_if.core_req_addr;
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assign core_dcache_req_if.core_req_data = core_req_if.core_req_data;
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assign core_dcache_req_if.core_req_tag = core_req_if.core_req_tag;
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assign core_io_req_if.core_req_valid = core_req_if.core_req_valid & {`NUM_THREADS{io_select}};
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assign core_io_req_if.core_req_rw = core_req_if.core_req_rw;
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assign core_io_req_if.core_req_byteen = core_req_if.core_req_byteen;
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assign core_io_req_if.core_req_addr = core_req_if.core_req_addr;
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assign core_io_req_if.core_req_data = core_req_if.core_req_data;
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assign core_io_req_if.core_req_tag = core_req_if.core_req_tag;
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assign core_req_if.core_req_ready = io_select ? core_io_req_if.core_req_ready : core_dcache_req_if.core_req_ready;
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wire dcache_rsp_valid = (| core_dcache_rsp_if.core_rsp_valid);
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assign core_rsp_if.core_rsp_valid = dcache_rsp_valid ? core_dcache_rsp_if.core_rsp_valid : core_io_rsp_if.core_rsp_valid;
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assign core_rsp_if.core_rsp_data = dcache_rsp_valid ? core_dcache_rsp_if.core_rsp_data : core_io_rsp_if.core_rsp_data;
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assign core_rsp_if.core_rsp_tag = dcache_rsp_valid ? core_dcache_rsp_if.core_rsp_tag : core_io_rsp_if.core_rsp_tag;
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assign core_dcache_rsp_if.core_rsp_ready = core_rsp_if.core_rsp_ready;
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assign core_io_rsp_if.core_rsp_ready = core_rsp_if.core_rsp_ready && ~dcache_rsp_valid;
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endmodule |