67 lines
2.0 KiB
Tcl
67 lines
2.0 KiB
Tcl
load_package flow
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package require cmdline
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set options {
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{ "project.arg" "" "Project name" }
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{ "family.arg" "" "Device family name" }
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{ "device.arg" "" "Device name" }
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{ "top.arg" "" "Top level module" }
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{ "src.arg" "" "Verilog source file" }
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{ "inc.arg" "" "Include path (optional)" }
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{ "sdc.arg" "" "Timing Design Constraints file (optional)" }
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{ "set.arg" "" "Macro value (optional)" }
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}
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set q_args_orig $quartus(args)
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array set opts [::cmdline::getoptions quartus(args) $options]
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# Verify required parameters
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set requiredParameters {project family device top src}
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foreach p $requiredParameters {
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if {$opts($p) == ""} {
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puts stderr "Missing required parameter: -$p"
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exit 1
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}
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}
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project_new $opts(project) -overwrite
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set_global_assignment -name FAMILY $opts(family)
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set_global_assignment -name DEVICE $opts(device)
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set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
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set idx 0
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foreach arg $q_args_orig {
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incr idx
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if [string match "-src" $arg] {
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set_global_assignment -name VERILOG_FILE [lindex $q_args_orig $idx]
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}
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if [string match "-inc" $arg] {
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set_global_assignment -name SEARCH_PATH [lindex $q_args_orig $idx]
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}
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if [string match "-sdc" $arg] {
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set_global_assignment -name SDC_FILE [lindex $q_args_orig $idx]
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}
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if [string match "-set" $arg] {
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set_global_assignment -name VERILOG_MACRO [lindex $q_args_orig $idx]
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}
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}
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proc make_all_pins_virtual {} {
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execute_module -tool map
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set name_ids [get_names -filter * -node_type pin]
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foreach_in_collection name_id $name_ids {
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set pin_name [get_name_info -info full_path $name_id]
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post_message "Making VIRTUAL_PIN assignment to $pin_name"
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set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
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}
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export_assignments
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}
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make_all_pins_virtual
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project_close |