154 lines
4.6 KiB
Verilog
154 lines
4.6 KiB
Verilog
`include "VX_define.vh"
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module VX_gpr_ram (
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input wire clk,
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input wire reset,
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input wire write_ce,
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VX_gpr_read_if gpr_read_if,
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VX_wb_if writeback_if,
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output wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] a_reg_data,
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output wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] b_reg_data
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);
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wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] a_reg_data_unqual;
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wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] b_reg_data_unqual;
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assign a_reg_data = (gpr_read_if.rs1 != 0) ? a_reg_data_unqual : 0;
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assign b_reg_data = (gpr_read_if.rs2 != 0) ? b_reg_data_unqual : 0;
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wire [`NUM_THREADS-1:0] write_enable = writeback_if.valid & {`NUM_THREADS{write_ce && (writeback_if.wb != 0)}};
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`ifndef ASIC
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reg [`NUM_THREADS-1:0][31:0] ram[31:0];
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`UNUSED_VAR(reset)
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genvar i;
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for (i = 0; i < `NUM_THREADS; i++) begin
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always @(posedge clk) begin
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if (write_enable[i]) begin
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ram[writeback_if.rd][i] <= writeback_if.data[i];
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end
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end
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end
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assign a_reg_data_unqual = ram[gpr_read_if.rs1];
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assign b_reg_data_unqual = ram[gpr_read_if.rs2];
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`else
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wire going_to_write = write_enable & (| writeback_if.wb_valid);
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wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] write_bit_mask;
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genvar i;
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for (i = 0; i < `NUM_THREADS; i++) begin
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wire local_write = write_enable & writeback_if.wb_valid[i];
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assign write_bit_mask[i] = {`NUM_GPRS{~local_write}};
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end
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wire cenb = 0;
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wire cena_1 = 0;
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wire cena_2 = 0;
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wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] tmp_a;
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wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] tmp_b;
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`ifndef SYN
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genvar j;
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for (i = 0; i < `NUM_THREADS; i++) begin
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for (j = 0; j < `NUM_GPRS; j++) begin
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assign a_reg_data_unqual[i][j] = ((tmp_a[i][j] === 1'dx) || cena_1) ? 1'b0 : tmp_a[i][j];
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assign b_reg_data_unqual[i][j] = ((tmp_b[i][j] === 1'dx) || cena_2) ? 1'b0 : tmp_b[i][j];
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end
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end
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`else
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assign a_reg_data_unqual = tmp_a;
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assign b_reg_data_unqual = tmp_b;
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`endif
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wire [`NUM_THREADS-1:0][`NUM_GPRS-1:0] to_write = writeback_if.write_data;
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for (i = 0; i < 'NT; i=i+4)
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begin
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`IGNORE_WARNINGS_BEGIN
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rf2_32x128_wm1 first_ram (
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.CENYA(),
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.AYA(),
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.CENYB(),
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.WENYB(),
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.AYB(),
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.QA(tmp_a[(i+3):(i)]),
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.SOA(),
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.SOB(),
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.CLKA(clk),
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.CENA(cena_1),
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.AA(gpr_read_if.rs1[(i+3):(i)]),
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.CLKB(clk),
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.CENB(cenb),
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.WENB(write_bit_mask[(i+3):(i)]),
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.AB(writeback_if.rd[(i+3):(i)]),
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.DB(to_write[(i+3):(i)]),
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.EMAA(3'b011),
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.EMASA(1'b0),
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.EMAB(3'b011),
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.TENA(1'b1),
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.TCENA(1'b0),
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.TAA(5'b0),
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.TENB(1'b1),
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.TCENB(1'b0),
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.TWENB(128'b0),
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.TAB(5'b0),
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.TDB(128'b0),
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.RET1N(1'b1),
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.SIA(2'b0),
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.SEA(1'b0),
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.DFTRAMBYP(1'b0),
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.SIB(2'b0),
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.SEB(1'b0),
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.COLLDISN(1'b1)
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);
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rf2_`NUM_GPRSx128_wm1 second_ram (
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.CENYA(),
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.AYA(),
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.CENYB(),
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.WENYB(),
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.AYB(),
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.QA(tmp_b[(i+3):(i)]),
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.SOA(),
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.SOB(),
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.CLKA(clk),
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.CENA(cena_2),
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.AA(gpr_read_if.rs2[(i+3):(i)]),
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.CLKB(clk),
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.CENB(cenb),
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.WENB(write_bit_mask[(i+3):(i)]),
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.AB(writeback_if.rd[(i+3):(i)]),
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.DB(to_write[(i+3):(i)]),
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.EMAA(3'b011),
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.EMASA(1'b0),
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.EMAB(3'b011),
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.TENA(1'b1),
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.TCENA(1'b0),
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.TAA(5'b0),
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.TENB(1'b1),
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.TCENB(1'b0),
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.TWENB(128'b0),
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.TAB(5'b0),
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.TDB(128'b0),
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.RET1N(1'b1),
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.SIA(2'b0),
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.SEA(1'b0),
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.DFTRAMBYP(1'b0),
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.SIB(2'b0),
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.SEB(1'b0),
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.COLLDISN(1'b1)
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);
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`IGNORE_WARNINGS_END
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end
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`endif
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endmodule
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