Blaise Tine e770824d47 fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance

2021-01-10 20:26:15 -08:00

..

cache

pipeline refactoring - fmax >= 222 mhz

2020-08-14 21:50:14 -07:00

core

Adding Altera Stratix 10 support

2020-12-27 10:44:57 -08:00

core8

Adding Altera Stratix 10 support

2020-12-27 10:44:57 -08:00

pipeline

FPU float<->int conversion optimization

2020-12-29 15:37:45 -08:00

top

Adding Altera Stratix 10 support

2020-12-27 10:44:57 -08:00

top1

Adding Altera Stratix 10 support

2020-12-27 10:44:57 -08:00

top2

Adding Altera Stratix 10 support

2020-12-27 10:44:57 -08:00

top8

minor updates

2021-01-05 15:03:41 -08:00

top16

fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance

2021-01-10 20:26:15 -08:00

top32

minor updates

2021-01-06 07:18:14 -08:00

unittest

minor updates

2021-01-06 07:18:14 -08:00

vortex

Adding Altera Stratix 10 support

2020-12-27 10:44:57 -08:00

.gitignore

minor updates

2021-01-06 07:18:14 -08:00

project.sdc

performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

2020-12-19 02:45:06 -08:00

project.tcl

minor update

2021-01-06 19:59:04 -08:00

timing-html.tcl

performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

2020-12-19 02:45:06 -08:00