90 lines
2.4 KiB
Verilog
90 lines
2.4 KiB
Verilog
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`include "VX_define.v"
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module VX_gpr (
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input wire clk,
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input wire valid_write_request,
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VX_gpr_read_inter VX_gpr_read,
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VX_wb_inter VX_writeback_inter,
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output reg[`NT_M1:0][31:0] out_a_reg_data,
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output reg[`NT_M1:0][31:0] out_b_reg_data
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);
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wire write_enable;
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assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd != 5'h0));
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// always @(*) begin
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// if(write_enable) $display("Writing to %d: %d = %h",VX_writeback_inter.wb_warp_num, VX_writeback_inter.rd, VX_writeback_inter.write_data[0][31:0]);
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// end
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byte_enabled_simple_dual_port_ram first_ram(
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.we (write_enable),
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.clk (clk),
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.waddr (VX_writeback_inter.rd),
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.raddr1(VX_gpr_read.rs1),
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.raddr2(VX_gpr_read.rs2),
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.be (VX_writeback_inter.wb_valid),
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.wdata (VX_writeback_inter.write_data),
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.q1 (out_a_reg_data),
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.q2 (out_b_reg_data)
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);
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// // USING RAM blocks
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// // First RAM
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// byte_enabled_simple_dual_port_ram first_ram(
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// .we (write_enable),
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// .clk (clk),
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// .waddr(VX_writeback_inter.rd),
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// .raddr(VX_gpr_read.rs1),
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// .be (VX_writeback_inter.wb_valid),
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// .wdata(VX_writeback_inter.write_data),
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// .q (out_a_reg_data)
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// );
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// // Second RAM block
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// byte_enabled_simple_dual_port_ram second_ram(
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// .we (write_enable),
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// .clk (clk),
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// .waddr(VX_writeback_inter.rd),
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// .raddr(VX_gpr_read.rs2),
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// .be (VX_writeback_inter.wb_valid),
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// .wdata(VX_writeback_inter.write_data),
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// .q (out_b_reg_data)
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// );
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// logic[`NT_M1:0][31:0] gpr[31:0]; // gpr[register_number][thread_number][data_bits]
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// wire write_enable;
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// assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd != 5'h0));
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// assign read_enable = valid_request;
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// // Using Registers
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// integer thread_index;
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// always_ff@(posedge clk)
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// begin
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// if (write_enable) begin
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// for (thread_index = 0; thread_index <= `NT_M1; thread_index = thread_index + 1) begin
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// if (VX_writeback_inter.wb_valid[thread_index]) begin
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// gpr[VX_writeback_inter.rd][thread_index] <= VX_writeback_inter.write_data[thread_index];
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// end
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// end
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// end
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// out_a_reg_data <= gpr[VX_gpr_read.rs1];
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// out_b_reg_data <= gpr[VX_gpr_read.rs2];
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// end
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endmodule |