f126a23114
gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code.
10 lines
104 B
Plaintext
10 lines
104 B
Plaintext
./rtl/obj_dir/
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./rtl/obj_dir/*.vcd
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./rtl/.*
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./rtl/modelsim/*.vcd
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*.vcd
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.*
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!.gitignore
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*.pyc
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__pycache__
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