f126a23114
gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code.
7 lines
90 B
Makefile
7 lines
90 B
Makefile
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.PHONY: build_config
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build_config:
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../rtl/gen_config.py --outv none --outc ./config.h
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