79 lines
1.6 KiB
Verilog
79 lines
1.6 KiB
Verilog
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`include "VX_define.v"
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module VX_m_w_reg (
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input wire clk,
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input wire[31:0] in_alu_result[`NT_M1:0],
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input wire[31:0] in_mem_result[`NT_M1:0], // NEW
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input wire[4:0] in_rd,
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input wire[1:0] in_wb,
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input wire[4:0] in_rs1,
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input wire[4:0] in_rs2,
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input wire[31:0] in_PC_next,
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input wire in_freeze,
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input wire in_valid[`NT_M1:0],
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output wire[31:0] out_alu_result[`NT_M1:0],
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output wire[31:0] out_mem_result[`NT_M1:0], // NEW
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output wire[4:0] out_rd,
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output wire[1:0] out_wb,
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output wire[4:0] out_rs1,
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output wire[4:0] out_rs2,
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output wire[31:0] out_PC_next,
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output wire out_valid[`NT_M1:0]
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);
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reg[31:0] alu_result[`NT_M1:0];
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reg[31:0] mem_result[`NT_M1:0];
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reg[4:0] rd;
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reg[4:0] rs1;
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reg[4:0] rs2;
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reg[1:0] wb;
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reg[31:0] PC_next;
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reg valid[`NT_M1:0];
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initial begin
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// alu_result = 0;
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// mem_result = 0;
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rd = 0;
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rs1 = 0;
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rs2 = 0;
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wb = 0;
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PC_next = 0;
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// valid = 0;
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end
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assign out_alu_result = alu_result;
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assign out_mem_result = mem_result;
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assign out_rd = rd;
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assign out_rs1 = rs1;
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assign out_rs2 = rs2;
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assign out_wb = wb;
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assign out_PC_next = PC_next;
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assign out_valid = valid;
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always @(posedge clk) begin
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if(in_freeze == 1'b0) begin
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alu_result <= in_alu_result;
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mem_result <= in_mem_result;
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rd <= in_rd;
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rs1 <= in_rs1;
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rs2 <= in_rs2;
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wb <= in_wb;
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PC_next <= in_PC_next;
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valid <= in_valid;
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end
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end
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endmodule // VX_m_w_reg
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