102 lines
4.2 KiB
Verilog
102 lines
4.2 KiB
Verilog
`include "VX_define.vh"
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module VX_io_arb #(
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parameter NUM_REQS = 1,
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parameter WORD_SIZE = 1,
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parameter TAG_IN_WIDTH = 1,
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parameter TAG_OUT_WIDTH = 1,
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parameter WORD_WIDTH = WORD_SIZE * 8,
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parameter ADDR_WIDTH = 32 - `CLOG2(WORD_SIZE),
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parameter REQS_BITS = `CLOG2(NUM_REQS)
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) (
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input wire clk,
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input wire reset,
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// input requests
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input wire [NUM_REQS-1:0][`NUM_THREADS-1:0] io_req_valid_in,
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input wire [NUM_REQS-1:0][TAG_IN_WIDTH-1:0] io_req_tag_in,
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input wire [NUM_REQS-1:0][`NUM_THREADS-1:0][ADDR_WIDTH-1:0] io_req_addr_in,
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input wire [NUM_REQS-1:0] io_req_rw_in,
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input wire [NUM_REQS-1:0][`NUM_THREADS-1:0][WORD_SIZE-1:0] io_req_byteen_in,
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input wire [NUM_REQS-1:0][`NUM_THREADS-1:0][WORD_WIDTH-1:0] io_req_data_in,
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output wire [NUM_REQS-1:0] io_req_ready_in,
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// output request
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output wire [`NUM_THREADS-1:0] io_req_valid_out,
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output wire [TAG_OUT_WIDTH-1:0] io_req_tag_out,
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output wire [`NUM_THREADS-1:0][ADDR_WIDTH-1:0] io_req_addr_out,
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output wire io_req_rw_out,
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output wire [`NUM_THREADS-1:0][WORD_SIZE-1:0] io_req_byteen_out,
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output wire [`NUM_THREADS-1:0][WORD_WIDTH-1:0] io_req_data_out,
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input wire io_req_ready_out,
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// input response
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output wire [NUM_REQS-1:0] io_rsp_valid_in,
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output wire [NUM_REQS-1:0][TAG_IN_WIDTH-1:0] io_rsp_tag_in,
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output wire [NUM_REQS-1:0][WORD_WIDTH-1:0] io_rsp_data_in,
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input wire [NUM_REQS-1:0] io_rsp_ready_in,
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// output response
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input wire io_rsp_valid_out,
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input wire [TAG_OUT_WIDTH-1:0] io_rsp_tag_out,
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input wire [WORD_WIDTH-1:0] io_rsp_data_out,
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output wire io_rsp_ready_out
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);
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wire [NUM_REQS-1:0] valids;
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for (genvar i = 0; i < NUM_REQS; i++) begin
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assign valids[i] = (| io_req_valid_in[i]);
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end
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wire [NUM_REQS-1:0][(`NUM_THREADS + TAG_OUT_WIDTH + (`NUM_THREADS * ADDR_WIDTH) + 1 + (`NUM_THREADS * WORD_SIZE) + (`NUM_THREADS * WORD_WIDTH))-1:0] data_in;
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for (genvar i = 0; i < NUM_REQS; i++) begin
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assign data_in[i] = {{io_req_valid_in[i], io_req_tag_in[i], REQS_BITS'(i)}, io_req_addr_in[i], io_req_rw_in[i], io_req_byteen_in[i], io_req_data_in[i]};
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end
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wire [`NUM_THREADS-1:0] io_req_tmask_out;
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wire io_req_valid_out_unqual;
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VX_stream_arbiter #(
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.NUM_REQS(NUM_REQS),
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.DATAW(`NUM_THREADS + TAG_OUT_WIDTH + (`NUM_THREADS * ADDR_WIDTH) + 1 + (`NUM_THREADS * WORD_SIZE) + (`NUM_THREADS * WORD_WIDTH)),
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.BUFFERED(NUM_REQS >= 4)
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) req_arb (
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.clk (clk),
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.reset (reset),
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.valid_in (valids),
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.valid_out (io_req_valid_out_unqual),
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.data_in (data_in),
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.data_out ({io_req_tmask_out, io_req_tag_out, io_req_addr_out, io_req_rw_out, io_req_byteen_out, io_req_data_out}),
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.ready_in (io_req_ready_in),
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.ready_out (io_req_ready_out)
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);
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assign io_req_valid_out = {`NUM_THREADS{io_req_valid_out_unqual}} & io_req_tmask_out;
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///////////////////////////////////////////////////////////////////////
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if (NUM_REQS > 1) begin
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wire [REQS_BITS-1:0] rsp_sel = io_rsp_tag_out[REQS_BITS-1:0];
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for (genvar i = 0; i < NUM_REQS; i++) begin
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assign io_rsp_valid_in[i] = io_rsp_valid_out && (rsp_sel == REQS_BITS'(i));
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assign io_rsp_tag_in[i] = io_rsp_tag_out[REQS_BITS +: TAG_IN_WIDTH];
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assign io_rsp_data_in[i] = io_rsp_data_out;
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end
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assign io_rsp_ready_out = io_rsp_ready_in[rsp_sel];
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end else begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign io_rsp_valid_in = io_rsp_valid_out;
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assign io_rsp_tag_in = io_rsp_tag_out;
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assign io_rsp_data_in = io_rsp_data_out;
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assign io_rsp_ready_out = io_rsp_ready_in;
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end
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endmodule |