137 lines
6.0 KiB
Verilog
137 lines
6.0 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_cache_wb_sel_merge #(
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// Size of cache in bytes
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parameter CACHE_SIZE_BYTES = 1024,
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE_BYTES = 16,
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// Number of banks {1, 2, 4, 8,...}
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parameter NUM_BANKS = 8,
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// Size of a word in bytes
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parameter WORD_SIZE_BYTES = 4,
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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parameter NUM_REQUESTS = 2,
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// Number of cycles to complete stage 1 (read from memory)
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parameter STAGE_1_CYCLES = 2,
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// Function ID, {Dcache=0, Icache=1, Sharedmemory=2}
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parameter FUNC_ID = 0,
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Core Request Queue Size
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parameter REQQ_SIZE = 8,
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// Miss Reserv Queue Knob
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parameter MRVQ_SIZE = 8,
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// Dram Fill Rsp Queue Size
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parameter DFPQ_SIZE = 2,
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// Snoop Req Queue
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parameter SNRQ_SIZE = 8,
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Core Writeback Queue Size
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parameter CWBQ_SIZE = 8,
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// Dram Writeback Queue Size
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parameter DWBQ_SIZE = 4,
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// Dram Fill Req Queue Size
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parameter DFQQ_SIZE = 8,
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// Lower Level Cache Hit Queue Size
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parameter LLVQ_SIZE = 16,
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// Fill Invalidator Size {Fill invalidator must be active}
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parameter FILL_INVALIDAOR_SIZE = 16,
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// Dram knobs
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parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
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) (
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// Per Bank WB
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input wire [NUM_BANKS-1:0] per_bank_wb_valid,
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input wire [NUM_BANKS-1:0][`LOG2UP(NUM_REQUESTS)-1:0] per_bank_wb_tid,
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input wire [NUM_BANKS-1:0][4:0] per_bank_wb_rd,
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input wire [NUM_BANKS-1:0][1:0] per_bank_wb_wb,
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input wire [NUM_BANKS-1:0][`NW_BITS-1:0] per_bank_wb_warp_num,
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input wire [NUM_BANKS-1:0][`WORD_SIZE_RNG] per_bank_wb_data,
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input wire [NUM_BANKS-1:0][31:0] per_bank_wb_pc,
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input wire [NUM_BANKS-1:0][31:0] per_bank_wb_addr,
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output wire [NUM_BANKS-1:0] per_bank_wb_pop,
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// Core Writeback
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input wire core_rsp_ready,
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output reg [NUM_REQUESTS-1:0] core_rsp_valid,
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output reg [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_rsp_data,
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output reg [NUM_REQUESTS-1:0][31:0] core_rsp_pc,
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output wire [4:0] core_rsp_read,
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output wire [1:0] core_rsp_write,
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output wire [`NW_BITS-1:0] core_rsp_warp_num,
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output reg [NUM_REQUESTS-1:0][31:0] core_rsp_addr
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);
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reg [NUM_BANKS-1:0] per_bank_wb_pop_unqual;
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assign per_bank_wb_pop = per_bank_wb_pop_unqual & {NUM_BANKS{core_rsp_ready}};
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// wire[NUM_BANKS-1:0] bank_wants_wb;
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// genvar curr_bank;
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// generate
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// for (curr_bank = 0; curr_bank < NUM_BANKS; curr_bank=curr_bank+1) begin
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// assign bank_wants_wb[curr_bank] = (|per_bank_wb_valid[curr_bank]);
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// end
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// endgenerate
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wire [`LOG2UP(NUM_BANKS)-1:0] main_bank_index;
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wire found_bank;
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VX_generic_priority_encoder #(
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.N(NUM_BANKS)
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) sel_bank (
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.valids(per_bank_wb_valid),
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.index (main_bank_index),
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.found (found_bank)
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);
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assign core_rsp_read = per_bank_wb_rd[main_bank_index];
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assign core_rsp_write = per_bank_wb_wb[main_bank_index];
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assign core_rsp_warp_num = per_bank_wb_warp_num[main_bank_index];
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integer i;
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generate
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always @(*) begin
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core_rsp_valid = 0;
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core_rsp_data = 0;
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core_rsp_pc = 0;
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core_rsp_addr = 0;
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for (i = 0; i < NUM_BANKS; i = i + 1) begin
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if ((FUNC_ID == `L2FUNC_ID) || (FUNC_ID == `L3FUNC_ID)) begin
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if (found_bank
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&& !core_rsp_valid[per_bank_wb_tid[i]]
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&& per_bank_wb_valid[i]
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&& ((main_bank_index == `LOG2UP(NUM_BANKS)'(i))
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|| (per_bank_wb_tid[i] != per_bank_wb_tid[main_bank_index]))) begin
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core_rsp_valid[per_bank_wb_tid[i]] = 1;
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core_rsp_data[per_bank_wb_tid[i]] = per_bank_wb_data[i];
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core_rsp_pc[per_bank_wb_tid[i]] = per_bank_wb_pc[i];
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core_rsp_addr[per_bank_wb_tid[i]] = per_bank_wb_addr[i];
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per_bank_wb_pop_unqual[i] = 1;
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end else begin
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per_bank_wb_pop_unqual[i] = 0;
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end
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end else begin
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if (((main_bank_index == `LOG2UP(NUM_BANKS)'(i))
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|| (per_bank_wb_tid[i] != per_bank_wb_tid[main_bank_index]))
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&& found_bank
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&& !core_rsp_valid[per_bank_wb_tid[i]]
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&& (per_bank_wb_valid[i])
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&& (per_bank_wb_rd[i] == per_bank_wb_rd[main_bank_index])
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&& (per_bank_wb_warp_num[i] == per_bank_wb_warp_num[main_bank_index])) begin
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core_rsp_valid[per_bank_wb_tid[i]] = 1;
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core_rsp_data[per_bank_wb_tid[i]] = per_bank_wb_data[i];
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core_rsp_pc[per_bank_wb_tid[i]] = per_bank_wb_pc[i];
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core_rsp_addr[per_bank_wb_tid[i]] = per_bank_wb_addr[i];
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per_bank_wb_pop_unqual[i] = 1;
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end else begin
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per_bank_wb_pop_unqual[i] = 0;
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end
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end
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end
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end
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endgenerate
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endmodule |