100 lines
3.6 KiB
Verilog
100 lines
3.6 KiB
Verilog
`include "VX_define.vh"
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module VX_csr_io_arb #(
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parameter NUM_REQUESTS = 1,
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parameter REQS_BITS = `LOG2UP(NUM_REQUESTS)
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) (
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input wire clk,
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input wire reset,
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input wire [REQS_BITS-1:0] request_id,
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// input requests
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input wire csr_io_req_valid_in,
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input wire [11:0] csr_io_req_addr_in,
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input wire csr_io_req_rw_in,
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input wire [31:0] csr_io_req_data_in,
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output wire csr_io_req_ready_in,
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// output request
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output wire [NUM_REQUESTS-1:0] csr_io_req_valid_out,
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output wire [NUM_REQUESTS-1:0][11:0] csr_io_req_addr_out,
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output wire [NUM_REQUESTS-1:0] csr_io_req_rw_out,
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output wire [NUM_REQUESTS-1:0][31:0] csr_io_req_data_out,
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input wire [NUM_REQUESTS-1:0] csr_io_req_ready_out,
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// input response
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input wire [NUM_REQUESTS-1:0] csr_io_rsp_valid_in,
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input wire [NUM_REQUESTS-1:0][31:0] csr_io_rsp_data_in,
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output wire [NUM_REQUESTS-1:0] csr_io_rsp_ready_in,
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// output response
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output wire csr_io_rsp_valid_out,
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output wire [31:0] csr_io_rsp_data_out,
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input wire csr_io_rsp_ready_out
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);
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if (NUM_REQUESTS > 1) begin
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for (genvar i = 0; i < NUM_REQUESTS; i++) begin
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assign csr_io_req_valid_out[i] = csr_io_req_valid_in && (request_id == `REQS_BITS'(i));
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assign csr_io_req_addr_out[i] = csr_io_req_addr_in;
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assign csr_io_req_rw_out[i] = csr_io_req_rw_in;
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assign csr_io_req_data_out[i] = csr_io_req_data_in;
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end
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assign csr_io_req_ready_in = csr_io_req_ready_out[request_id];
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///////////////////////////////////////////////////////////////////////
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wire [REQS_BITS-1:0] rsp_idx;
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wire [NUM_REQUESTS-1:0] rsp_1hot;
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VX_rr_arbiter #(
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.N(NUM_REQUESTS)
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) rsp_arb (
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.clk (clk),
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.reset (reset),
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.requests (csr_io_rsp_valid_in),
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`UNUSED_PIN (grant_valid),
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.grant_index (rsp_idx),
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.grant_onehot (rsp_1hot)
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);
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wire stall = ~csr_io_rsp_ready_out && csr_io_rsp_valid_out;
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VX_generic_register #(
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.N(1 + 32),
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.R(1),
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.PASSTHRU(NUM_REQUESTS <= 2)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall),
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.flush (1'b0),
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.in ({csr_io_rsp_valid_in[rsp_idx], csr_io_rsp_data_in[rsp_idx]}),
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.out ({csr_io_rsp_valid_out, csr_io_rsp_data_out})
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);
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for (genvar i = 0; i < NUM_REQUESTS; i++) begin
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assign csr_io_rsp_ready_in[i] = rsp_1hot[i] && ~stall;
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end
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end else begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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`UNUSED_VAR (request_id)
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assign csr_io_req_valid_out = csr_io_req_valid_in;
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assign csr_io_req_addr_out = csr_io_req_addr_in;
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assign csr_io_req_rw_out = csr_io_req_rw_in;
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assign csr_io_req_data_out = csr_io_req_data_in;
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assign csr_io_req_ready_in = csr_io_req_ready_out;
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assign csr_io_rsp_valid_out = csr_io_rsp_valid_in;
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assign csr_io_rsp_data_out = csr_io_rsp_data_in;
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assign csr_io_rsp_ready_in = csr_io_rsp_ready_out;
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end
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endmodule |