78 lines
2.6 KiB
Verilog
78 lines
2.6 KiB
Verilog
`include "VX_cache_config.v"
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module VX_cache_dfq_queue
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(
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input wire clk,
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input wire reset,
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input wire dfqq_push,
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input wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req,
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input wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr,
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input wire dfqq_pop,
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output wire dfqq_req,
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output wire[31:0] dfqq_req_addr,
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output wire dfqq_empty,
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output wire dfqq_full
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);
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wire[`NUMBER_BANKS-1:0] out_per_bank_dram_fill_req;
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wire[`NUMBER_BANKS-1:0][31:0] out_per_bank_dram_fill_req_addr;
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reg [`NUMBER_BANKS-1:0] use_per_bank_dram_fill_req;
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reg [`NUMBER_BANKS-1:0][31:0] use_per_bank_dram_fill_req_addr;
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wire[`NUMBER_BANKS-1:0] qual_bank_dram_fill_req;
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wire[`NUMBER_BANKS-1:0][31:0] qual_bank_dram_fill_req_addr;
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wire[`NUMBER_BANKS-1:0] updated_bank_dram_fill_req;
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wire use_empty = !(|use_per_bank_dram_fill_req);
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wire out_empty = !(|out_per_bank_dram_fill_req);
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wire push_qual = dfqq_push && !dfqq_full;
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wire pop_qual = dfqq_pop && use_empty && !out_empty && !dfqq_empty;
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VX_generic_queue #(.DATAW(`NUMBER_BANKS * (1+32)), .SIZE(`dFQQ_SIZE)) dfqq_queue(
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.clk (clk),
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.reset (reset),
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.push (push_qual),
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.in_data ({per_bank_dram_fill_req, per_bank_dram_fill_req_addr}),
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.pop (pop_qual),
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.out_data({out_per_bank_dram_fill_req, out_per_bank_dram_fill_req_addr}),
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.empty (dfqq_empty),
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.full (dfqq_full)
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);
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assign qual_bank_dram_fill_req = use_empty ? out_per_bank_dram_fill_req : use_per_bank_dram_fill_req;
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assign qual_bank_dram_fill_req_addr = use_empty ? out_per_bank_dram_fill_req_addr : use_per_bank_dram_fill_req_addr;
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wire[`vx_clog2(`NUMBER_BANKS)-1:0] qual_request_index;
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wire qual_has_request;
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VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_bank(
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.valids(qual_bank_dram_fill_req),
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.index (qual_request_index),
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.found (qual_has_request)
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);
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assign dfqq_req = qual_bank_dram_fill_req [qual_request_index];
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assign dfqq_req_addr = qual_bank_dram_fill_req_addr[qual_request_index];
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assign updated_bank_dram_fill_req = qual_bank_dram_fill_req & (~(1 << qual_request_index));
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always @(posedge clk or reset) begin
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if (reset) begin
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use_per_bank_dram_fill_req <= 0;
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use_per_bank_dram_fill_req_addr <= 0;
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end else begin
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if (dfqq_pop && qual_has_request) begin
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use_per_bank_dram_fill_req <= updated_bank_dram_fill_req;
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use_per_bank_dram_fill_req_addr <= qual_bank_dram_fill_req_addr;
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end
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end
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end
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endmodule |