114 lines
2.4 KiB
Verilog
114 lines
2.4 KiB
Verilog
module VX_back_end (
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input wire clk,
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input wire reset,
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input wire schedule_delay,
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input wire[31:0] csr_decode_csr_data,
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output wire out_mem_delay,
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VX_jal_response_inter VX_jal_rsp,
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VX_branch_response_inter VX_branch_rsp,
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VX_frE_to_bckE_req_inter VX_bckE_req,
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VX_wb_inter VX_writeback_inter,
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VX_warp_ctl_inter VX_warp_ctl,
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VX_dcache_response_inter VX_dcache_rsp,
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VX_dcache_request_inter VX_dcache_req,
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VX_csr_write_request_inter VX_csr_w_req
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);
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wire[11:0] execute_csr_address;
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wire execute_is_csr;
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reg[31:0] execute_csr_result;
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wire execute_jal;
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wire[31:0] execute_jal_dest;
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VX_mw_wb_inter VX_mw_wb();
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VX_mem_req_inter VX_exe_mem_req();
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VX_mem_req_inter VX_mem_req();
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VX_gpr_data_inter VX_gpr_data();
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VX_frE_to_bckE_req_inter VX_bckE_req_out();
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// LSU input + output
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VX_lsu_req_inter VX_lsu_req();
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VX_inst_mem_wb_inter VX_mem_wb();
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// Exec unit input + output
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VX_exec_unit_req_inter VX_exec_unit_req();
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VX_inst_exec_wb_inter VX_inst_exec_wb();
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// GPU unit input
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VX_gpu_inst_req_inter VX_gpu_inst_req();
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VX_gpr_stage VX_gpr_stage(
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.clk (clk),
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.schedule_delay (schedule_delay),
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.VX_writeback_inter(VX_writeback_inter),
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.VX_bckE_req (VX_bckE_req),
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.VX_bckE_req_out (VX_bckE_req_out),
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.VX_gpr_data (VX_gpr_data)
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);
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VX_inst_multiplex VX_inst_mult(
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.VX_bckE_req (VX_bckE_req_out),
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.VX_gpr_data (VX_gpr_data),
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.VX_exec_unit_req(VX_exec_unit_req),
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.VX_lsu_req (VX_lsu_req),
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.VX_gpu_inst_req (VX_gpu_inst_req)
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);
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VX_lsu load_store_unit(
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// .clk (clk),
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.VX_lsu_req (VX_lsu_req),
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.VX_mem_wb (VX_mem_wb),
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.VX_dcache_rsp(VX_dcache_rsp),
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.VX_dcache_req(VX_dcache_req),
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.out_delay (out_mem_delay)
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);
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VX_execute_unit VX_execUnit(
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// .clk (clk),
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.VX_exec_unit_req(VX_exec_unit_req),
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.VX_inst_exec_wb (VX_inst_exec_wb),
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.VX_jal_rsp (VX_jal_rsp),
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.VX_branch_rsp (VX_branch_rsp),
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.in_csr_data (csr_decode_csr_data),
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.out_csr_address (VX_csr_w_req.csr_address),
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.out_is_csr (VX_csr_w_req.is_csr),
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.out_csr_result (VX_csr_w_req.csr_result)
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);
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VX_gpgpu_inst VX_gpgpu_inst(
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.VX_gpu_inst_req(VX_gpu_inst_req),
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.VX_warp_ctl (VX_warp_ctl)
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);
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VX_writeback VX_wb(
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.VX_mem_wb (VX_mem_wb),
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.VX_inst_exec_wb (VX_inst_exec_wb),
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.VX_writeback_inter(VX_writeback_inter)
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);
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endmodule |