362 lines
9.8 KiB
Verilog
362 lines
9.8 KiB
Verilog
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`include "VX_define.v"
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module VX_decode(
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// Fetch Inputs
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VX_inst_meta_inter fd_inst_meta_de,
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// Outputs
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VX_frE_to_bckE_req_inter VX_frE_to_bckE_req,
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VX_wstall_inter VX_wstall,
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VX_join_inter VX_join,
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output wire terminate_sim
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);
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wire[31:0] in_instruction = fd_inst_meta_de.instruction;
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wire[31:0] in_curr_PC = fd_inst_meta_de.inst_pc;
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wire[`NW_M1:0] in_warp_num = fd_inst_meta_de.warp_num;
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assign VX_frE_to_bckE_req.curr_PC = in_curr_PC;
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wire[`NT_M1:0] in_valid = fd_inst_meta_de.valid;
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wire[6:0] curr_opcode;
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wire is_itype;
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wire is_rtype;
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wire is_stype;
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wire is_btype;
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wire is_linst;
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wire is_jal;
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wire is_jalr;
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wire is_lui;
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wire is_auipc;
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wire is_csr;
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wire is_csr_immed;
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wire is_e_inst;
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wire is_gpgpu;
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wire is_wspawn;
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wire is_tmc;
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wire is_split;
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wire is_join;
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wire is_barrier;
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wire[2:0] func3;
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wire[6:0] func7;
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wire[11:0] u_12;
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wire[7:0] jal_b_19_to_12;
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wire jal_b_11;
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wire[9:0] jal_b_10_to_1;
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wire jal_b_20;
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wire jal_b_0;
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wire[20:0] jal_unsigned_offset;
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wire[31:0] jal_1_offset;
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wire[11:0] jalr_immed;
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wire[31:0] jal_2_offset;
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wire jal_sys_cond1;
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wire jal_sys_cond2;
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wire jal_sys_jal;
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wire[31:0] jal_sys_off;
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wire csr_cond1;
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wire csr_cond2;
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wire[11:0] alu_tempp;
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wire alu_shift_i;
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wire[11:0] alu_shift_i_immed;
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wire[1:0] csr_type;
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reg[4:0] csr_alu;
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reg[4:0] alu_op;
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reg[4:0] mul_alu;
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reg[19:0] temp_upper_immed;
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reg temp_jal;
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reg[31:0] temp_jal_offset;
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reg[31:0] temp_itype_immed;
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reg[2:0] temp_branch_type;
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reg temp_branch_stall;
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// always @(posedge reset) begin
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// end
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assign VX_frE_to_bckE_req.valid = fd_inst_meta_de.valid;
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assign VX_frE_to_bckE_req.warp_num = in_warp_num;
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assign curr_opcode = in_instruction[6:0];
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assign VX_frE_to_bckE_req.rd = in_instruction[11:7];
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assign VX_frE_to_bckE_req.rs1 = in_instruction[19:15];
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assign VX_frE_to_bckE_req.rs2 = in_instruction[24:20];
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assign func3 = in_instruction[14:12];
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assign func7 = in_instruction[31:25];
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assign u_12 = in_instruction[31:20];
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assign VX_frE_to_bckE_req.PC_next = in_curr_PC + 32'h4;
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// Write Back sigal
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assign is_rtype = (curr_opcode == `R_INST);
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assign is_linst = (curr_opcode == `L_INST);
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assign is_itype = (curr_opcode == `ALU_INST) || is_linst;
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assign is_stype = (curr_opcode == `S_INST);
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assign is_btype = (curr_opcode == `B_INST);
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assign is_jal = (curr_opcode == `JAL_INST);
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assign is_jalr = (curr_opcode == `JALR_INST);
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assign is_lui = (curr_opcode == `LUI_INST);
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assign is_auipc = (curr_opcode == `AUIPC_INST);
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assign is_csr = (curr_opcode == `SYS_INST) && (func3 != 0);
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assign is_csr_immed = (is_csr) && (func3[2] == 1);
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// assign is_e_inst = (curr_opcode == `SYS_INST) && (func3 == 0);
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assign is_e_inst = in_instruction == 32'h00000073;
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assign is_gpgpu = (curr_opcode == `GPGPU_INST);
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assign is_tmc = is_gpgpu && (func3 == 0); // Goes to BE
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assign is_wspawn = is_gpgpu && (func3 == 1); // Goes to BE
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assign is_barrier = is_gpgpu && (func3 == 4); // Goes to BE
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assign is_split = is_gpgpu && (func3 == 2); // Goes to BE
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assign is_join = is_gpgpu && (func3 == 3); // Doesn't go to BE
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assign VX_join.is_join = is_join;
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assign VX_join.join_warp_num = in_warp_num;
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assign VX_frE_to_bckE_req.is_wspawn = is_wspawn;
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assign VX_frE_to_bckE_req.is_tmc = is_tmc;
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assign VX_frE_to_bckE_req.is_split = is_split;
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assign VX_frE_to_bckE_req.is_barrier = is_barrier;
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assign VX_frE_to_bckE_req.csr_immed = is_csr_immed;
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assign VX_frE_to_bckE_req.is_csr = is_csr;
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assign VX_frE_to_bckE_req.wb = (is_jal || is_jalr || is_e_inst) ? `WB_JAL :
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is_linst ? `WB_MEM :
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(is_itype || is_rtype || is_lui || is_auipc || is_csr) ? `WB_ALU :
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`NO_WB;
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assign VX_frE_to_bckE_req.rs2_src = (is_itype || is_stype) ? `RS2_IMMED : `RS2_REG;
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// MEM signals
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assign VX_frE_to_bckE_req.mem_read = (is_linst) ? func3 : `NO_MEM_READ;
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assign VX_frE_to_bckE_req.mem_write = (is_stype) ? func3 : `NO_MEM_WRITE;
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// UPPER IMMEDIATE
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always @(*) begin
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case(curr_opcode)
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`LUI_INST: temp_upper_immed = {func7, VX_frE_to_bckE_req.rs2, VX_frE_to_bckE_req.rs1, func3};
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`AUIPC_INST: temp_upper_immed = {func7, VX_frE_to_bckE_req.rs2, VX_frE_to_bckE_req.rs1, func3};
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default: temp_upper_immed = 20'h0;
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endcase // curr_opcode
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end
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assign VX_frE_to_bckE_req.upper_immed = temp_upper_immed;
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assign jal_b_19_to_12 = in_instruction[19:12];
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assign jal_b_11 = in_instruction[20];
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assign jal_b_10_to_1 = in_instruction[30:21];
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assign jal_b_20 = in_instruction[31];
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assign jal_b_0 = 1'b0;
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assign jal_unsigned_offset = {jal_b_20, jal_b_19_to_12, jal_b_11, jal_b_10_to_1, jal_b_0};
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assign jal_1_offset = {{11{jal_b_20}}, jal_unsigned_offset};
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assign jalr_immed = {func7, VX_frE_to_bckE_req.rs2};
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assign jal_2_offset = {{20{jalr_immed[11]}}, jalr_immed};
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assign jal_sys_cond1 = func3 == 3'h0;
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assign jal_sys_cond2 = u_12 < 12'h2;
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assign jal_sys_jal = (jal_sys_cond1 && jal_sys_cond2) ? 1'b1 : 1'b0;
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assign jal_sys_off = (jal_sys_cond1 && jal_sys_cond2) ? 32'hb0000000 : 32'hdeadbeef;
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// JAL
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always @(*) begin
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case(curr_opcode)
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`JAL_INST:
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begin
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temp_jal = 1'b1 && (|in_valid);
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temp_jal_offset = jal_1_offset;
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end
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`JALR_INST:
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begin
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temp_jal = 1'b1 && (|in_valid);
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temp_jal_offset = jal_2_offset;
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end
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`SYS_INST:
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begin
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// $display("SYS EBREAK %h", (jal_sys_jal && (|in_valid)) );
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temp_jal = jal_sys_jal && (|in_valid);
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temp_jal_offset = jal_sys_off;
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end
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default:
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begin
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temp_jal = 1'b0 && (|in_valid);
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temp_jal_offset = 32'hdeadbeef;
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end
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endcase
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end
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assign VX_frE_to_bckE_req.jalQual = is_jal;
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assign VX_frE_to_bckE_req.jal = temp_jal;
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assign VX_frE_to_bckE_req.jal_offset = temp_jal_offset;
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// wire is_ebreak;
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// assign is_ebreak = is_e_inst;
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wire ebreak = (curr_opcode == `SYS_INST) && (jal_sys_jal && (|in_valid));
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assign VX_frE_to_bckE_req.ebreak = ebreak;
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wire out_ebreak = ebreak;
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assign terminate_sim = is_e_inst;
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// CSR
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assign csr_cond1 = func3 != 3'h0;
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assign csr_cond2 = u_12 >= 12'h2;
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assign VX_frE_to_bckE_req.csr_address = (csr_cond1 && csr_cond2) ? u_12 : 12'h55;
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// ITYPE IMEED
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assign alu_shift_i = (func3 == 3'h1) || (func3 == 3'h5);
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assign alu_shift_i_immed = {{7{1'b0}}, VX_frE_to_bckE_req.rs2};
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assign alu_tempp = alu_shift_i ? alu_shift_i_immed : u_12;
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always @(*) begin
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case(curr_opcode)
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`ALU_INST: temp_itype_immed = {{20{alu_tempp[11]}}, alu_tempp};
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`S_INST: temp_itype_immed = {{20{func7[6]}}, func7, VX_frE_to_bckE_req.rd};
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`L_INST: temp_itype_immed = {{20{u_12[11]}}, u_12};
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`B_INST: temp_itype_immed = {{20{in_instruction[31]}}, in_instruction[31], in_instruction[7], in_instruction[30:25], in_instruction[11:8]};
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default: temp_itype_immed = 32'hdeadbeef;
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endcase
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end
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assign VX_frE_to_bckE_req.itype_immed = temp_itype_immed;
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always @(*) begin
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case(curr_opcode)
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`B_INST:
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begin
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// $display("BRANCH IN DECODE");
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temp_branch_stall = 1'b1 && (|in_valid);
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case(func3)
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3'h0: temp_branch_type = `BEQ;
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3'h1: temp_branch_type = `BNE;
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3'h4: temp_branch_type = `BLT;
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3'h5: temp_branch_type = `BGT;
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3'h6: temp_branch_type = `BLTU;
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3'h7: temp_branch_type = `BGTU;
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default: temp_branch_type = `NO_BRANCH;
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endcase
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end
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`JAL_INST:
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begin
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temp_branch_type = `NO_BRANCH;
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temp_branch_stall = 1'b1 && (|in_valid);
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end
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`JALR_INST:
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begin
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temp_branch_type = `NO_BRANCH;
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temp_branch_stall = 1'b1 && (|in_valid);
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end
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default:
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begin
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temp_branch_type = `NO_BRANCH;
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temp_branch_stall = 1'b0 && (|in_valid);
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end
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endcase
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end
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assign VX_frE_to_bckE_req.branch_type = temp_branch_type;
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assign VX_wstall.wstall = (temp_branch_stall || is_tmc || is_split || is_barrier) && (|in_valid);
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assign VX_wstall.warp_num = in_warp_num;
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always @(*) begin
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// ALU OP
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case(func3)
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3'h0: alu_op = (curr_opcode == `ALU_INST) ? `ADD : (func7 == 7'h0 ? `ADD : `SUB);
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3'h1: alu_op = `SLLA;
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3'h2: alu_op = `SLT;
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3'h3: alu_op = `SLTU;
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3'h4: alu_op = `XOR;
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3'h5: alu_op = (func7 == 7'h0) ? `SRL : `SRA;
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3'h6: alu_op = `OR;
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3'h7: alu_op = `AND;
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default: alu_op = `NO_ALU;
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endcase
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end
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always @(*) begin
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// ALU OP
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case(func3)
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3'h0: mul_alu = `MUL;
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3'h1: mul_alu = `MULH;
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3'h2: mul_alu = `MULHSU;
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3'h3: mul_alu = `MULHU;
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3'h4: mul_alu = `DIV;
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3'h5: mul_alu = `DIVU;
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3'h6: mul_alu = `REM;
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3'h7: mul_alu = `REMU;
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default: mul_alu = `NO_ALU;
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endcase
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end
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assign csr_type = func3[1:0];
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always @(*) begin
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case(csr_type)
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2'h1: csr_alu = `CSR_ALU_RW;
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2'h2: csr_alu = `CSR_ALU_RS;
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2'h3: csr_alu = `CSR_ALU_RC;
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default: csr_alu = `NO_ALU;
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endcase
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end
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wire[4:0] temp_final_alu;
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assign temp_final_alu = is_btype ? ((VX_frE_to_bckE_req.branch_type < `BLTU) ? `SUB : `SUBU) :
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is_lui ? `LUI_ALU :
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is_auipc ? `AUIPC_ALU :
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is_csr ? csr_alu :
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(is_stype || is_linst) ? `ADD :
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alu_op;
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assign VX_frE_to_bckE_req.alu_op = ((func7[0] == 1'b1) && is_rtype) ? mul_alu : temp_final_alu;
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endmodule
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