85 lines
3.1 KiB
Systemverilog
85 lines
3.1 KiB
Systemverilog
`include "VX_define.vh"
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module VX_scoreboard #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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VX_ibuffer_if.slave ibuffer_if,
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VX_writeback_if.slave writeback_if
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);
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reg [`NUM_WARPS-1:0][`NUM_REGS-1:0] inuse_regs, inuse_regs_n;
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wire reserve_reg = ibuffer_if.valid && ibuffer_if.ready && ibuffer_if.wb;
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wire release_reg = writeback_if.valid && writeback_if.ready && writeback_if.eop;
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always @(*) begin
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inuse_regs_n = inuse_regs;
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if (reserve_reg) begin
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inuse_regs_n[ibuffer_if.wid][ibuffer_if.rd] = 1;
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end
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if (release_reg) begin
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inuse_regs_n[writeback_if.wid][writeback_if.rd] = 0;
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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inuse_regs <= '0;
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end else begin
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inuse_regs <= inuse_regs_n;
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end
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end
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reg deq_inuse_rd, deq_inuse_rs1, deq_inuse_rs2, deq_inuse_rs3;
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always @(posedge clk) begin
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deq_inuse_rd <= inuse_regs_n[ibuffer_if.wid_n][ibuffer_if.rd_n];
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deq_inuse_rs1 <= inuse_regs_n[ibuffer_if.wid_n][ibuffer_if.rs1_n];
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deq_inuse_rs2 <= inuse_regs_n[ibuffer_if.wid_n][ibuffer_if.rs2_n];
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deq_inuse_rs3 <= inuse_regs_n[ibuffer_if.wid_n][ibuffer_if.rs3_n];
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end
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assign writeback_if.ready = 1'b1;
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assign ibuffer_if.ready = ~(deq_inuse_rd
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| deq_inuse_rs1
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| deq_inuse_rs2
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| deq_inuse_rs3);
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`UNUSED_VAR (writeback_if.PC)
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reg [31:0] deadlock_ctr;
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wire [31:0] deadlock_timeout = 10000 * (1 ** (`L2_ENABLE + `L3_ENABLE));
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always @(posedge clk) begin
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if (reset) begin
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deadlock_ctr <= 0;
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end else begin
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`ifdef DBG_TRACE_PIPELINE
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if (ibuffer_if.valid && ~ibuffer_if.ready) begin
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dpi_trace("%d: *** core%0d-stall: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b\n",
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$time, CORE_ID, ibuffer_if.wid, ibuffer_if.PC, ibuffer_if.rd, ibuffer_if.wb,
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deq_inuse_rd, deq_inuse_rs1, deq_inuse_rs2, deq_inuse_rs3);
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end
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`endif
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if (release_reg) begin
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`ASSERT(inuse_regs[writeback_if.wid][writeback_if.rd] != 0,
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("%t: *** core%0d: invalid writeback register: wid=%0d, PC=%0h, rd=%0d",
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$time, CORE_ID, writeback_if.wid, writeback_if.PC, writeback_if.rd));
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end
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if (ibuffer_if.valid && ~ibuffer_if.ready) begin
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deadlock_ctr <= deadlock_ctr + 1;
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`ASSERT(deadlock_ctr < deadlock_timeout,
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("%t: *** core%0d-deadlock: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b",
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$time, CORE_ID, ibuffer_if.wid, ibuffer_if.PC, ibuffer_if.rd, ibuffer_if.wb,
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deq_inuse_rd, deq_inuse_rs1, deq_inuse_rs2, deq_inuse_rs3));
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end else if (ibuffer_if.valid && ibuffer_if.ready) begin
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deadlock_ctr <= 0;
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end
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end
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end
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endmodule |