82 lines
1.8 KiB
Systemverilog
82 lines
1.8 KiB
Systemverilog
`ifndef VX_IBUFFER_IF
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`define VX_IBUFFER_IF
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`include "VX_define.vh"
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interface VX_ibuffer_if ();
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wire valid;
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wire [`NW_BITS-1:0] wid;
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wire [`NUM_THREADS-1:0] tmask;
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wire [31:0] PC;
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wire [`EX_BITS-1:0] ex_type;
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wire [`INST_OP_BITS-1:0] op_type;
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wire [`INST_MOD_BITS-1:0] op_mod;
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wire wb;
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wire use_PC;
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wire use_imm;
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wire [31:0] imm;
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wire [`NR_BITS-1:0] rd;
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wire [`NR_BITS-1:0] rs1;
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wire [`NR_BITS-1:0] rs2;
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wire [`NR_BITS-1:0] rs3;
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wire [`NR_BITS-1:0] rd_n;
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wire [`NR_BITS-1:0] rs1_n;
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wire [`NR_BITS-1:0] rs2_n;
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wire [`NR_BITS-1:0] rs3_n;
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wire [`NW_BITS-1:0] wid_n;
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wire ready;
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modport master (
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output valid,
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output wid,
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output tmask,
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output PC,
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output ex_type,
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output op_type,
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output op_mod,
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output wb,
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output use_PC,
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output use_imm,
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output imm,
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output rd,
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output rs1,
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output rs2,
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output rs3,
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output rd_n,
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output rs1_n,
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output rs2_n,
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output rs3_n,
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output wid_n,
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input ready
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);
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modport slave (
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input valid,
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input wid,
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input tmask,
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input PC,
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input ex_type,
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input op_type,
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input op_mod,
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input wb,
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input use_PC,
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input use_imm,
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input imm,
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input rd,
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input rs1,
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input rs2,
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input rs3,
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input rd_n,
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input rs1_n,
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input rs2_n,
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input rs3_n,
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input wid_n,
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output ready
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);
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endinterface
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`endif |