127 lines
4.1 KiB
Verilog
127 lines
4.1 KiB
Verilog
`include "VX_define.vh"
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module VX_mul_unit #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// Inputs
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VX_mul_req_if mul_req_if,
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// Outputs
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VX_commit_if mul_commit_if
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);
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reg [`NUM_THREADS-1:0][31:0] alu_result;
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wire [`NUM_THREADS-1:0][63:0] mul_result;
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wire [`NUM_THREADS-1:0][31:0] div_result;
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wire [`NUM_THREADS-1:0][31:0] rem_result;
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wire [`MUL_BITS-1:0] alu_op = mul_req_if.mul_op;
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wire [`NUM_THREADS-1:0][31:0] alu_in1 = mul_req_if.rs1_data;
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wire [`NUM_THREADS-1:0][31:0] alu_in2 = mul_req_if.rs2_data;
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genvar i;
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for (i = 0; i < `NUM_THREADS; i++) begin
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wire [32:0] mul_in1 = {(alu_op != `MUL_MULHU) & alu_in1[i][31], alu_in1[i]};
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wire [32:0] mul_in2 = {(alu_op != `MUL_MULHU && alu_op != `MUL_MULHSU) & alu_in2[i][31], alu_in2[i]};
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wire [32:0] div_in1 = {(alu_op == `MUL_DIV || alu_op == `MUL_REM) & alu_in1[i][31], alu_in1[i]};
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wire [32:0] div_in2 = {(alu_op == `MUL_DIV || alu_op == `MUL_REM) & alu_in2[i][31], alu_in2[i]};
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VX_mult #(
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.WIDTHA(33),
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.WIDTHB(33),
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.WIDTHP(64),
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.SIGNED(1),
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.PIPELINE(`MUL_LATENCY)
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) multiplier (
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.clk(clk),
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.reset(reset),
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.dataa(mul_in1),
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.datab(mul_in2),
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.result(mul_result[i])
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);
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VX_divide #(
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.WIDTHN(33),
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.WIDTHD(33),
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.WIDTHQ(32),
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.WIDTHR(32),
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.NSIGNED(1),
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.DSIGNED(1),
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.PIPELINE(`DIV_LATENCY)
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) sdiv (
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.clk(clk),
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.reset(reset),
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.numer(div_in1),
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.denom(div_in2),
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.quotient(div_result[i]),
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.remainder(rem_result[i])
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);
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always @(*) begin
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case (alu_op)
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`MUL_MUL: alu_result[i] = mul_result[i][31:0];
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`MUL_MULH,
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`MUL_MULHSU,
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`MUL_MULHU: alu_result[i] = mul_result[i][63:32];
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`MUL_DIV,
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`MUL_DIVU: alu_result[i] = (alu_in2[i] == 0) ? 32'hffffffff : div_result[i];
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`MUL_REM,
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`MUL_REMU: alu_result[i] = (alu_in2[i] == 0) ? alu_in1[i] : rem_result[i];
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default: alu_result[i] = alu_in1[i] + alu_in2[i]; // ADD, LUI, AUIPC, FENCE
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endcase
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end
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end
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wire stall;
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reg result_avail;
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reg [4:0] pending_ctr;
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wire [4:0] instr_delay = `IS_DIV_OP(alu_op) ? `DIV_LATENCY : `MUL_LATENCY;
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always @(posedge clk) begin
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if (reset) begin
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result_avail <= 0;
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pending_ctr <= 0;
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end else begin
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if (result_avail && !stall) begin
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result_avail <= 0;
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pending_ctr <= 0;
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end
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if ((| mul_req_if.valid) && (pending_ctr == 0)) begin
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pending_ctr <= instr_delay - 1;
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if (instr_delay == 1)
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result_avail <= 1;
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end else if (pending_ctr != 0) begin
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pending_ctr <= pending_ctr - 1;
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if (pending_ctr == 1)
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result_avail <= 1;
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end
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end
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end
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wire pipeline_stall = ~result_avail && (| mul_req_if.valid);
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assign stall = (~mul_commit_if.ready && (| mul_commit_if.valid))
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|| pipeline_stall;
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wire flush = mul_commit_if.ready && pipeline_stall;
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VX_generic_register #(
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.N(`NUM_THREADS + `NW_BITS + 32 + `NR_BITS + `WB_BITS + (`NUM_THREADS * 32))
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) mul_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall),
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.flush (flush),
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.in ({mul_req_if.valid, mul_req_if.warp_num, mul_req_if.curr_PC, mul_req_if.rd, mul_req_if.wb, alu_result}),
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.out ({mul_commit_if.valid, mul_commit_if.warp_num, mul_commit_if.curr_PC, mul_commit_if.rd, mul_commit_if.wb, mul_commit_if.data})
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);
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assign mul_req_if.ready = ~stall;
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endmodule |