Some bugs need to be fixed.

2024-12-29 16:20:43 +08:00
parent 320f71ac96
commit 582917df99
27 changed files with 1106 additions and 536 deletions
--- a/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir
+++ b/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir
@ -0,0 +1,480 @@
+FIRRTL version 1.2.0
+circuit TopOrigin :
+  module Core : @[src/main/scala/micore/Core.scala 8:7]
+    input clock : Clock @[src/main/scala/micore/Core.scala 8:7]
+    input reset : UInt<1> @[src/main/scala/micore/Core.scala 8:7]
+    output io_imem_addr : UInt<32> @[src/main/scala/micore/Core.scala 9:14]
+    input io_imem_inst : UInt<32> @[src/main/scala/micore/Core.scala 9:14]
+    output io_dmem_addr : UInt<32> @[src/main/scala/micore/Core.scala 9:14]
+    input io_dmem_rdata : UInt<32> @[src/main/scala/micore/Core.scala 9:14]
+    output io_dmem_wen : UInt<1> @[src/main/scala/micore/Core.scala 9:14]
+    output io_dmem_wdata : UInt<32> @[src/main/scala/micore/Core.scala 9:14]
+    output io_exit : UInt<1> @[src/main/scala/micore/Core.scala 9:14]
+
+    mem regfile : @[src/main/scala/micore/Core.scala 16:28]
+      data-type => UInt<32>
+      depth => 32
+      read-latency => 1
+      write-latency => 1
+      reader => id_rs1_data_MPORT
+      reader => id_rs2_data_MPORT
+      writer => MPORT
+      read-under-write => undefined
+    reg id_reg_pc : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), id_reg_pc) @[src/main/scala/micore/Core.scala 19:19]
+    reg id_reg_inst : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), id_reg_inst) @[src/main/scala/micore/Core.scala 19:19]
+    reg exe_reg_pc : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_pc) @[src/main/scala/micore/Core.scala 24:20]
+    reg exe_reg_wb_addr : UInt<5>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 24:20]
+    reg exe_reg_op1_data : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_op1_data) @[src/main/scala/micore/Core.scala 24:20]
+    reg exe_reg_op2_data : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_op2_data) @[src/main/scala/micore/Core.scala 24:20]
+    reg exe_reg_rs2_data : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_rs2_data) @[src/main/scala/micore/Core.scala 24:20]
+    reg exe_reg_exe_fun : UInt<5>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 24:20]
+    reg exe_reg_mem_wen : UInt<2>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 24:20]
+    reg exe_reg_rf_wen : UInt<2>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 24:20]
+    reg exe_reg_wb_sel : UInt<3>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 24:20]
+    reg exe_reg_imm_b_sext : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_imm_b_sext) @[src/main/scala/micore/Core.scala 24:20]
+    reg mem_reg_pc : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), mem_reg_pc) @[src/main/scala/micore/Core.scala 37:20]
+    reg mem_reg_wb_addr : UInt<5>, clock with :
+      reset => (UInt<1>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 37:20]
+    reg mem_reg_alu_out : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), mem_reg_alu_out) @[src/main/scala/micore/Core.scala 37:20]
+    reg mem_reg_rs2_data : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), mem_reg_rs2_data) @[src/main/scala/micore/Core.scala 37:20]
+    reg mem_reg_rf_wen : UInt<2>, clock with :
+      reset => (UInt<1>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 37:20]
+    reg mem_reg_wb_sel : UInt<3>, clock with :
+      reset => (UInt<1>("h0"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 37:20]
+    reg mem_reg_mem_wen : UInt<2>, clock with :
+      reset => (UInt<1>("h0"), mem_reg_mem_wen) @[src/main/scala/micore/Core.scala 37:20]
+    reg wb_reg_wb_addr : UInt<5>, clock with :
+      reset => (UInt<1>("h0"), wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 47:19]
+    reg wb_reg_rf_wen : UInt<2>, clock with :
+      reset => (UInt<1>("h0"), wb_reg_rf_wen) @[src/main/scala/micore/Core.scala 47:19]
+    reg wb_reg_wb_data : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), wb_reg_wb_data) @[src/main/scala/micore/Core.scala 47:19]
+    reg if_reg_pc : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), if_reg_pc) @[src/main/scala/micore/Core.scala 54:26]
+    node _if_pc_plus4_T = add(if_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 64:31]
+    node if_pc_plus4 = tail(_if_pc_plus4_T, 1) @[src/main/scala/micore/Core.scala 64:31]
+    node _id_rs1_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 92:21]
+    node id_rs1_addr = bits(id_reg_inst, 25, 21) @[src/main/scala/micore/Core.scala 86:32]
+    node _id_rs1_data_hazard_T_1 = neq(id_rs1_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 92:48]
+    node _id_rs1_data_hazard_T_2 = and(_id_rs1_data_hazard_T, _id_rs1_data_hazard_T_1) @[src/main/scala/micore/Core.scala 92:32]
+    node _id_rs1_data_hazard_T_3 = eq(id_rs1_addr, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 92:73]
+    node id_rs1_data_hazard = and(_id_rs1_data_hazard_T_2, _id_rs1_data_hazard_T_3) @[src/main/scala/micore/Core.scala 92:57]
+    node _id_rs2_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 94:21]
+    node id_rs2_addr = bits(id_reg_inst, 20, 16) @[src/main/scala/micore/Core.scala 87:32]
+    node _id_rs2_data_hazard_T_1 = neq(id_rs2_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 94:48]
+    node _id_rs2_data_hazard_T_2 = and(_id_rs2_data_hazard_T, _id_rs2_data_hazard_T_1) @[src/main/scala/micore/Core.scala 94:32]
+    node _id_rs2_data_hazard_T_3 = eq(id_rs2_addr, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 94:73]
+    node id_rs2_data_hazard = and(_id_rs2_data_hazard_T_2, _id_rs2_data_hazard_T_3) @[src/main/scala/micore/Core.scala 94:57]
+    node _stall_flg_T = or(id_rs1_data_hazard, id_rs2_data_hazard) @[src/main/scala/micore/Core.scala 95:36]
+    node stall_flg = _stall_flg_T @[src/main/scala/micore/Core.scala 58:23 95:13]
+    node _if_pc_next_T = mux(stall_flg, if_reg_pc, if_pc_plus4) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_jmp_flg_T = eq(exe_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 222:34]
+    node exe_jmp_flg = _exe_jmp_flg_T @[src/main/scala/micore/Core.scala 222:15 61:25]
+    node _exe_alu_out_T_37 = eq(UInt<5>("he"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4]
+    node _exe_alu_out_T_35 = eq(UInt<5>("h9"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4]
+    node _exe_alu_out_T_16 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 206:36]
+    node _exe_alu_out_T_17 = asSInt(exe_reg_op2_data) @[src/main/scala/micore/Core.scala 206:62]
+    node _exe_alu_out_T_18 = lt(_exe_alu_out_T_16, _exe_alu_out_T_17) @[src/main/scala/micore/Core.scala 206:43]
+    node _exe_alu_out_T_33 = eq(UInt<5>("h8"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4]
+    node _exe_alu_out_T_12 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 205:36]
+    node _exe_alu_out_T_13 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 205:62]
+    node _exe_alu_out_T_14 = dshr(_exe_alu_out_T_12, _exe_alu_out_T_13) @[src/main/scala/micore/Core.scala 205:43]
+    node _exe_alu_out_T_15 = asUInt(_exe_alu_out_T_14) @[src/main/scala/micore/Core.scala 205:70]
+    node _exe_alu_out_T_31 = eq(UInt<5>("h7"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4]
+    node _exe_alu_out_T_10 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 204:55]
+    node _exe_alu_out_T_11 = dshr(exe_reg_op1_data, _exe_alu_out_T_10) @[src/main/scala/micore/Core.scala 204:36]
+    node _exe_alu_out_T_29 = eq(UInt<5>("h6"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4]
+    node _exe_alu_out_T_7 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 203:55]
+    node _exe_alu_out_T_8 = dshl(exe_reg_op1_data, _exe_alu_out_T_7) @[src/main/scala/micore/Core.scala 203:36]
+    node _exe_alu_out_T_9 = bits(_exe_alu_out_T_8, 31, 0) @[src/main/scala/micore/Core.scala 203:62]
+    node _exe_alu_out_T_27 = eq(UInt<5>("h5"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4]
+    node _exe_alu_out_T_6 = xor(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 202:36]
+    node _exe_alu_out_T_25 = eq(UInt<5>("h4"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4]
+    node _exe_alu_out_T_5 = or(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 201:35]
+    node _exe_alu_out_T_23 = eq(UInt<5>("h3"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4]
+    node _exe_alu_out_T_4 = and(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 200:36]
+    node _exe_alu_out_T_21 = eq(UInt<5>("h2"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4]
+    node _exe_alu_out_T_2 = sub(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 199:36]
+    node _exe_alu_out_T_3 = tail(_exe_alu_out_T_2, 1) @[src/main/scala/micore/Core.scala 199:36]
+    node _exe_alu_out_T_19 = eq(UInt<5>("h1"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4]
+    node _exe_alu_out_T = add(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 198:36]
+    node _exe_alu_out_T_1 = tail(_exe_alu_out_T, 1) @[src/main/scala/micore/Core.scala 198:36]
+    node _exe_alu_out_T_20 = mux(_exe_alu_out_T_19, _exe_alu_out_T_1, UInt<32>("h0")) @[src/main/scala/micore/Core.scala 196:4]
+    node _exe_alu_out_T_22 = mux(_exe_alu_out_T_21, _exe_alu_out_T_3, _exe_alu_out_T_20) @[src/main/scala/micore/Core.scala 196:4]
+    node _exe_alu_out_T_24 = mux(_exe_alu_out_T_23, _exe_alu_out_T_4, _exe_alu_out_T_22) @[src/main/scala/micore/Core.scala 196:4]
+    node _exe_alu_out_T_26 = mux(_exe_alu_out_T_25, _exe_alu_out_T_5, _exe_alu_out_T_24) @[src/main/scala/micore/Core.scala 196:4]
+    node _exe_alu_out_T_28 = mux(_exe_alu_out_T_27, _exe_alu_out_T_6, _exe_alu_out_T_26) @[src/main/scala/micore/Core.scala 196:4]
+    node _exe_alu_out_T_30 = mux(_exe_alu_out_T_29, _exe_alu_out_T_9, _exe_alu_out_T_28) @[src/main/scala/micore/Core.scala 196:4]
+    node _exe_alu_out_T_32 = mux(_exe_alu_out_T_31, _exe_alu_out_T_11, _exe_alu_out_T_30) @[src/main/scala/micore/Core.scala 196:4]
+    node _exe_alu_out_T_34 = mux(_exe_alu_out_T_33, _exe_alu_out_T_15, _exe_alu_out_T_32) @[src/main/scala/micore/Core.scala 196:4]
+    node _exe_alu_out_T_36 = mux(_exe_alu_out_T_35, _exe_alu_out_T_18, _exe_alu_out_T_34) @[src/main/scala/micore/Core.scala 196:4]
+    node _exe_alu_out_T_38 = mux(_exe_alu_out_T_37, exe_reg_op1_data, _exe_alu_out_T_36) @[src/main/scala/micore/Core.scala 196:4]
+    node exe_alu_out = _exe_alu_out_T_38 @[src/main/scala/micore/Core.scala 193:15 62:25]
+    node _if_pc_next_T_1 = mux(exe_jmp_flg, exe_alu_out, _if_pc_next_T) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_br_flg_T_4 = eq(UInt<5>("hc"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 214:4]
+    node _exe_br_flg_T_1 = neq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 217:35]
+    node _exe_br_flg_T_2 = eq(UInt<5>("hb"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 214:4]
+    node _exe_br_flg_T = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 216:35]
+    node _exe_br_flg_T_3 = mux(_exe_br_flg_T_2, _exe_br_flg_T, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 214:4]
+    node _exe_br_flg_T_5 = mux(_exe_br_flg_T_4, _exe_br_flg_T_1, _exe_br_flg_T_3) @[src/main/scala/micore/Core.scala 214:4]
+    node exe_br_flg = _exe_br_flg_T_5 @[src/main/scala/micore/Core.scala 211:14 59:24]
+    node _exe_br_target_T = add(exe_reg_pc, exe_reg_imm_b_sext) @[src/main/scala/micore/Core.scala 221:31]
+    node _exe_br_target_T_1 = tail(_exe_br_target_T, 1) @[src/main/scala/micore/Core.scala 221:31]
+    node exe_br_target = _exe_br_target_T_1 @[src/main/scala/micore/Core.scala 221:17 60:27]
+    node if_pc_next = mux(exe_br_flg, exe_br_target, _if_pc_next_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _id_reg_pc_T = mux(stall_flg, id_reg_pc, if_reg_pc) @[src/main/scala/micore/Core.scala 76:19]
+    node _id_reg_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 80:19]
+    node _id_reg_inst_T_1 = mux(stall_flg, id_reg_inst, io_imem_inst) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _id_reg_inst_T_2 = mux(_id_reg_inst_T, UInt<32>("h0"), _id_reg_inst_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node id_wb_addr = bits(id_reg_inst, 15, 11) @[src/main/scala/micore/Core.scala 88:31]
+    node _id_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 98:21]
+    node _id_inst_T_1 = or(_id_inst_T, stall_flg) @[src/main/scala/micore/Core.scala 98:36]
+    node id_inst = mux(_id_inst_T_1, UInt<32>("h0"), id_reg_inst) @[src/main/scala/micore/Core.scala 98:8]
+    node _id_rs1_data_T = eq(id_rs1_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 101:17]
+    node _id_rs1_data_T_1 = eq(id_rs1_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 104:20]
+    node _id_rs1_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 104:60]
+    node _id_rs1_data_T_3 = and(_id_rs1_data_T_1, _id_rs1_data_T_2) @[src/main/scala/micore/Core.scala 104:41]
+    node _id_rs1_data_T_4 = eq(id_rs1_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 107:22]
+    node _id_rs1_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 107:60]
+    node _id_rs1_data_T_6 = and(_id_rs1_data_T_4, _id_rs1_data_T_5) @[src/main/scala/micore/Core.scala 107:42]
+    node _id_rs1_data_T_7 = mux(_id_rs1_data_T_6, wb_reg_wb_data, regfile.id_rs1_data_MPORT.data) @[src/main/scala/micore/Core.scala 106:10]
+    node _id_rs1_data_T_8 = mux(_id_rs1_data_T_3, mem_reg_alu_out, _id_rs1_data_T_7) @[src/main/scala/micore/Core.scala 103:8]
+    node id_rs1_data = mux(_id_rs1_data_T, UInt<32>("h0"), _id_rs1_data_T_8) @[src/main/scala/micore/Core.scala 100:24]
+    node _id_rs2_data_T = eq(id_rs2_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 114:17]
+    node _id_rs2_data_T_1 = eq(id_rs2_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 117:20]
+    node _id_rs2_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 117:60]
+    node _id_rs2_data_T_3 = and(_id_rs2_data_T_1, _id_rs2_data_T_2) @[src/main/scala/micore/Core.scala 117:41]
+    node _id_rs2_data_T_4 = eq(id_rs2_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 120:22]
+    node _id_rs2_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 120:60]
+    node _id_rs2_data_T_6 = and(_id_rs2_data_T_4, _id_rs2_data_T_5) @[src/main/scala/micore/Core.scala 120:42]
+    node _id_rs2_data_T_7 = mux(_id_rs2_data_T_6, wb_reg_wb_data, regfile.id_rs2_data_MPORT.data) @[src/main/scala/micore/Core.scala 119:10]
+    node _id_rs2_data_T_8 = mux(_id_rs2_data_T_3, mem_reg_alu_out, _id_rs2_data_T_7) @[src/main/scala/micore/Core.scala 116:8]
+    node id_rs2_data = mux(_id_rs2_data_T, UInt<32>("h0"), _id_rs2_data_T_8) @[src/main/scala/micore/Core.scala 113:24]
+    node _id_imm_i_sext_T = bits(id_inst, 15, 15) @[src/main/scala/micore/Core.scala 128:43]
+    node _id_imm_i_sext_T_1 = mux(_id_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 128:31]
+    node _id_imm_i_sext_T_2 = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 128:57]
+    node id_imm_i_sext = cat(_id_imm_i_sext_T_1, _id_imm_i_sext_T_2) @[src/main/scala/micore/Core.scala 128:26]
+    node _id_imm_b_sext_T = bits(id_inst, 15, 15) @[src/main/scala/micore/Core.scala 129:43]
+    node _id_imm_b_sext_T_1 = mux(_id_imm_b_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 129:31]
+    node _id_imm_b_sext_T_2 = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 129:57]
+    node id_imm_b_sext = cat(_id_imm_b_sext_T_1, _id_imm_b_sext_T_2) @[src/main/scala/micore/Core.scala 129:26]
+    node _csignals_T = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_1 = eq(UInt<34>("h230000000"), _csignals_T) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_2 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_3 = eq(UInt<34>("h2b0000000"), _csignals_T_2) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_4 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_5 = eq(UInt<6>("h20"), _csignals_T_4) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_6 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_7 = eq(UInt<32>("h80000000"), _csignals_T_6) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_8 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_9 = eq(UInt<6>("h22"), _csignals_T_8) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_10 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_11 = eq(UInt<6>("h24"), _csignals_T_10) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_12 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_13 = eq(UInt<6>("h25"), _csignals_T_12) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_14 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_15 = eq(UInt<6>("h26"), _csignals_T_14) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_16 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_17 = eq(UInt<32>("hc0000000"), _csignals_T_16) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_18 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_19 = eq(UInt<32>("hd0000000"), _csignals_T_18) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_20 = and(id_inst, UInt<31>("h7ff0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_21 = eq(UInt<1>("h0"), _csignals_T_20) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_22 = and(id_inst, UInt<31>("h7ff0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_23 = eq(UInt<2>("h2"), _csignals_T_22) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_24 = and(id_inst, UInt<31>("h7ff0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_25 = eq(UInt<2>("h3"), _csignals_T_24) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_26 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_27 = eq(UInt<6>("h2a"), _csignals_T_26) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_28 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_29 = eq(UInt<31>("h40000000"), _csignals_T_28) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_30 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_31 = eq(UInt<31>("h50000000"), _csignals_T_30) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_32 = and(id_inst, UInt<32>("hffffffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_33 = eq(UInt<28>("hc000000"), _csignals_T_32) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_34 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_35 = eq(UInt<4>("h8"), _csignals_T_34) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_36 = and(id_inst, UInt<33>("h1ffc003ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_37 = eq(UInt<31>("h78000000"), _csignals_T_36) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_38 = and(id_inst, UInt<33>("h1ffffffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_39 = eq(UInt<1>("h0"), _csignals_T_38) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_40 = mux(_csignals_T_39, UInt<5>("h0"), UInt<5>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_41 = mux(_csignals_T_37, UInt<5>("h1"), _csignals_T_40) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_42 = mux(_csignals_T_35, UInt<5>("he"), _csignals_T_41) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_43 = mux(_csignals_T_33, UInt<5>("h1"), _csignals_T_42) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_44 = mux(_csignals_T_31, UInt<5>("hc"), _csignals_T_43) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_45 = mux(_csignals_T_29, UInt<5>("hb"), _csignals_T_44) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_46 = mux(_csignals_T_27, UInt<5>("h9"), _csignals_T_45) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_47 = mux(_csignals_T_25, UInt<5>("h8"), _csignals_T_46) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_48 = mux(_csignals_T_23, UInt<5>("h7"), _csignals_T_47) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_49 = mux(_csignals_T_21, UInt<5>("h6"), _csignals_T_48) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_50 = mux(_csignals_T_19, UInt<5>("h4"), _csignals_T_49) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_51 = mux(_csignals_T_17, UInt<5>("h3"), _csignals_T_50) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_52 = mux(_csignals_T_15, UInt<5>("h5"), _csignals_T_51) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_53 = mux(_csignals_T_13, UInt<5>("h4"), _csignals_T_52) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_54 = mux(_csignals_T_11, UInt<5>("h3"), _csignals_T_53) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_55 = mux(_csignals_T_9, UInt<5>("h2"), _csignals_T_54) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_56 = mux(_csignals_T_7, UInt<5>("h1"), _csignals_T_55) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_57 = mux(_csignals_T_5, UInt<5>("h1"), _csignals_T_56) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_58 = mux(_csignals_T_3, UInt<5>("h1"), _csignals_T_57) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node csignals_0 = mux(_csignals_T_1, UInt<5>("h1"), _csignals_T_58) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_59 = mux(_csignals_T_39, UInt<2>("h2"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_60 = mux(_csignals_T_37, UInt<2>("h2"), _csignals_T_59) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_61 = mux(_csignals_T_35, UInt<2>("h0"), _csignals_T_60) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_62 = mux(_csignals_T_33, UInt<2>("h1"), _csignals_T_61) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_63 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_62) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_64 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_63) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_65 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_64) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_66 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_65) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_67 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_66) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_68 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_67) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_69 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_68) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_70 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_69) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_71 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_70) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_72 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_71) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_73 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_72) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_74 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_73) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_75 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_74) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_76 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_75) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_77 = mux(_csignals_T_3, UInt<2>("h0"), _csignals_T_76) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node csignals_1 = mux(_csignals_T_1, UInt<2>("h0"), _csignals_T_77) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_78 = mux(_csignals_T_39, UInt<3>("h0"), UInt<3>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_79 = mux(_csignals_T_37, UInt<3>("h5"), _csignals_T_78) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_80 = mux(_csignals_T_35, UInt<3>("h0"), _csignals_T_79) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_81 = mux(_csignals_T_33, UInt<3>("h4"), _csignals_T_80) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_82 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_81) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_83 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_82) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_84 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_83) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_85 = mux(_csignals_T_25, UInt<3>("h1"), _csignals_T_84) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_86 = mux(_csignals_T_23, UInt<3>("h1"), _csignals_T_85) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_87 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_86) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_88 = mux(_csignals_T_19, UInt<3>("h2"), _csignals_T_87) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_89 = mux(_csignals_T_17, UInt<3>("h2"), _csignals_T_88) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_90 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_89) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_91 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_90) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_92 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_91) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_93 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_92) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_94 = mux(_csignals_T_7, UInt<3>("h2"), _csignals_T_93) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_95 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_94) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_96 = mux(_csignals_T_3, UInt<3>("h3"), _csignals_T_95) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node csignals_2 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_96) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_97 = mux(_csignals_T_39, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_98 = mux(_csignals_T_37, UInt<2>("h0"), _csignals_T_97) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_99 = mux(_csignals_T_35, UInt<2>("h0"), _csignals_T_98) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_100 = mux(_csignals_T_33, UInt<2>("h0"), _csignals_T_99) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_101 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_100) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_102 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_101) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_103 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_102) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_104 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_103) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_105 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_104) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_106 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_105) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_107 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_106) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_108 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_107) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_109 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_108) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_110 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_109) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_111 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_110) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_112 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_111) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_113 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_112) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_114 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_113) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_115 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_114) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node csignals_3 = mux(_csignals_T_1, UInt<2>("h0"), _csignals_T_115) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_116 = mux(_csignals_T_39, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_117 = mux(_csignals_T_37, UInt<2>("h1"), _csignals_T_116) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_118 = mux(_csignals_T_35, UInt<2>("h0"), _csignals_T_117) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_119 = mux(_csignals_T_33, UInt<2>("h1"), _csignals_T_118) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_120 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_119) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_121 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_120) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_122 = mux(_csignals_T_27, UInt<2>("h1"), _csignals_T_121) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_123 = mux(_csignals_T_25, UInt<2>("h1"), _csignals_T_122) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_124 = mux(_csignals_T_23, UInt<2>("h1"), _csignals_T_123) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_125 = mux(_csignals_T_21, UInt<2>("h1"), _csignals_T_124) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_126 = mux(_csignals_T_19, UInt<2>("h1"), _csignals_T_125) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_127 = mux(_csignals_T_17, UInt<2>("h1"), _csignals_T_126) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_128 = mux(_csignals_T_15, UInt<2>("h1"), _csignals_T_127) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_129 = mux(_csignals_T_13, UInt<2>("h1"), _csignals_T_128) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_130 = mux(_csignals_T_11, UInt<2>("h1"), _csignals_T_129) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_131 = mux(_csignals_T_9, UInt<2>("h1"), _csignals_T_130) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_132 = mux(_csignals_T_7, UInt<2>("h1"), _csignals_T_131) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_133 = mux(_csignals_T_5, UInt<2>("h1"), _csignals_T_132) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_134 = mux(_csignals_T_3, UInt<2>("h0"), _csignals_T_133) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node csignals_4 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_134) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_135 = mux(_csignals_T_39, UInt<3>("h0"), UInt<3>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_136 = mux(_csignals_T_37, UInt<3>("h1"), _csignals_T_135) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_137 = mux(_csignals_T_35, UInt<3>("h0"), _csignals_T_136) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_138 = mux(_csignals_T_33, UInt<3>("h3"), _csignals_T_137) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_139 = mux(_csignals_T_31, UInt<3>("h0"), _csignals_T_138) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_140 = mux(_csignals_T_29, UInt<3>("h0"), _csignals_T_139) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_141 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_140) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_142 = mux(_csignals_T_25, UInt<3>("h1"), _csignals_T_141) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_143 = mux(_csignals_T_23, UInt<3>("h1"), _csignals_T_142) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_144 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_143) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_145 = mux(_csignals_T_19, UInt<3>("h1"), _csignals_T_144) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_146 = mux(_csignals_T_17, UInt<3>("h1"), _csignals_T_145) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_147 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_146) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_148 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_147) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_149 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_148) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_150 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_149) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_151 = mux(_csignals_T_7, UInt<3>("h1"), _csignals_T_150) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_152 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_151) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_153 = mux(_csignals_T_3, UInt<3>("h0"), _csignals_T_152) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node csignals_5 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_153) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _id_op1_data_T = eq(csignals_1, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 163:16]
+    node _id_op1_data_T_1 = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 165:20]
+    node _id_op1_data_T_2 = mux(_id_op1_data_T_1, id_reg_pc, UInt<32>("h0")) @[src/main/scala/micore/Core.scala 165:8]
+    node id_op1_data = mux(_id_op1_data_T, id_rs1_data, _id_op1_data_T_2) @[src/main/scala/micore/Core.scala 162:24]
+    node _id_op2_data_T = bits(id_inst, 25, 25) @[src/main/scala/micore/Core.scala 175:37]
+    node _id_op2_data_T_1 = mux(_id_op2_data_T, UInt<4>("hf"), UInt<4>("h0")) @[src/main/scala/micore/Core.scala 175:26]
+    node _id_op2_data_T_2 = bits(id_inst, 25, 0) @[src/main/scala/micore/Core.scala 175:51]
+    node id_op2_data_hi = cat(_id_op2_data_T_1, _id_op2_data_T_2) @[src/main/scala/micore/Core.scala 175:21]
+    node _id_op2_data_T_3 = cat(id_op2_data_hi, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 175:21]
+    node _id_op2_data_T_4 = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 176:29]
+    node _id_op2_data_T_5 = mux(UInt<1>("h0"), UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 176:42]
+    node _id_op2_data_T_6 = cat(_id_op2_data_T_4, _id_op2_data_T_5) @[src/main/scala/micore/Core.scala 176:21]
+    node _id_op2_data_T_7 = eq(UInt<3>("h1"), csignals_2) @[src/main/scala/micore/Core.scala 170:4]
+    node _id_op2_data_T_8 = mux(_id_op2_data_T_7, id_rs2_data, UInt<32>("h0")) @[src/main/scala/micore/Core.scala 170:4]
+    node _id_op2_data_T_9 = eq(UInt<3>("h2"), csignals_2) @[src/main/scala/micore/Core.scala 170:4]
+    node _id_op2_data_T_10 = mux(_id_op2_data_T_9, id_imm_i_sext, _id_op2_data_T_8) @[src/main/scala/micore/Core.scala 170:4]
+    node _id_op2_data_T_11 = eq(UInt<3>("h3"), csignals_2) @[src/main/scala/micore/Core.scala 170:4]
+    node _id_op2_data_T_12 = mux(_id_op2_data_T_11, id_imm_i_sext, _id_op2_data_T_10) @[src/main/scala/micore/Core.scala 170:4]
+    node _id_op2_data_T_13 = eq(UInt<3>("h4"), csignals_2) @[src/main/scala/micore/Core.scala 170:4]
+    node _id_op2_data_T_14 = mux(_id_op2_data_T_13, _id_op2_data_T_3, _id_op2_data_T_12) @[src/main/scala/micore/Core.scala 170:4]
+    node _id_op2_data_T_15 = eq(UInt<3>("h5"), csignals_2) @[src/main/scala/micore/Core.scala 170:4]
+    node id_op2_data = mux(_id_op2_data_T_15, _id_op2_data_T_6, _id_op2_data_T_14) @[src/main/scala/micore/Core.scala 170:4]
+    node _mem_wb_data_T = add(mem_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 244:28]
+    node _mem_wb_data_T_1 = tail(_mem_wb_data_T, 1) @[src/main/scala/micore/Core.scala 244:28]
+    node _mem_wb_data_T_2 = eq(UInt<3>("h2"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 241:4]
+    node _mem_wb_data_T_3 = mux(_mem_wb_data_T_2, io_dmem_rdata, mem_reg_alu_out) @[src/main/scala/micore/Core.scala 241:4]
+    node _mem_wb_data_T_4 = eq(UInt<3>("h3"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 241:4]
+    node mem_wb_data = mux(_mem_wb_data_T_4, _mem_wb_data_T_1, _mem_wb_data_T_3) @[src/main/scala/micore/Core.scala 241:4]
+    node _T = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 254:22]
+    node _GEN_0 = validif(_T, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 254:33 255:12]
+    node _GEN_1 = validif(_T, clock) @[src/main/scala/micore/Core.scala 254:33 255:12]
+    node _GEN_2 = mux(_T, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Core.scala 254:33 255:12 16:28]
+    node _GEN_3 = validif(_T, UInt<1>("h1")) @[src/main/scala/micore/Core.scala 254:33 255:29]
+    node _GEN_4 = validif(_T, wb_reg_wb_data) @[src/main/scala/micore/Core.scala 254:33 255:29]
+    node _io_exit_T = eq(id_reg_inst, UInt<32>("hc0000000")) @[src/main/scala/micore/Core.scala 258:27]
+    io_imem_addr <= if_reg_pc @[src/main/scala/micore/Core.scala 55:16]
+    io_dmem_addr <= mem_reg_alu_out @[src/main/scala/micore/Core.scala 234:16]
+    io_dmem_wen <= bits(mem_reg_mem_wen, 0, 0) @[src/main/scala/micore/Core.scala 235:15]
+    io_dmem_wdata <= mem_reg_rs2_data @[src/main/scala/micore/Core.scala 236:17]
+    io_exit <= _io_exit_T @[src/main/scala/micore/Core.scala 258:11]
+    regfile.id_rs1_data_MPORT.addr <= id_rs1_addr @[src/main/scala/micore/Core.scala 109:16]
+    regfile.id_rs1_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 86:32]
+    regfile.id_rs1_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 109:16]
+    regfile.id_rs2_data_MPORT.addr <= id_rs2_addr @[src/main/scala/micore/Core.scala 122:16]
+    regfile.id_rs2_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 87:32]
+    regfile.id_rs2_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 122:16]
+    regfile.MPORT.addr <= _GEN_0
+    regfile.MPORT.en <= _GEN_2
+    regfile.MPORT.clk <= _GEN_1
+    regfile.MPORT.data <= _GEN_4
+    regfile.MPORT.mask <= _GEN_3
+    id_reg_pc <= _id_reg_pc_T @[src/main/scala/micore/Core.scala 76:13]
+    id_reg_inst <= _id_reg_inst_T_2 @[src/main/scala/micore/Core.scala 77:15]
+    exe_reg_pc <= id_reg_pc @[src/main/scala/micore/Core.scala 181:14]
+    exe_reg_wb_addr <= id_wb_addr @[src/main/scala/micore/Core.scala 185:19]
+    exe_reg_op1_data <= id_op1_data @[src/main/scala/micore/Core.scala 182:20]
+    exe_reg_op2_data <= id_op2_data @[src/main/scala/micore/Core.scala 183:20]
+    exe_reg_rs2_data <= id_rs2_data @[src/main/scala/micore/Core.scala 184:20]
+    exe_reg_exe_fun <= csignals_0 @[src/main/scala/micore/Core.scala 190:19]
+    exe_reg_mem_wen <= csignals_3 @[src/main/scala/micore/Core.scala 187:19]
+    exe_reg_rf_wen <= csignals_4 @[src/main/scala/micore/Core.scala 188:18]
+    exe_reg_wb_sel <= csignals_5 @[src/main/scala/micore/Core.scala 186:18]
+    exe_reg_imm_b_sext <= id_imm_b_sext @[src/main/scala/micore/Core.scala 189:22]
+    mem_reg_pc <= exe_reg_pc @[src/main/scala/micore/Core.scala 225:14]
+    mem_reg_wb_addr <= exe_reg_wb_addr @[src/main/scala/micore/Core.scala 226:19]
+    mem_reg_alu_out <= exe_alu_out @[src/main/scala/micore/Core.scala 227:19]
+    mem_reg_rs2_data <= exe_reg_rs2_data @[src/main/scala/micore/Core.scala 228:20]
+    mem_reg_rf_wen <= exe_reg_rf_wen @[src/main/scala/micore/Core.scala 229:18]
+    mem_reg_wb_sel <= exe_reg_wb_sel @[src/main/scala/micore/Core.scala 230:18]
+    mem_reg_mem_wen <= exe_reg_mem_wen @[src/main/scala/micore/Core.scala 231:19]
+    wb_reg_wb_addr <= mem_reg_wb_addr @[src/main/scala/micore/Core.scala 249:18]
+    wb_reg_rf_wen <= mem_reg_rf_wen @[src/main/scala/micore/Core.scala 250:17]
+    wb_reg_wb_data <= mem_wb_data @[src/main/scala/micore/Core.scala 251:18]
+    if_reg_pc <= mux(reset, UInt<32>("h0"), if_pc_next) @[src/main/scala/micore/Core.scala 54:{26,26} 73:13]
+
+  module Memory : @[src/main/scala/micore/Memory.scala 20:7]
+    input clock : Clock @[src/main/scala/micore/Memory.scala 20:7]
+    input reset : UInt<1> @[src/main/scala/micore/Memory.scala 20:7]
+    input io_imem_addr : UInt<32> @[src/main/scala/micore/Memory.scala 21:14]
+    output io_imem_inst : UInt<32> @[src/main/scala/micore/Memory.scala 21:14]
+    input io_dmem_addr : UInt<32> @[src/main/scala/micore/Memory.scala 21:14]
+    output io_dmem_rdata : UInt<32> @[src/main/scala/micore/Memory.scala 21:14]
+    input io_dmem_wen : UInt<1> @[src/main/scala/micore/Memory.scala 21:14]
+    input io_dmem_wdata : UInt<32> @[src/main/scala/micore/Memory.scala 21:14]
+
+    mem mem : @[src/main/scala/micore/Memory.scala 27:24]
+      data-type => UInt<32>
+      depth => 512
+      read-latency => 1
+      write-latency => 1
+      reader => io_imem_inst_MPORT
+      reader => io_dmem_rdata_MPORT
+      writer => MPORT
+      read-under-write => undefined
+    node _io_imem_inst_T = shr(io_imem_addr, 2) @[src/main/scala/micore/Memory.scala 31:41]
+    node _GEN_0 = validif(UInt<1>("h1"), _io_imem_inst_T) @[src/main/scala/micore/Memory.scala 31:{27,27}]
+    node _io_imem_inst_WIRE = _GEN_0 @[src/main/scala/micore/Memory.scala 31:27]
+    node _io_imem_inst_T_1 = bits(_io_imem_inst_WIRE, 8, 0) @[src/main/scala/micore/Memory.scala 31:27]
+    node _GEN_1 = mux(UInt<1>("h1"), UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Memory.scala 27:24 31:{27,27}]
+    node _GEN_2 = validif(UInt<1>("h1"), _io_imem_inst_T_1) @[src/main/scala/micore/Memory.scala 31:{27,27}]
+    node _GEN_3 = validif(UInt<1>("h1"), clock) @[src/main/scala/micore/Memory.scala 31:{27,27}]
+    node _io_dmem_rdata_T = shr(io_dmem_addr, 2) @[src/main/scala/micore/Memory.scala 33:42]
+    node _GEN_4 = validif(UInt<1>("h1"), _io_dmem_rdata_T) @[src/main/scala/micore/Memory.scala 33:{28,28}]
+    node _io_dmem_rdata_WIRE = _GEN_4 @[src/main/scala/micore/Memory.scala 33:28]
+    node _io_dmem_rdata_T_1 = bits(_io_dmem_rdata_WIRE, 8, 0) @[src/main/scala/micore/Memory.scala 33:28]
+    node _GEN_5 = validif(UInt<1>("h1"), _io_dmem_rdata_T_1) @[src/main/scala/micore/Memory.scala 33:{28,28}]
+    node _T = shr(io_dmem_addr, 2) @[src/main/scala/micore/Memory.scala 36:28]
+    node _T_1 = bits(_T, 8, 0) @[src/main/scala/micore/Memory.scala 36:14]
+    node _GEN_6 = validif(io_dmem_wen, _T_1) @[src/main/scala/micore/Memory.scala 35:21 36:14]
+    node _GEN_7 = validif(io_dmem_wen, clock) @[src/main/scala/micore/Memory.scala 35:21 36:14]
+    node _GEN_8 = mux(io_dmem_wen, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Memory.scala 35:21 36:14 27:24]
+    node _GEN_9 = validif(io_dmem_wen, UInt<1>("h1")) @[src/main/scala/micore/Memory.scala 35:21 36:14]
+    node _GEN_10 = validif(io_dmem_wen, io_dmem_wdata) @[src/main/scala/micore/Memory.scala 35:21 36:14]
+    io_imem_inst <= mem.io_imem_inst_MPORT.data @[src/main/scala/micore/Memory.scala 31:16]
+    io_dmem_rdata <= mem.io_dmem_rdata_MPORT.data @[src/main/scala/micore/Memory.scala 33:17]
+    mem.io_imem_inst_MPORT.addr <= _GEN_2
+    mem.io_imem_inst_MPORT.en <= _GEN_1
+    mem.io_imem_inst_MPORT.clk <= _GEN_3
+    mem.io_dmem_rdata_MPORT.addr <= _GEN_5
+    mem.io_dmem_rdata_MPORT.en <= _GEN_1
+    mem.io_dmem_rdata_MPORT.clk <= _GEN_3
+    mem.MPORT.addr <= _GEN_6
+    mem.MPORT.en <= _GEN_8
+    mem.MPORT.clk <= _GEN_7
+    mem.MPORT.data <= _GEN_10
+    mem.MPORT.mask <= _GEN_9
+
+  module TopOrigin : @[src/main/scala/micore/Top.scala 8:7]
+    input clock : Clock @[src/main/scala/micore/Top.scala 8:7]
+    input reset : UInt<1> @[src/main/scala/micore/Top.scala 8:7]
+    output io_exit : UInt<1> @[src/main/scala/micore/Top.scala 9:14]
+
+    inst core of Core @[src/main/scala/micore/Top.scala 12:20]
+    inst memory of Memory @[src/main/scala/micore/Top.scala 13:22]
+    io_exit <= core.io_exit @[src/main/scala/micore/Top.scala 18:11]
+    core.clock <= clock
+    core.reset <= reset
+    core.io_imem_inst <= memory.io_imem_inst @[src/main/scala/micore/Top.scala 15:16]
+    core.io_dmem_rdata <= memory.io_dmem_rdata @[src/main/scala/micore/Top.scala 16:16]
+    memory.clock <= clock
+    memory.reset <= reset
+    memory.io_imem_addr <= core.io_imem_addr @[src/main/scala/micore/Top.scala 15:16]
+    memory.io_dmem_addr <= core.io_dmem_addr @[src/main/scala/micore/Top.scala 16:16]
+    memory.io_dmem_wen <= core.io_dmem_wen @[src/main/scala/micore/Top.scala 16:16]
+    memory.io_dmem_wdata <= core.io_dmem_wdata @[src/main/scala/micore/Top.scala 16:16]