Quest Completed!
This commit is contained in:
@ -18,6 +18,9 @@ circuit TopOrigin :
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write-latency => 1
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reader => id_rs_data_MPORT
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reader => id_rt_data_MPORT
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reader => MPORT_1
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reader => MPORT_2
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reader => MPORT_3
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writer => MPORT
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read-under-write => undefined
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reg id_reg_pc : UInt<32>, clock with :
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@ -32,79 +35,90 @@ circuit TopOrigin :
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reset => (UInt<1>("h0"), exe_reg_op1_data) @[src/main/scala/micore/Core.scala 25:33]
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reg exe_reg_op2_data : UInt<32>, clock with :
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reset => (UInt<1>("h0"), exe_reg_op2_data) @[src/main/scala/micore/Core.scala 26:33]
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reg exe_reg_rs_data : UInt<32>, clock with :
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reset => (UInt<1>("h0"), exe_reg_rs_data) @[src/main/scala/micore/Core.scala 27:32]
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reg exe_reg_rt_data : UInt<32>, clock with :
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reset => (UInt<1>("h0"), exe_reg_rt_data) @[src/main/scala/micore/Core.scala 28:32]
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reset => (UInt<1>("h0"), exe_reg_rt_data) @[src/main/scala/micore/Core.scala 27:32]
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reg exe_reg_exe_fun : UInt<5>, clock with :
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reset => (UInt<1>("h0"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 29:32]
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reset => (UInt<1>("h0"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 28:32]
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reg exe_reg_mem_wen : UInt<2>, clock with :
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reset => (UInt<1>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 30:32]
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reset => (UInt<1>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 29:32]
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reg exe_reg_rf_wen : UInt<2>, clock with :
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reset => (UInt<1>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 31:31]
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reset => (UInt<1>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 30:31]
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reg exe_reg_wb_sel : UInt<3>, clock with :
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reset => (UInt<1>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 32:31]
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reset => (UInt<1>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 31:31]
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reg exe_reg_imm_i_sext : UInt<32>, clock with :
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reset => (UInt<1>("h0"), exe_reg_imm_i_sext) @[src/main/scala/micore/Core.scala 33:35]
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reset => (UInt<1>("h0"), exe_reg_imm_i_sext) @[src/main/scala/micore/Core.scala 32:35]
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reg exe_reg_imm_j : UInt<32>, clock with :
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reset => (UInt<1>("h0"), exe_reg_imm_j) @[src/main/scala/micore/Core.scala 34:30]
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reset => (UInt<1>("h0"), exe_reg_imm_j) @[src/main/scala/micore/Core.scala 33:30]
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reg mem_reg_pc : UInt<32>, clock with :
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reset => (UInt<1>("h0"), mem_reg_pc) @[src/main/scala/micore/Core.scala 37:27]
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reset => (UInt<1>("h0"), mem_reg_pc) @[src/main/scala/micore/Core.scala 36:27]
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reg mem_reg_wb_addr : UInt<5>, clock with :
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reset => (UInt<1>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 38:32]
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reg mem_reg_alu_out : UInt<32>, clock with :
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reset => (UInt<1>("h0"), mem_reg_alu_out) @[src/main/scala/micore/Core.scala 39:32]
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reset => (UInt<1>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 37:32]
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reg mem_reg_rt_data : UInt<32>, clock with :
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reset => (UInt<1>("h0"), mem_reg_rt_data) @[src/main/scala/micore/Core.scala 40:32]
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reset => (UInt<1>("h0"), mem_reg_rt_data) @[src/main/scala/micore/Core.scala 38:32]
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reg mem_reg_mem_wen : UInt<2>, clock with :
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reset => (UInt<1>("h0"), mem_reg_mem_wen) @[src/main/scala/micore/Core.scala 41:32]
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reset => (UInt<1>("h0"), mem_reg_mem_wen) @[src/main/scala/micore/Core.scala 39:32]
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reg mem_reg_rf_wen : UInt<2>, clock with :
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reset => (UInt<1>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 42:31]
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reset => (UInt<1>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 40:31]
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reg mem_reg_wb_sel : UInt<3>, clock with :
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reset => (UInt<1>("h0"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 43:31]
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reset => (UInt<1>("h0"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 41:31]
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reg mem_reg_alu_out : UInt<32>, clock with :
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reset => (UInt<1>("h0"), mem_reg_alu_out) @[src/main/scala/micore/Core.scala 42:32]
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reg wb_reg_wb_addr : UInt<5>, clock with :
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reset => (UInt<1>("h0"), wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 46:31]
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reset => (UInt<1>("h0"), wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 45:31]
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reg wb_reg_rf_wen : UInt<2>, clock with :
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reset => (UInt<1>("h0"), wb_reg_rf_wen) @[src/main/scala/micore/Core.scala 47:30]
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reset => (UInt<1>("h0"), wb_reg_rf_wen) @[src/main/scala/micore/Core.scala 46:30]
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reg wb_reg_wb_data : UInt<32>, clock with :
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reset => (UInt<1>("h0"), wb_reg_wb_data) @[src/main/scala/micore/Core.scala 48:31]
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reset => (UInt<1>("h0"), wb_reg_wb_data) @[src/main/scala/micore/Core.scala 47:31]
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reg if_reg_pc : UInt<32>, clock with :
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reset => (UInt<1>("h0"), if_reg_pc) @[src/main/scala/micore/Core.scala 51:26]
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node _if_pc_plus4_T = add(if_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 61:31]
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node if_pc_plus4 = tail(_if_pc_plus4_T, 1) @[src/main/scala/micore/Core.scala 61:31]
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node stall_flg = UInt<1>("h0") @[src/main/scala/micore/Core.scala 55:23 93:13]
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reset => (UInt<1>("h0"), if_reg_pc) @[src/main/scala/micore/Core.scala 50:26]
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node _if_pc_plus4_T = add(if_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 60:31]
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node if_pc_plus4 = tail(_if_pc_plus4_T, 1) @[src/main/scala/micore/Core.scala 60:31]
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node _id_rs_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 87:21]
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node id_rs_addr_b = bits(id_reg_inst, 25, 21) @[src/main/scala/micore/Core.scala 82:33]
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node _id_rs_data_hazard_T_1 = neq(id_rs_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 87:49]
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node _id_rs_data_hazard_T_2 = and(_id_rs_data_hazard_T, _id_rs_data_hazard_T_1) @[src/main/scala/micore/Core.scala 87:32]
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node _id_rs_data_hazard_T_3 = eq(id_rs_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 87:75]
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node id_rs_data_hazard = and(_id_rs_data_hazard_T_2, _id_rs_data_hazard_T_3) @[src/main/scala/micore/Core.scala 87:58]
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node _id_rt_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 89:21]
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node id_rt_addr_b = bits(id_reg_inst, 20, 16) @[src/main/scala/micore/Core.scala 83:33]
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node _id_rt_data_hazard_T_1 = neq(id_rt_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 89:49]
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node _id_rt_data_hazard_T_2 = and(_id_rt_data_hazard_T, _id_rt_data_hazard_T_1) @[src/main/scala/micore/Core.scala 89:32]
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node _id_rt_data_hazard_T_3 = eq(id_rt_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 89:75]
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node id_rt_data_hazard = and(_id_rt_data_hazard_T_2, _id_rt_data_hazard_T_3) @[src/main/scala/micore/Core.scala 89:58]
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node _stall_flg_T = or(id_rs_data_hazard, id_rt_data_hazard) @[src/main/scala/micore/Core.scala 90:35]
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node stall_flg = _stall_flg_T @[src/main/scala/micore/Core.scala 54:23 90:13]
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node _if_pc_next_T = mux(stall_flg, if_reg_pc, if_pc_plus4) @[src/main/scala/chisel3/util/Mux.scala 126:16]
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node _exe_jmp_flg_T = eq(exe_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 222:34]
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node exe_jmp_flg = _exe_jmp_flg_T @[src/main/scala/micore/Core.scala 222:15 58:25]
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node _exe_alu_out_T = eq(exe_reg_exe_fun, UInt<5>("h1")) @[src/main/scala/micore/Core.scala 191:24]
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node _exe_alu_out_T_1 = add(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 191:58]
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node _exe_alu_out_T_2 = tail(_exe_alu_out_T_1, 1) @[src/main/scala/micore/Core.scala 191:58]
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node _exe_alu_out_T_3 = eq(exe_reg_exe_fun, UInt<5>("h2")) @[src/main/scala/micore/Core.scala 192:24]
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node _exe_alu_out_T_4 = sub(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 192:58]
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node _exe_alu_out_T_5 = tail(_exe_alu_out_T_4, 1) @[src/main/scala/micore/Core.scala 192:58]
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node _exe_alu_out_T_6 = eq(exe_reg_exe_fun, UInt<5>("h3")) @[src/main/scala/micore/Core.scala 193:24]
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node _exe_alu_out_T_7 = and(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 193:58]
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node _exe_alu_out_T_8 = eq(exe_reg_exe_fun, UInt<5>("h4")) @[src/main/scala/micore/Core.scala 194:24]
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node _exe_alu_out_T_9 = or(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 194:57]
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node _exe_alu_out_T_10 = eq(exe_reg_exe_fun, UInt<5>("h5")) @[src/main/scala/micore/Core.scala 195:24]
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node _exe_alu_out_T_11 = xor(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 195:58]
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node _exe_alu_out_T_12 = eq(exe_reg_exe_fun, UInt<5>("h6")) @[src/main/scala/micore/Core.scala 196:24]
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node _exe_alu_out_T_13 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 196:77]
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node _exe_alu_out_T_14 = dshl(exe_reg_op1_data, _exe_alu_out_T_13) @[src/main/scala/micore/Core.scala 196:58]
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node _exe_alu_out_T_15 = bits(_exe_alu_out_T_14, 31, 0) @[src/main/scala/micore/Core.scala 199:9]
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node _exe_alu_out_T_16 = eq(exe_reg_exe_fun, UInt<5>("h7")) @[src/main/scala/micore/Core.scala 200:24]
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node _exe_alu_out_T_17 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 200:77]
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node _exe_alu_out_T_18 = dshr(exe_reg_op1_data, _exe_alu_out_T_17) @[src/main/scala/micore/Core.scala 200:58]
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node _exe_alu_out_T_19 = eq(exe_reg_exe_fun, UInt<5>("h8")) @[src/main/scala/micore/Core.scala 204:24]
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node _exe_alu_out_T_20 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 204:58]
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node _exe_alu_out_T_21 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 204:84]
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node _exe_alu_out_T_22 = dshr(_exe_alu_out_T_20, _exe_alu_out_T_21) @[src/main/scala/micore/Core.scala 204:65]
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node _exe_alu_out_T_23 = asUInt(_exe_alu_out_T_22) @[src/main/scala/micore/Core.scala 207:10]
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node _exe_alu_out_T_24 = eq(exe_reg_exe_fun, UInt<5>("h9")) @[src/main/scala/micore/Core.scala 208:24]
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node _exe_alu_out_T_25 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 208:58]
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node _exe_alu_out_T_26 = asSInt(exe_reg_op2_data) @[src/main/scala/micore/Core.scala 208:84]
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node _exe_alu_out_T_27 = lt(_exe_alu_out_T_25, _exe_alu_out_T_26) @[src/main/scala/micore/Core.scala 208:65]
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node _exe_alu_out_T_28 = eq(exe_reg_exe_fun, UInt<5>("hd")) @[src/main/scala/micore/Core.scala 209:24]
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node _exe_jmp_flg_T = eq(exe_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 231:34]
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node exe_jmp_flg = _exe_jmp_flg_T @[src/main/scala/micore/Core.scala 231:15 57:25]
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node _exe_alu_out_T = eq(exe_reg_exe_fun, UInt<5>("h1")) @[src/main/scala/micore/Core.scala 198:24]
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node _exe_alu_out_T_1 = add(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 198:58]
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node _exe_alu_out_T_2 = tail(_exe_alu_out_T_1, 1) @[src/main/scala/micore/Core.scala 198:58]
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node _exe_alu_out_T_3 = eq(exe_reg_exe_fun, UInt<5>("h2")) @[src/main/scala/micore/Core.scala 199:24]
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node _exe_alu_out_T_4 = sub(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 199:58]
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node _exe_alu_out_T_5 = tail(_exe_alu_out_T_4, 1) @[src/main/scala/micore/Core.scala 199:58]
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node _exe_alu_out_T_6 = eq(exe_reg_exe_fun, UInt<5>("h3")) @[src/main/scala/micore/Core.scala 200:24]
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node _exe_alu_out_T_7 = and(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 200:58]
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node _exe_alu_out_T_8 = eq(exe_reg_exe_fun, UInt<5>("h4")) @[src/main/scala/micore/Core.scala 201:24]
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node _exe_alu_out_T_9 = or(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 201:57]
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node _exe_alu_out_T_10 = eq(exe_reg_exe_fun, UInt<5>("h5")) @[src/main/scala/micore/Core.scala 202:24]
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node _exe_alu_out_T_11 = xor(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 202:58]
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node _exe_alu_out_T_12 = eq(exe_reg_exe_fun, UInt<5>("h6")) @[src/main/scala/micore/Core.scala 203:24]
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node _exe_alu_out_T_13 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 203:77]
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node _exe_alu_out_T_14 = dshl(exe_reg_op1_data, _exe_alu_out_T_13) @[src/main/scala/micore/Core.scala 203:58]
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node _exe_alu_out_T_15 = bits(_exe_alu_out_T_14, 31, 0) @[src/main/scala/micore/Core.scala 206:9]
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node _exe_alu_out_T_16 = eq(exe_reg_exe_fun, UInt<5>("h7")) @[src/main/scala/micore/Core.scala 207:24]
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node _exe_alu_out_T_17 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 207:77]
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node _exe_alu_out_T_18 = dshr(exe_reg_op1_data, _exe_alu_out_T_17) @[src/main/scala/micore/Core.scala 207:58]
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node _exe_alu_out_T_19 = eq(exe_reg_exe_fun, UInt<5>("h8")) @[src/main/scala/micore/Core.scala 211:24]
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node _exe_alu_out_T_20 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 211:58]
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node _exe_alu_out_T_21 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 211:84]
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node _exe_alu_out_T_22 = dshr(_exe_alu_out_T_20, _exe_alu_out_T_21) @[src/main/scala/micore/Core.scala 211:65]
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node _exe_alu_out_T_23 = asUInt(_exe_alu_out_T_22) @[src/main/scala/micore/Core.scala 214:10]
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node _exe_alu_out_T_24 = eq(exe_reg_exe_fun, UInt<5>("h9")) @[src/main/scala/micore/Core.scala 215:24]
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node _exe_alu_out_T_25 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 215:58]
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node _exe_alu_out_T_26 = asSInt(exe_reg_op2_data) @[src/main/scala/micore/Core.scala 215:84]
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node _exe_alu_out_T_27 = lt(_exe_alu_out_T_25, _exe_alu_out_T_26) @[src/main/scala/micore/Core.scala 215:65]
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node _exe_alu_out_T_28 = eq(exe_reg_exe_fun, UInt<5>("hd")) @[src/main/scala/micore/Core.scala 216:24]
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node _exe_alu_out_T_29 = mux(_exe_alu_out_T_28, exe_reg_op1_data, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
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node _exe_alu_out_T_30 = mux(_exe_alu_out_T_24, _exe_alu_out_T_27, _exe_alu_out_T_29) @[src/main/scala/chisel3/util/Mux.scala 126:16]
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node _exe_alu_out_T_31 = mux(_exe_alu_out_T_19, _exe_alu_out_T_23, _exe_alu_out_T_30) @[src/main/scala/chisel3/util/Mux.scala 126:16]
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@ -115,68 +129,72 @@ circuit TopOrigin :
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node _exe_alu_out_T_36 = mux(_exe_alu_out_T_6, _exe_alu_out_T_7, _exe_alu_out_T_35) @[src/main/scala/chisel3/util/Mux.scala 126:16]
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node _exe_alu_out_T_37 = mux(_exe_alu_out_T_3, _exe_alu_out_T_5, _exe_alu_out_T_36) @[src/main/scala/chisel3/util/Mux.scala 126:16]
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node _exe_alu_out_T_38 = mux(_exe_alu_out_T, _exe_alu_out_T_2, _exe_alu_out_T_37) @[src/main/scala/chisel3/util/Mux.scala 126:16]
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node exe_alu_out = _exe_alu_out_T_38 @[src/main/scala/micore/Core.scala 188:15 59:25]
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node exe_alu_out = _exe_alu_out_T_38 @[src/main/scala/micore/Core.scala 195:15 58:25]
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node _if_pc_next_T_1 = mux(exe_jmp_flg, exe_alu_out, _if_pc_next_T) @[src/main/scala/chisel3/util/Mux.scala 126:16]
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node _exe_br_flg_T = eq(exe_reg_exe_fun, UInt<5>("hb")) @[src/main/scala/micore/Core.scala 216:24]
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node _exe_br_flg_T_1 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 216:57]
|
||||
node _exe_br_flg_T_2 = eq(exe_reg_exe_fun, UInt<5>("hc")) @[src/main/scala/micore/Core.scala 217:24]
|
||||
node _exe_br_flg_T_3 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 217:58]
|
||||
node _exe_br_flg_T_4 = eq(_exe_br_flg_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 217:39]
|
||||
node _exe_br_flg_T_5 = mux(_exe_br_flg_T_2, _exe_br_flg_T_4, UInt<1>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _exe_br_flg_T_6 = mux(_exe_br_flg_T, _exe_br_flg_T_1, _exe_br_flg_T_5) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node exe_br_flg = _exe_br_flg_T_6 @[src/main/scala/micore/Core.scala 213:14 56:24]
|
||||
node _exe_br_target_T = dshl(exe_reg_imm_i_sext, UInt<5>("h2")) @[src/main/scala/micore/Core.scala 221:53]
|
||||
node _exe_br_target_T_1 = add(exe_reg_pc, _exe_br_target_T) @[src/main/scala/micore/Core.scala 221:31]
|
||||
node _exe_br_target_T_2 = tail(_exe_br_target_T_1, 1) @[src/main/scala/micore/Core.scala 221:31]
|
||||
node exe_br_target = bits(_exe_br_target_T_2, 31, 0) @[src/main/scala/micore/Core.scala 221:17 57:27]
|
||||
node _exe_br_flg_T = eq(exe_reg_exe_fun, UInt<5>("hb")) @[src/main/scala/micore/Core.scala 223:24]
|
||||
node _exe_br_flg_T_1 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 223:57]
|
||||
node _exe_br_flg_T_2 = eq(exe_reg_exe_fun, UInt<5>("hc")) @[src/main/scala/micore/Core.scala 224:24]
|
||||
node _exe_br_flg_T_3 = neq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 224:57]
|
||||
node _exe_br_flg_T_4 = mux(_exe_br_flg_T_2, _exe_br_flg_T_3, UInt<1>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _exe_br_flg_T_5 = mux(_exe_br_flg_T, _exe_br_flg_T_1, _exe_br_flg_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node exe_br_flg = _exe_br_flg_T_5 @[src/main/scala/micore/Core.scala 220:14 55:24]
|
||||
node _exe_br_target_T = dshl(exe_reg_imm_i_sext, UInt<5>("h2")) @[src/main/scala/micore/Core.scala 228:53]
|
||||
node _exe_br_target_T_1 = add(exe_reg_pc, _exe_br_target_T) @[src/main/scala/micore/Core.scala 228:31]
|
||||
node _exe_br_target_T_2 = tail(_exe_br_target_T_1, 1) @[src/main/scala/micore/Core.scala 228:31]
|
||||
node exe_br_target = bits(_exe_br_target_T_2, 31, 0) @[src/main/scala/micore/Core.scala 228:17 56:27]
|
||||
node if_pc_next = mux(exe_br_flg, exe_br_target, _if_pc_next_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _id_reg_pc_T = mux(stall_flg, id_reg_pc, if_reg_pc) @[src/main/scala/micore/Core.scala 73:19]
|
||||
node _id_reg_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 77:19]
|
||||
node _id_reg_pc_T = mux(stall_flg, id_reg_pc, if_reg_pc) @[src/main/scala/micore/Core.scala 72:19]
|
||||
node _id_reg_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 76:19]
|
||||
node _id_reg_inst_T_1 = mux(stall_flg, id_reg_inst, io_imem_inst) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _id_reg_inst_T_2 = mux(_id_reg_inst_T, UInt<32>("h20090000"), _id_reg_inst_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node id_rs_addr = bits(id_reg_inst, 25, 21) @[src/main/scala/micore/Core.scala 83:31]
|
||||
node id_rt_addr = bits(id_reg_inst, 20, 16) @[src/main/scala/micore/Core.scala 84:31]
|
||||
node id_rd_addr = bits(id_reg_inst, 15, 11) @[src/main/scala/micore/Core.scala 85:31]
|
||||
node _id_rs_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 89:21]
|
||||
node _id_rs_data_hazard_T_1 = neq(id_rs_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 89:47]
|
||||
node _id_rs_data_hazard_T_2 = and(_id_rs_data_hazard_T, _id_rs_data_hazard_T_1) @[src/main/scala/micore/Core.scala 89:32]
|
||||
node _id_rs_data_hazard_T_3 = eq(id_rs_addr, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 89:71]
|
||||
node id_rs_data_hazard = and(_id_rs_data_hazard_T_2, _id_rs_data_hazard_T_3) @[src/main/scala/micore/Core.scala 89:56]
|
||||
node _id_rt_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 91:21]
|
||||
node _id_rt_data_hazard_T_1 = neq(id_rt_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 91:47]
|
||||
node _id_rt_data_hazard_T_2 = and(_id_rt_data_hazard_T, _id_rt_data_hazard_T_1) @[src/main/scala/micore/Core.scala 91:32]
|
||||
node _id_rt_data_hazard_T_3 = eq(id_rt_addr, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 91:71]
|
||||
node id_rt_data_hazard = and(_id_rt_data_hazard_T_2, _id_rt_data_hazard_T_3) @[src/main/scala/micore/Core.scala 91:56]
|
||||
node _id_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 96:21]
|
||||
node _id_inst_T_1 = or(_id_inst_T, stall_flg) @[src/main/scala/micore/Core.scala 96:36]
|
||||
node id_inst = mux(_id_inst_T_1, UInt<32>("h20090000"), id_reg_inst) @[src/main/scala/micore/Core.scala 96:8]
|
||||
node _id_rs_data_T = eq(id_rs_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 101:19]
|
||||
node _id_rs_data_T_1 = eq(id_rs_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 102:20]
|
||||
node _id_rs_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 102:60]
|
||||
node _id_rs_data_T_3 = and(_id_rs_data_T_1, _id_rs_data_T_2) @[src/main/scala/micore/Core.scala 102:41]
|
||||
node _id_rs_data_T_4 = eq(id_rs_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 103:20]
|
||||
node _id_rs_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 103:58]
|
||||
node _id_rs_data_T_6 = and(_id_rs_data_T_4, _id_rs_data_T_5) @[src/main/scala/micore/Core.scala 103:40]
|
||||
node _id_rs_data_T_7 = mux(_id_rs_data_T_6, wb_reg_wb_data, regfile.id_rs_data_MPORT.data) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _id_rs_data_T_8 = mux(_id_rs_data_T_3, mem_reg_alu_out, _id_rs_data_T_7) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node id_rs_data = mux(_id_rs_data_T, UInt<32>("h0"), _id_rs_data_T_8) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _id_rt_data_T = eq(id_rt_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 109:19]
|
||||
node _id_rt_data_T_1 = eq(id_rt_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 110:20]
|
||||
node _id_rt_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 110:60]
|
||||
node _id_rt_data_T_3 = and(_id_rt_data_T_1, _id_rt_data_T_2) @[src/main/scala/micore/Core.scala 110:41]
|
||||
node _id_rt_data_T_4 = eq(id_rt_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 111:20]
|
||||
node _id_rt_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 111:58]
|
||||
node _id_rt_data_T_6 = and(_id_rt_data_T_4, _id_rt_data_T_5) @[src/main/scala/micore/Core.scala 111:40]
|
||||
node _id_rt_data_T_7 = mux(_id_rt_data_T_6, wb_reg_wb_data, regfile.id_rt_data_MPORT.data) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _id_rt_data_T_8 = mux(_id_rt_data_T_3, mem_reg_alu_out, _id_rt_data_T_7) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node id_rt_data = mux(_id_rt_data_T, UInt<32>("h0"), _id_rt_data_T_8) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node id_imm_i = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 115:25]
|
||||
node _id_imm_i_sext_T = bits(id_imm_i, 15, 15) @[src/main/scala/micore/Core.scala 116:44]
|
||||
node _id_imm_i_sext_T_1 = mux(_id_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 116:31]
|
||||
node id_imm_i_sext = cat(_id_imm_i_sext_T_1, id_imm_i) @[src/main/scala/micore/Core.scala 116:26]
|
||||
node _id_imm_j_T = bits(id_inst, 25, 0) @[src/main/scala/micore/Core.scala 117:29]
|
||||
node _id_imm_j_T_1 = mux(UInt<1>("h0"), UInt<2>("h3"), UInt<2>("h0")) @[src/main/scala/micore/Core.scala 117:42]
|
||||
node id_imm_j = cat(_id_imm_j_T, _id_imm_j_T_1) @[src/main/scala/micore/Core.scala 117:21]
|
||||
node _id_reg_inst_T_2 = mux(_id_reg_inst_T, UInt<32>("h20000000"), _id_reg_inst_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _id_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 93:21]
|
||||
node _id_inst_T_1 = or(_id_inst_T, stall_flg) @[src/main/scala/micore/Core.scala 93:36]
|
||||
node id_inst = mux(_id_inst_T_1, UInt<32>("h20000000"), id_reg_inst) @[src/main/scala/micore/Core.scala 93:8]
|
||||
node id_rs_addr = bits(id_inst, 25, 21) @[src/main/scala/micore/Core.scala 95:27]
|
||||
node id_rt_addr = bits(id_inst, 20, 16) @[src/main/scala/micore/Core.scala 96:27]
|
||||
node id_rd_addr = bits(id_inst, 15, 11) @[src/main/scala/micore/Core.scala 97:27]
|
||||
node _id_rs_data_T = eq(id_rs_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 103:19]
|
||||
node _id_rs_data_T_1 = eq(id_rs_addr, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 104:20]
|
||||
node _id_rs_data_T_2 = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 104:60]
|
||||
node _id_rs_data_T_3 = and(_id_rs_data_T_1, _id_rs_data_T_2) @[src/main/scala/micore/Core.scala 104:41]
|
||||
node _id_rs_data_T_4 = eq(id_rs_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 105:20]
|
||||
node _id_rs_data_T_5 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 105:60]
|
||||
node _id_rs_data_T_6 = and(_id_rs_data_T_4, _id_rs_data_T_5) @[src/main/scala/micore/Core.scala 105:41]
|
||||
node _id_rs_data_T_7 = eq(id_rs_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 107:21]
|
||||
node _id_rs_data_T_8 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 107:59]
|
||||
node _id_rs_data_T_9 = and(_id_rs_data_T_7, _id_rs_data_T_8) @[src/main/scala/micore/Core.scala 107:41]
|
||||
node _id_rs_data_T_10 = mux(_id_rs_data_T_9, wb_reg_wb_data, regfile.id_rs_data_MPORT.data) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _mem_wb_data_T = eq(mem_reg_wb_sel, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 250:23]
|
||||
node _mem_wb_data_T_1 = eq(mem_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 251:23]
|
||||
node _mem_wb_data_T_2 = add(mem_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 251:49]
|
||||
node _mem_wb_data_T_3 = tail(_mem_wb_data_T_2, 1) @[src/main/scala/micore/Core.scala 251:49]
|
||||
node _mem_wb_data_T_4 = mux(_mem_wb_data_T_1, _mem_wb_data_T_3, mem_reg_alu_out) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _mem_wb_data_T_5 = mux(_mem_wb_data_T, io_dmem_rdata, _mem_wb_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node mem_wb_data = _mem_wb_data_T_5 @[src/main/scala/micore/Core.scala 247:15 99:25]
|
||||
node _id_rs_data_T_11 = mux(_id_rs_data_T_6, mem_wb_data, _id_rs_data_T_10) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _id_rs_data_T_12 = mux(_id_rs_data_T_3, exe_alu_out, _id_rs_data_T_11) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node id_rs_data = mux(_id_rs_data_T, UInt<32>("h0"), _id_rs_data_T_12) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _id_rt_data_T = eq(id_rt_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 114:19]
|
||||
node _id_rt_data_T_1 = eq(id_rt_addr, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 115:20]
|
||||
node _id_rt_data_T_2 = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 115:60]
|
||||
node _id_rt_data_T_3 = and(_id_rt_data_T_1, _id_rt_data_T_2) @[src/main/scala/micore/Core.scala 115:41]
|
||||
node _id_rt_data_T_4 = eq(id_rt_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 116:20]
|
||||
node _id_rt_data_T_5 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 116:60]
|
||||
node _id_rt_data_T_6 = and(_id_rt_data_T_4, _id_rt_data_T_5) @[src/main/scala/micore/Core.scala 116:41]
|
||||
node _id_rt_data_T_7 = eq(id_rt_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 118:21]
|
||||
node _id_rt_data_T_8 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 118:59]
|
||||
node _id_rt_data_T_9 = and(_id_rt_data_T_7, _id_rt_data_T_8) @[src/main/scala/micore/Core.scala 118:41]
|
||||
node _id_rt_data_T_10 = mux(_id_rt_data_T_9, wb_reg_wb_data, regfile.id_rt_data_MPORT.data) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _id_rt_data_T_11 = mux(_id_rt_data_T_6, mem_wb_data, _id_rt_data_T_10) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _id_rt_data_T_12 = mux(_id_rt_data_T_3, exe_alu_out, _id_rt_data_T_11) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node id_rt_data = mux(_id_rt_data_T, UInt<32>("h0"), _id_rt_data_T_12) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node id_imm_i = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 123:25]
|
||||
node _id_imm_i_sext_T = bits(id_imm_i, 15, 15) @[src/main/scala/micore/Core.scala 124:44]
|
||||
node _id_imm_i_sext_T_1 = mux(_id_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 124:31]
|
||||
node id_imm_i_sext = cat(_id_imm_i_sext_T_1, id_imm_i) @[src/main/scala/micore/Core.scala 124:26]
|
||||
node _id_imm_j_T = bits(id_inst, 25, 0) @[src/main/scala/micore/Core.scala 125:29]
|
||||
node _id_imm_j_T_1 = mux(UInt<1>("h0"), UInt<2>("h3"), UInt<2>("h0")) @[src/main/scala/micore/Core.scala 125:42]
|
||||
node id_imm_j = cat(_id_imm_j_T, _id_imm_j_T_1) @[src/main/scala/micore/Core.scala 125:21]
|
||||
node _csignals_T = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_1 = eq(UInt<32>("h8c000000"), _csignals_T) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_2 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
@ -321,110 +339,157 @@ circuit TopOrigin :
|
||||
node _csignals_T_136 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_135) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node _csignals_T_137 = mux(_csignals_T_3, UInt<3>("h0"), _csignals_T_136) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node csignals_5 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_137) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node _id_op1_data_T = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 150:19]
|
||||
node _id_op1_data_T_1 = eq(csignals_1, UInt<2>("h2")) @[src/main/scala/micore/Core.scala 151:19]
|
||||
node _id_op1_data_T = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 158:19]
|
||||
node _id_op1_data_T_1 = eq(csignals_1, UInt<2>("h2")) @[src/main/scala/micore/Core.scala 159:19]
|
||||
node _id_op1_data_T_2 = mux(_id_op1_data_T_1, id_reg_pc, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node id_op1_data = mux(_id_op1_data_T, id_rs_data, _id_op1_data_T_2) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _id_op2_data_T = eq(csignals_2, UInt<3>("h1")) @[src/main/scala/micore/Core.scala 158:19]
|
||||
node _id_op2_data_T_1 = eq(csignals_2, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 159:19]
|
||||
node _id_op2_data_T_2 = eq(csignals_2, UInt<3>("h4")) @[src/main/scala/micore/Core.scala 160:19]
|
||||
node _id_op2_data_T = eq(csignals_2, UInt<3>("h1")) @[src/main/scala/micore/Core.scala 166:19]
|
||||
node _id_op2_data_T_1 = eq(csignals_2, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 167:19]
|
||||
node _id_op2_data_T_2 = eq(csignals_2, UInt<3>("h4")) @[src/main/scala/micore/Core.scala 168:19]
|
||||
node _id_op2_data_T_3 = mux(_id_op2_data_T_2, id_imm_j, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _id_op2_data_T_4 = mux(_id_op2_data_T_1, id_imm_i_sext, _id_op2_data_T_3) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node id_op2_data = mux(_id_op2_data_T, id_rt_data, _id_op2_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _exe_reg_wb_addr_T = eq(csignals_5, UInt<3>("h1")) @[src/main/scala/micore/Core.scala 173:18]
|
||||
node _exe_reg_wb_addr_T_1 = bits(id_inst, 31, 26) @[src/main/scala/micore/Core.scala 173:39]
|
||||
node _exe_reg_wb_addr_T_2 = eq(_exe_reg_wb_addr_T_1, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 176:9]
|
||||
node _exe_reg_wb_addr_T_3 = and(_exe_reg_wb_addr_T, _exe_reg_wb_addr_T_2) @[src/main/scala/micore/Core.scala 173:29]
|
||||
node _exe_reg_wb_addr_T_4 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/micore/Core.scala 177:16]
|
||||
node _exe_reg_wb_addr_T_5 = eq(UInt<28>("hc000000"), _exe_reg_wb_addr_T_4) @[src/main/scala/micore/Core.scala 177:16]
|
||||
node _exe_reg_wb_addr_T = eq(csignals_5, UInt<3>("h1")) @[src/main/scala/micore/Core.scala 180:18]
|
||||
node _exe_reg_wb_addr_T_1 = bits(id_inst, 31, 26) @[src/main/scala/micore/Core.scala 180:39]
|
||||
node _exe_reg_wb_addr_T_2 = eq(_exe_reg_wb_addr_T_1, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 183:9]
|
||||
node _exe_reg_wb_addr_T_3 = and(_exe_reg_wb_addr_T, _exe_reg_wb_addr_T_2) @[src/main/scala/micore/Core.scala 180:29]
|
||||
node _exe_reg_wb_addr_T_4 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/micore/Core.scala 184:16]
|
||||
node _exe_reg_wb_addr_T_5 = eq(UInt<28>("hc000000"), _exe_reg_wb_addr_T_4) @[src/main/scala/micore/Core.scala 184:16]
|
||||
node _exe_reg_wb_addr_T_6 = mux(_exe_reg_wb_addr_T_5, UInt<5>("h1f"), id_rt_addr) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _exe_reg_wb_addr_T_7 = mux(_exe_reg_wb_addr_T_3, id_rd_addr, _exe_reg_wb_addr_T_6) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _mem_wb_data_T = eq(mem_reg_wb_sel, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 241:23]
|
||||
node _mem_wb_data_T_1 = eq(mem_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 242:23]
|
||||
node _mem_wb_data_T_2 = add(mem_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 242:49]
|
||||
node _mem_wb_data_T_3 = tail(_mem_wb_data_T_2, 1) @[src/main/scala/micore/Core.scala 242:49]
|
||||
node _mem_wb_data_T_4 = mux(_mem_wb_data_T_1, _mem_wb_data_T_3, mem_reg_alu_out) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node mem_wb_data = mux(_mem_wb_data_T, io_dmem_rdata, _mem_wb_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _T = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 252:22]
|
||||
node _T_1 = neq(wb_reg_wb_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 252:50]
|
||||
node _T_2 = and(_T, _T_1) @[src/main/scala/micore/Core.scala 252:32]
|
||||
node _GEN_0 = validif(_T_2, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 252:59 253:12]
|
||||
node _GEN_1 = validif(_T_2, clock) @[src/main/scala/micore/Core.scala 252:59 253:12]
|
||||
node _GEN_2 = mux(_T_2, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Core.scala 252:59 253:12 15:20]
|
||||
node _GEN_3 = validif(_T_2, UInt<1>("h1")) @[src/main/scala/micore/Core.scala 252:59 253:29]
|
||||
node _GEN_4 = validif(_T_2, wb_reg_wb_data) @[src/main/scala/micore/Core.scala 252:59 253:29]
|
||||
node _io_exit_T = eq(id_reg_inst, UInt<32>("h114514")) @[src/main/scala/micore/Core.scala 256:27]
|
||||
node _T_3 = asUInt(reset) @[src/main/scala/micore/Core.scala 259:9]
|
||||
node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 259:9]
|
||||
node _T_5 = asUInt(reset) @[src/main/scala/micore/Core.scala 260:9]
|
||||
node _T_6 = eq(_T_5, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 260:9]
|
||||
node _T_7 = asUInt(reset) @[src/main/scala/micore/Core.scala 261:9]
|
||||
node _T_8 = eq(_T_7, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 261:9]
|
||||
node _T_9 = asUInt(reset) @[src/main/scala/micore/Core.scala 262:9]
|
||||
node _T_10 = eq(_T_9, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 262:9]
|
||||
node _T_11 = asUInt(reset) @[src/main/scala/micore/Core.scala 263:9]
|
||||
node _T_12 = eq(_T_11, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 263:9]
|
||||
node _T_13 = asUInt(reset) @[src/main/scala/micore/Core.scala 264:9]
|
||||
node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 264:9]
|
||||
node _T_15 = asUInt(reset) @[src/main/scala/micore/Core.scala 265:9]
|
||||
node _T_16 = eq(_T_15, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 265:9]
|
||||
node _T_17 = asUInt(reset) @[src/main/scala/micore/Core.scala 266:9]
|
||||
node _T_18 = eq(_T_17, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 266:9]
|
||||
node _T_19 = asUInt(reset) @[src/main/scala/micore/Core.scala 267:9]
|
||||
node _T_20 = eq(_T_19, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 267:9]
|
||||
node _T_21 = asUInt(reset) @[src/main/scala/micore/Core.scala 268:9]
|
||||
node _T_22 = eq(_T_21, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 268:9]
|
||||
io_imem_addr <= if_reg_pc @[src/main/scala/micore/Core.scala 52:16]
|
||||
io_dmem_addr <= mem_reg_alu_out @[src/main/scala/micore/Core.scala 234:16]
|
||||
io_dmem_wen <= bits(mem_reg_mem_wen, 0, 0) @[src/main/scala/micore/Core.scala 235:15]
|
||||
io_dmem_wdata <= mem_reg_rt_data @[src/main/scala/micore/Core.scala 236:17]
|
||||
io_exit <= _io_exit_T @[src/main/scala/micore/Core.scala 256:11]
|
||||
regfile.id_rs_data_MPORT.addr <= id_rs_addr @[src/main/scala/micore/Core.scala 99:12]
|
||||
regfile.id_rs_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 99:12]
|
||||
regfile.id_rs_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 99:12]
|
||||
regfile.id_rt_data_MPORT.addr <= id_rt_addr @[src/main/scala/micore/Core.scala 107:12]
|
||||
regfile.id_rt_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 107:12]
|
||||
regfile.id_rt_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 107:12]
|
||||
node _T = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 261:22]
|
||||
node _T_1 = neq(wb_reg_wb_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 261:50]
|
||||
node _T_2 = and(_T, _T_1) @[src/main/scala/micore/Core.scala 261:32]
|
||||
node _GEN_0 = validif(_T_2, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 261:59 262:12]
|
||||
node _GEN_1 = validif(_T_2, clock) @[src/main/scala/micore/Core.scala 261:59 262:12]
|
||||
node _GEN_2 = mux(_T_2, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Core.scala 261:59 262:12 15:20]
|
||||
node _GEN_3 = validif(_T_2, UInt<1>("h1")) @[src/main/scala/micore/Core.scala 261:59 262:29]
|
||||
node _GEN_4 = validif(_T_2, wb_reg_wb_data) @[src/main/scala/micore/Core.scala 261:59 262:29]
|
||||
node _io_exit_T = eq(id_reg_inst, UInt<32>("h114514")) @[src/main/scala/micore/Core.scala 265:27]
|
||||
node _T_3 = asUInt(reset) @[src/main/scala/micore/Core.scala 268:9]
|
||||
node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 268:9]
|
||||
node _T_5 = asUInt(reset) @[src/main/scala/micore/Core.scala 269:9]
|
||||
node _T_6 = eq(_T_5, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 269:9]
|
||||
node _T_7 = asUInt(reset) @[src/main/scala/micore/Core.scala 270:9]
|
||||
node _T_8 = eq(_T_7, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 270:9]
|
||||
node _T_9 = asUInt(reset) @[src/main/scala/micore/Core.scala 271:9]
|
||||
node _T_10 = eq(_T_9, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 271:9]
|
||||
node _T_11 = asUInt(reset) @[src/main/scala/micore/Core.scala 272:9]
|
||||
node _T_12 = eq(_T_11, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 272:9]
|
||||
node _T_13 = asUInt(reset) @[src/main/scala/micore/Core.scala 273:9]
|
||||
node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 273:9]
|
||||
node _T_15 = asUInt(reset) @[src/main/scala/micore/Core.scala 274:9]
|
||||
node _T_16 = eq(_T_15, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 274:9]
|
||||
node _T_17 = asUInt(reset) @[src/main/scala/micore/Core.scala 275:9]
|
||||
node _T_18 = eq(_T_17, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 275:9]
|
||||
node _T_19 = asUInt(reset) @[src/main/scala/micore/Core.scala 276:9]
|
||||
node _T_20 = eq(_T_19, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 276:9]
|
||||
node _T_21 = asUInt(reset) @[src/main/scala/micore/Core.scala 277:9]
|
||||
node _T_22 = eq(_T_21, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 277:9]
|
||||
node _T_23 = asUInt(reset) @[src/main/scala/micore/Core.scala 278:9]
|
||||
node _T_24 = eq(_T_23, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 278:9]
|
||||
node _T_25 = asUInt(reset) @[src/main/scala/micore/Core.scala 284:9]
|
||||
node _T_26 = eq(_T_25, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 284:9]
|
||||
node _T_27 = asUInt(reset) @[src/main/scala/micore/Core.scala 285:9]
|
||||
node _T_28 = eq(_T_27, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 285:9]
|
||||
node _T_29 = asUInt(reset) @[src/main/scala/micore/Core.scala 286:9]
|
||||
node _T_30 = eq(_T_29, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 286:9]
|
||||
node _T_31 = asUInt(reset) @[src/main/scala/micore/Core.scala 287:9]
|
||||
node _T_32 = eq(_T_31, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 287:9]
|
||||
node _T_33 = asUInt(reset) @[src/main/scala/micore/Core.scala 288:9]
|
||||
node _T_34 = eq(_T_33, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 288:9]
|
||||
node _T_35 = asUInt(reset) @[src/main/scala/micore/Core.scala 290:9]
|
||||
node _T_36 = eq(_T_35, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 290:9]
|
||||
node _T_37 = asUInt(reset) @[src/main/scala/micore/Core.scala 291:9]
|
||||
node _T_38 = eq(_T_37, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 291:9]
|
||||
node _T_39 = asUInt(reset) @[src/main/scala/micore/Core.scala 292:9]
|
||||
node _T_40 = eq(_T_39, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 292:9]
|
||||
node _T_41 = asUInt(reset) @[src/main/scala/micore/Core.scala 293:9]
|
||||
node _T_42 = eq(_T_41, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 293:9]
|
||||
node _T_43 = asUInt(reset) @[src/main/scala/micore/Core.scala 294:9]
|
||||
node _T_44 = eq(_T_43, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 294:9]
|
||||
node _T_45 = asUInt(reset) @[src/main/scala/micore/Core.scala 295:9]
|
||||
node _T_46 = eq(_T_45, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 295:9]
|
||||
node _T_47 = asUInt(reset) @[src/main/scala/micore/Core.scala 296:9]
|
||||
node _T_48 = eq(_T_47, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 296:9]
|
||||
node _T_49 = asUInt(reset) @[src/main/scala/micore/Core.scala 297:9]
|
||||
node _T_50 = eq(_T_49, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 297:9]
|
||||
node _T_51 = asUInt(reset) @[src/main/scala/micore/Core.scala 298:9]
|
||||
node _T_52 = eq(_T_51, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 298:9]
|
||||
io_imem_addr <= if_reg_pc @[src/main/scala/micore/Core.scala 51:16]
|
||||
io_dmem_addr <= mem_reg_alu_out @[src/main/scala/micore/Core.scala 243:16]
|
||||
io_dmem_wen <= bits(mem_reg_mem_wen, 0, 0) @[src/main/scala/micore/Core.scala 244:15]
|
||||
io_dmem_wdata <= mem_reg_rt_data @[src/main/scala/micore/Core.scala 245:17]
|
||||
io_exit <= _io_exit_T @[src/main/scala/micore/Core.scala 265:11]
|
||||
regfile.id_rs_data_MPORT.addr <= id_rs_addr @[src/main/scala/micore/Core.scala 101:12]
|
||||
regfile.id_rs_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 101:12]
|
||||
regfile.id_rs_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 101:12]
|
||||
regfile.id_rt_data_MPORT.addr <= id_rt_addr @[src/main/scala/micore/Core.scala 112:12]
|
||||
regfile.id_rt_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 112:12]
|
||||
regfile.id_rt_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 112:12]
|
||||
regfile.MPORT_1.addr <= UInt<5>("h10") @[src/main/scala/micore/Core.scala 295:36]
|
||||
regfile.MPORT_1.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 295:36]
|
||||
regfile.MPORT_1.clk <= clock @[src/main/scala/micore/Core.scala 295:36]
|
||||
regfile.MPORT_2.addr <= UInt<5>("h12") @[src/main/scala/micore/Core.scala 296:36]
|
||||
regfile.MPORT_2.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 296:36]
|
||||
regfile.MPORT_2.clk <= clock @[src/main/scala/micore/Core.scala 296:36]
|
||||
regfile.MPORT_3.addr <= UInt<5>("h8") @[src/main/scala/micore/Core.scala 297:36]
|
||||
regfile.MPORT_3.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 297:36]
|
||||
regfile.MPORT_3.clk <= clock @[src/main/scala/micore/Core.scala 297:36]
|
||||
regfile.MPORT.addr <= _GEN_0
|
||||
regfile.MPORT.en <= _GEN_2
|
||||
regfile.MPORT.clk <= _GEN_1
|
||||
regfile.MPORT.data <= _GEN_4
|
||||
regfile.MPORT.mask <= _GEN_3
|
||||
id_reg_pc <= mux(reset, UInt<32>("h0"), _id_reg_pc_T) @[src/main/scala/micore/Core.scala 19:{26,26} 73:13]
|
||||
id_reg_inst <= mux(reset, UInt<32>("h0"), _id_reg_inst_T_2) @[src/main/scala/micore/Core.scala 20:{28,28} 74:15]
|
||||
exe_reg_pc <= mux(reset, UInt<32>("h0"), id_reg_pc) @[src/main/scala/micore/Core.scala 165:14 23:{27,27}]
|
||||
exe_reg_wb_addr <= mux(reset, UInt<5>("h0"), _exe_reg_wb_addr_T_7) @[src/main/scala/micore/Core.scala 170:19 24:{32,32}]
|
||||
exe_reg_op1_data <= mux(reset, UInt<32>("h0"), id_op1_data) @[src/main/scala/micore/Core.scala 166:20 25:{33,33}]
|
||||
exe_reg_op2_data <= mux(reset, UInt<32>("h0"), id_op2_data) @[src/main/scala/micore/Core.scala 167:20 26:{33,33}]
|
||||
exe_reg_rs_data <= mux(reset, UInt<32>("h0"), id_rs_data) @[src/main/scala/micore/Core.scala 168:19 27:{32,32}]
|
||||
exe_reg_rt_data <= mux(reset, UInt<32>("h0"), id_rt_data) @[src/main/scala/micore/Core.scala 169:19 28:{32,32}]
|
||||
exe_reg_exe_fun <= mux(reset, UInt<5>("h0"), csignals_0) @[src/main/scala/micore/Core.scala 185:19 29:{32,32}]
|
||||
exe_reg_mem_wen <= mux(reset, UInt<2>("h0"), csignals_3) @[src/main/scala/micore/Core.scala 181:19 30:{32,32}]
|
||||
exe_reg_rf_wen <= mux(reset, UInt<2>("h0"), csignals_4) @[src/main/scala/micore/Core.scala 182:18 31:{31,31}]
|
||||
exe_reg_wb_sel <= mux(reset, UInt<3>("h0"), csignals_5) @[src/main/scala/micore/Core.scala 180:18 32:{31,31}]
|
||||
exe_reg_imm_i_sext <= mux(reset, UInt<32>("h0"), id_imm_i_sext) @[src/main/scala/micore/Core.scala 183:22 33:{35,35}]
|
||||
exe_reg_imm_j <= mux(reset, UInt<32>("h0"), id_imm_j) @[src/main/scala/micore/Core.scala 184:17 34:{30,30}]
|
||||
mem_reg_pc <= mux(reset, UInt<32>("h0"), exe_reg_pc) @[src/main/scala/micore/Core.scala 225:14 37:{27,27}]
|
||||
mem_reg_wb_addr <= mux(reset, UInt<5>("h0"), exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 226:19 38:{32,32}]
|
||||
mem_reg_alu_out <= mux(reset, UInt<32>("h0"), exe_alu_out) @[src/main/scala/micore/Core.scala 227:19 39:{32,32}]
|
||||
mem_reg_rt_data <= mux(reset, UInt<32>("h0"), exe_reg_rt_data) @[src/main/scala/micore/Core.scala 228:19 40:{32,32}]
|
||||
mem_reg_mem_wen <= mux(reset, UInt<2>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 229:19 41:{32,32}]
|
||||
mem_reg_rf_wen <= mux(reset, UInt<2>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 230:18 42:{31,31}]
|
||||
mem_reg_wb_sel <= mux(reset, UInt<3>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 231:18 43:{31,31}]
|
||||
wb_reg_wb_addr <= mux(reset, UInt<5>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 247:18 46:{31,31}]
|
||||
wb_reg_rf_wen <= mux(reset, UInt<2>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 248:17 47:{30,30}]
|
||||
wb_reg_wb_data <= mux(reset, UInt<32>("h0"), mem_wb_data) @[src/main/scala/micore/Core.scala 249:18 48:{31,31}]
|
||||
if_reg_pc <= mux(reset, UInt<32>("h0"), if_pc_next) @[src/main/scala/micore/Core.scala 51:{26,26} 70:13]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "---------------\n") : printf @[src/main/scala/micore/Core.scala 259:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "if_reg_pc: 0x%x\n", if_reg_pc) : printf_1 @[src/main/scala/micore/Core.scala 260:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_8), UInt<1>("h1")), "id_reg_pc: 0x%x\n", id_reg_pc) : printf_2 @[src/main/scala/micore/Core.scala 261:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "id_reg_inst: 0x%x\n", id_reg_inst) : printf_3 @[src/main/scala/micore/Core.scala 262:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "exe_reg_pc: 0x%x\n", exe_reg_pc) : printf_4 @[src/main/scala/micore/Core.scala 263:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "exe_alu_out: 0x%x\n", exe_alu_out) : printf_5 @[src/main/scala/micore/Core.scala 264:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "mem_reg_pc: 0x%x\n", mem_reg_pc) : printf_6 @[src/main/scala/micore/Core.scala 265:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "mem_wb_data: 0x%x\n", mem_wb_data) : printf_7 @[src/main/scala/micore/Core.scala 266:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_20), UInt<1>("h1")), "wb_reg_wb_data: 0x%x\n", wb_reg_wb_data) : printf_8 @[src/main/scala/micore/Core.scala 267:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_22), UInt<1>("h1")), "---------------\n") : printf_9 @[src/main/scala/micore/Core.scala 268:9]
|
||||
id_reg_pc <= mux(reset, UInt<32>("h0"), _id_reg_pc_T) @[src/main/scala/micore/Core.scala 19:{26,26} 72:13]
|
||||
id_reg_inst <= mux(reset, UInt<32>("h0"), _id_reg_inst_T_2) @[src/main/scala/micore/Core.scala 20:{28,28} 73:15]
|
||||
exe_reg_pc <= mux(reset, UInt<32>("h0"), id_reg_pc) @[src/main/scala/micore/Core.scala 173:14 23:{27,27}]
|
||||
exe_reg_wb_addr <= mux(reset, UInt<5>("h0"), _exe_reg_wb_addr_T_7) @[src/main/scala/micore/Core.scala 177:19 24:{32,32}]
|
||||
exe_reg_op1_data <= mux(reset, UInt<32>("h0"), id_op1_data) @[src/main/scala/micore/Core.scala 174:20 25:{33,33}]
|
||||
exe_reg_op2_data <= mux(reset, UInt<32>("h0"), id_op2_data) @[src/main/scala/micore/Core.scala 175:20 26:{33,33}]
|
||||
exe_reg_rt_data <= mux(reset, UInt<32>("h0"), id_rt_data) @[src/main/scala/micore/Core.scala 176:19 27:{32,32}]
|
||||
exe_reg_exe_fun <= mux(reset, UInt<5>("h0"), csignals_0) @[src/main/scala/micore/Core.scala 192:19 28:{32,32}]
|
||||
exe_reg_mem_wen <= mux(reset, UInt<2>("h0"), csignals_3) @[src/main/scala/micore/Core.scala 188:19 29:{32,32}]
|
||||
exe_reg_rf_wen <= mux(reset, UInt<2>("h0"), csignals_4) @[src/main/scala/micore/Core.scala 189:18 30:{31,31}]
|
||||
exe_reg_wb_sel <= mux(reset, UInt<3>("h0"), csignals_5) @[src/main/scala/micore/Core.scala 187:18 31:{31,31}]
|
||||
exe_reg_imm_i_sext <= mux(reset, UInt<32>("h0"), id_imm_i_sext) @[src/main/scala/micore/Core.scala 190:22 32:{35,35}]
|
||||
exe_reg_imm_j <= mux(reset, UInt<32>("h0"), id_imm_j) @[src/main/scala/micore/Core.scala 191:17 33:{30,30}]
|
||||
mem_reg_pc <= mux(reset, UInt<32>("h0"), exe_reg_pc) @[src/main/scala/micore/Core.scala 234:14 36:{27,27}]
|
||||
mem_reg_wb_addr <= mux(reset, UInt<5>("h0"), exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 236:19 37:{32,32}]
|
||||
mem_reg_rt_data <= mux(reset, UInt<32>("h0"), exe_reg_rt_data) @[src/main/scala/micore/Core.scala 235:19 38:{32,32}]
|
||||
mem_reg_mem_wen <= mux(reset, UInt<2>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 240:19 39:{32,32}]
|
||||
mem_reg_rf_wen <= mux(reset, UInt<2>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 238:18 40:{31,31}]
|
||||
mem_reg_wb_sel <= mux(reset, UInt<3>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 239:18 41:{31,31}]
|
||||
mem_reg_alu_out <= mux(reset, UInt<32>("h0"), exe_alu_out) @[src/main/scala/micore/Core.scala 237:19 42:{32,32}]
|
||||
wb_reg_wb_addr <= mux(reset, UInt<5>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 258:18 45:{31,31}]
|
||||
wb_reg_rf_wen <= mux(reset, UInt<2>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 257:17 46:{30,30}]
|
||||
wb_reg_wb_data <= mux(reset, UInt<32>("h0"), mem_wb_data) @[src/main/scala/micore/Core.scala 256:18 47:{31,31}]
|
||||
if_reg_pc <= mux(reset, UInt<32>("h0"), if_pc_next) @[src/main/scala/micore/Core.scala 50:{26,26} 69:13]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "---------------\n") : printf @[src/main/scala/micore/Core.scala 268:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "if_inst: 0x%x\n", io_imem_inst) : printf_1 @[src/main/scala/micore/Core.scala 269:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_8), UInt<1>("h1")), "if_reg_pc: 0x%x\n", if_reg_pc) : printf_2 @[src/main/scala/micore/Core.scala 270:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "id_reg_pc: 0x%x\n", id_reg_pc) : printf_3 @[src/main/scala/micore/Core.scala 271:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "id_reg_inst: 0x%x\n", id_reg_inst) : printf_4 @[src/main/scala/micore/Core.scala 272:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "id_inst: 0x%x\n", id_inst) : printf_5 @[src/main/scala/micore/Core.scala 273:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "id_rs_data: 0x%x\n", id_rs_data) : printf_6 @[src/main/scala/micore/Core.scala 274:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "id_rt_data: 0x%x\n", id_rt_data) : printf_7 @[src/main/scala/micore/Core.scala 275:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_20), UInt<1>("h1")), "id_rs_addr: 0x%x\n", id_rs_addr) : printf_8 @[src/main/scala/micore/Core.scala 276:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_22), UInt<1>("h1")), "id_rt_addr: 0x%x\n", id_rt_addr) : printf_9 @[src/main/scala/micore/Core.scala 277:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_24), UInt<1>("h1")), "id_rd_addr: 0x%x\n", id_rd_addr) : printf_10 @[src/main/scala/micore/Core.scala 278:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_26), UInt<1>("h1")), "stall_flg: 0x%x\n", stall_flg) : printf_11 @[src/main/scala/micore/Core.scala 284:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_28), UInt<1>("h1")), "exe_reg_pc: 0x%x\n", exe_reg_pc) : printf_12 @[src/main/scala/micore/Core.scala 285:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_30), UInt<1>("h1")), "exe_reg_op1_data: 0x%x\n", exe_reg_op1_data) : printf_13 @[src/main/scala/micore/Core.scala 286:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_32), UInt<1>("h1")), "exe_reg_op2_data: 0x%x\n", exe_reg_op2_data) : printf_14 @[src/main/scala/micore/Core.scala 287:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_34), UInt<1>("h1")), "exe_alu_out: 0x%x\n", exe_alu_out) : printf_15 @[src/main/scala/micore/Core.scala 288:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_36), UInt<1>("h1")), "exe_reg_wb_addr: 0x%x\n", exe_reg_wb_addr) : printf_16 @[src/main/scala/micore/Core.scala 290:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_38), UInt<1>("h1")), "mem_reg_pc: 0x%x\n", mem_reg_pc) : printf_17 @[src/main/scala/micore/Core.scala 291:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_40), UInt<1>("h1")), "mem_wb_data: 0x%x\n", mem_wb_data) : printf_18 @[src/main/scala/micore/Core.scala 292:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_42), UInt<1>("h1")), "wb_reg_wb_addr: 0x%x\n", wb_reg_wb_addr) : printf_19 @[src/main/scala/micore/Core.scala 293:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_44), UInt<1>("h1")), "wb_reg_wb_data: 0x%x\n", wb_reg_wb_data) : printf_20 @[src/main/scala/micore/Core.scala 294:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_46), UInt<1>("h1")), "regfile s0: 0x%d\n", regfile.MPORT_1.data) : printf_21 @[src/main/scala/micore/Core.scala 295:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_48), UInt<1>("h1")), "regfile s2: 0x%d\n", regfile.MPORT_2.data) : printf_22 @[src/main/scala/micore/Core.scala 296:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_50), UInt<1>("h1")), "regfile t0: 0x%d\n", regfile.MPORT_3.data) : printf_23 @[src/main/scala/micore/Core.scala 297:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_52), UInt<1>("h1")), "---------------\n") : printf_24 @[src/main/scala/micore/Core.scala 298:9]
|
||||
|
||||
module Memory : @[src/main/scala/micore/Memory.scala 20:7]
|
||||
input clock : Clock @[src/main/scala/micore/Memory.scala 20:7]
|
||||
|
||||
Reference in New Issue
Block a user