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Code Optimization and Clean Up

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CGH0S7
2025-01-02 17:12:14 +08:00
parent 106519d1ab
commit b4e64b8f52
168 changed files with 689 additions and 1079 deletions
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131
testbench.sv
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@ -19,28 +19,56 @@
//
//////////////////////////////////////////////////////////////////////////////////
module tb_Top();
module Top_tb;
reg clock;
reg reset;
wire io_exit;
wire io_exit;
wire [3:0] io_anodes;
wire [6:0] io_segments;
wire [31:0] if_reg_pc;
wire [31:0] id_reg_pc;
wire [31:0] _memory_io_imem_inst;
wire [31:0] id_inst;
wire [31:0] id_reg_inst;
wire [31:0] exe_reg_op1_data;
wire [31:0] exe_reg_op2_data;
wire [31:0] exe_alu_out;
wire [3:0] exe_reg_exe_fun;
wire exe_br_flg;
wire stall_flg;
wire [31:0] mem_reg_alu_out;
wire [31:0] reg_r8;
wire [31:0] reg_r10;
wire [31:0] reg_r16;
wire [31:0] reg_r18;
Top uut (
.clock(clock),
.reset(reset),
.io_exit(io_exit),
.io_anodes(io_anodes),
.io_segments(io_segments)
);
.clock (clock),
.reset (reset),
.io_exit (io_exit)
);
assign if_reg_pc = uut.core.if_reg_pc;
assign id_reg_pc = uut.core.id_reg_pc;
assign _memory_io_imem_inst = uut.core._memory_io_imem_inst;
assign id_inst = uut.core.id_inst;
assign id_reg_inst = uut.core.id_reg_inst;
assign exe_reg_op1_data = uut.core.exe_reg_op1_data;
assign exe_reg_op2_data = uut.core.exe_reg_op2_data;
assign exe_alu_out = uut.core.exe_alu_out;
assign exe_reg_exe_fun = uut.core.exe_reg_exe_fun;
assign exe_br_flg = uut.core.exe_br_flg;
assign stall_flg = uut.core.stall_flg;
assign mem_reg_alu_out = uut.core.mem_reg_alu_out;
assign reg_r8 = uut.core.regfile_ext.Memory[8];
assign reg_r10 = uut.core.regfile_ext.Memory[10];
assign reg_r16 = uut.core.regfile_ext.Memory[16];
assign reg_r18 = uut.core.regfile_ext.Memory[18];
initial begin
clock = 0;
forever
#5 clock = ~clock; // 10ns周期，50MHz时钟
forever #5 clock = ~clock; // 10ns
end
initial begin
@ -49,68 +77,31 @@ module tb_Top();
reset = 0;
#1000;
$display("Simulation finished.");
$finish;
end
always @(posedge clock) begin
if (!reset) begin
// 打印当前PC值和指令
if (uut.core.io_imem_inst !== 32'hx) begin
$display("Time: %0t | PC: %h | Instruction: %h", $time, uut.core.if_reg_pc, uut.core.io_imem_inst);
end
// 打印ALU输入操作数和计算结果
if (uut.core.exe_alu_out !== 32'hx) begin
$display("Time: %0t | ALU Op1: %h | ALU Op2: %h | ALU Result: %h | ALU Fun: %h",
$time, uut.core.exe_reg_op1_data, uut.core.exe_reg_op2_data,
uut.core.exe_alu_out, uut.core.exe_reg_exe_fun);
end
// 打印寄存器文件读写操作
if (uut.core.regfile_ext.W0_en && uut.core.regfile_ext.W0_addr !== 5'hx) begin
$display("Time: %0t | RegFile Write | Addr: %h | Data: %h",
$time, uut.core.regfile_ext.W0_addr, uut.core.regfile_ext.W0_data);
end
if (uut.core.regfile_ext.R0_en && uut.core.regfile_ext.R0_addr !== 5'hx) begin
$display("Time: %0t | RegFile Read R0 | Addr: %h | Data: %h",
$time, uut.core.regfile_ext.R0_addr, uut.core.regfile_ext.R0_data);
end
if (uut.core.regfile_ext.R1_en && uut.core.regfile_ext.R1_addr !== 5'hx) begin
$display("Time: %0t | RegFile Read R1 | Addr: %h | Data: %h",
$time, uut.core.regfile_ext.R1_addr, uut.core.regfile_ext.R1_data);
end
// 打印内存读写操作
if (uut.memory.io_dmem_wen) begin
$display("Time: %0t | Memory Write | Addr: %h | Data: %h",
$time, uut.memory.io_dmem_addr, uut.memory.io_dmem_wdata);
end
if (uut.memory.io_dmem_rdata !== 32'hx) begin
$display("Time: %0t | Memory Read | Addr: %h | Data: %h",
$time, uut.memory.io_dmem_addr, uut.memory.io_dmem_rdata);
end
// 打印流水线各阶段的状态
$display("Time: %0t | IF Stage | PC: %h | Instruction: %h",
$time, uut.core.if_reg_pc, uut.core.io_imem_inst);
$display("Time: %0t | ID Stage | PC: %h | Instruction: %h | Op1: %h | Op2: %h",
$time, uut.core.id_reg_pc, uut.core.id_reg_inst,
uut.core.exe_reg_op1_data, uut.core.exe_reg_op2_data);
$display("Time: %0t | EXE Stage | PC: %h | ALU Result: %h",
$time, uut.core.exe_reg_pc, uut.core.exe_alu_out);
$display("Time: %0t | MEM Stage | PC: %h | Mem Addr: %h | Mem Data: %h",
$time, uut.core.mem_reg_pc, uut.memory.io_dmem_addr, uut.memory.io_dmem_rdata);
$display("Time: %0t | WB Stage | PC: %h | WB Addr: %h | WB Data: %h",
$time, uut.core.wb_reg_wb_addr, uut.core.wb_reg_wb_addr, uut.core.wb_reg_wb_data);
$display("Cycle: %0d", $time / 10);
$display("if_reg_pc: %h", if_reg_pc);
$display("id_reg_pc: %h", id_reg_pc);
$display("if_inst: %h", _memory_io_imem_inst);
$display("id_inst: %h", id_inst);
$display("id_reg_inst: %h", id_reg_inst);
$display("exe_reg_op1_data: %h", exe_reg_op1_data);
$display("exe_reg_op2_data: %h", exe_reg_op2_data);
$display("exe_reg_exe_fun: %h", exe_reg_exe_fun);
$display("exe_alu_out: %h", exe_alu_out);
$display("exe_br_flg: %h", exe_br_flg);
$display("stall_flg: %h", stall_flg);
$display("mem_reg_alu_out: %h", mem_reg_alu_out);
$display("Registers:");
$display("R%0d: %h", 8, reg_r8);
$display("R%0d: %h", 10, reg_r10);
$display("R%0d: %h", 16, reg_r16);
$display("R%0d: %h", 18, reg_r18);
$display("-----------------------------");
end
end
initial begin
$dumpfile("waveform.vcd");
$dumpvars(0, tb_Top); // 记录所有信号
end
endmodule
endmodule