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Fix bugs in Sicore

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This commit is contained in:
CGH0S7
2024-12-31 09:28:33 +08:00
parent b4cb98d8a9
commit c5eba63085
165 changed files with 645 additions and 650 deletions
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@ -51,30 +51,31 @@ module Core(
wire [31:0] _regfile_ext_R1_data;
reg [31:0] pc_reg;
wire [31:0] _pc_plus4_T = pc_reg + 32'h4;
wire [9:0] _GEN = {io_imem_inst[31:28], io_imem_inst[5:0]};
wire jmp_flg = io_imem_inst[31:28] == 4'h3 | _GEN == 10'h8;
wire [31:0] rs_data = (|(io_imem_inst[25:21])) ? _regfile_ext_R1_data : 32'h0;
wire [31:0] rt_data = (|(io_imem_inst[20:16])) ? _regfile_ext_R0_data : 32'h0;
wire [11:0] _GEN_0 = {io_imem_inst[31:26], io_imem_inst[5:0]};
wire _csignals_T_5 = _GEN_0 == 12'h20;
wire _csignals_T_7 = io_imem_inst[31:28] == 4'h8;
wire _csignals_T_9 = _GEN_0 == 12'h22;
wire _csignals_T_11 = _GEN_0 == 12'h24;
wire _csignals_T_13 = _GEN_0 == 12'h25;
wire _csignals_T_15 = _GEN_0 == 12'h26;
wire _csignals_T_17 = io_imem_inst[31:28] == 4'hC;
wire _csignals_T_19 = io_imem_inst[31:28] == 4'hD;
wire _csignals_T_21 = _GEN_0 == 12'h2A;
wire _csignals_T_23 = io_imem_inst[31:28] == 4'h4;
wire _csignals_T_25 = io_imem_inst[31:28] == 4'h5;
wire [16:0] _GEN_1 = {io_imem_inst[31:21], io_imem_inst[5:0]};
wire _csignals_T_27 = _GEN_1 == 17'h0;
wire _csignals_T_29 = _GEN_1 == 17'h2;
wire _csignals_T_31 = _GEN_1 == 17'h3;
wire _csignals_T_33 = io_imem_inst[31:28] == 4'h3;
wire _csignals_T_35 = _GEN == 10'h8;
wire [11:0] _GEN = {io_imem_inst[31:26], io_imem_inst[5:0]};
wire jmp_flg = io_imem_inst[31:26] == 6'h3 | _GEN == 12'h8;
wire [31:0] rs_data = (|(io_imem_inst[25:21])) ? _regfile_ext_R0_data : 32'h0;
wire [31:0] rt_data = (|(io_imem_inst[20:16])) ? _regfile_ext_R1_data : 32'h0;
wire _csignals_T_1 = io_imem_inst[31:26] == 6'h23;
wire _csignals_T_3 = io_imem_inst[31:26] == 6'h2B;
wire _csignals_T_5 = _GEN == 12'h20;
wire _csignals_T_7 = io_imem_inst[31:26] == 6'h8;
wire _csignals_T_9 = _GEN == 12'h22;
wire _csignals_T_11 = _GEN == 12'h24;
wire _csignals_T_13 = _GEN == 12'h25;
wire _csignals_T_15 = _GEN == 12'h26;
wire _csignals_T_17 = io_imem_inst[31:26] == 6'hC;
wire _csignals_T_19 = io_imem_inst[31:26] == 6'hD;
wire _csignals_T_21 = _GEN == 12'h2A;
wire _csignals_T_23 = io_imem_inst[31:26] == 6'h4;
wire _csignals_T_25 = io_imem_inst[31:26] == 6'h5;
wire [16:0] _GEN_0 = {io_imem_inst[31:21], io_imem_inst[5:0]};
wire _csignals_T_27 = _GEN_0 == 17'h0;
wire _csignals_T_29 = _GEN_0 == 17'h2;
wire _csignals_T_31 = _GEN_0 == 17'h3;
wire _csignals_T_33 = io_imem_inst[31:26] == 6'h3;
wire _csignals_T_35 = _GEN == 12'h8;
wire [4:0] csignals_0 =
_csignals_T_5 | _csignals_T_7
_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7
? 5'h1
: _csignals_T_9
? 5'h2
@ -103,38 +104,56 @@ module Core(
: _csignals_T_33
? 5'h1
: _csignals_T_35 ? 5'hD : 5'h0;
wire _GEN_2 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31;
wire _GEN_3 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_2;
wire _GEN_1 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31;
wire _GEN_2 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_1;
wire [1:0] csignals_1 =
_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3 | ~_csignals_T_33
_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7 | _csignals_T_9
| _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17 | _csignals_T_19
| _GEN_2 | ~_csignals_T_33
? 2'h1
: 2'h2;
wire [2:0] _csignals_T_85 =
_csignals_T_5
? 3'h1
: _csignals_T_7
? 3'h2
: _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
? 3'h1
: _csignals_T_17 | _csignals_T_19
? 3'h2
: _GEN_3 ? 3'h1 : _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35};
wire _GEN_4 = _csignals_T_23 | _csignals_T_25;
wire _GEN_5 =
wire [2:0] csignals_2 =
_csignals_T_1 | _csignals_T_3
? 3'h2
: _csignals_T_5
? 3'h1
: _csignals_T_7
? 3'h2
: _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
? 3'h1
: _csignals_T_17 | _csignals_T_19
? 3'h2
: _GEN_2 ? 3'h1 : _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35};
wire _GEN_3 = _csignals_T_23 | _csignals_T_25;
wire _GEN_4 =
_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21;
wire [1:0] _csignals_T_136 =
_GEN_5 ? 2'h1 : _GEN_4 ? 2'h0 : _GEN_2 ? 2'h1 : {2{_csignals_T_33}};
wire [1:0] csignals_4 =
_csignals_T_1
? 2'h1
: _csignals_T_3
? 2'h0
: _GEN_4
? 2'h1
: _GEN_3
? 2'h0
: {1'h0,
_csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33};
wire [2:0] csignals_5 =
_csignals_T_1
? 3'h2
: _csignals_T_3
? 3'h0
: _GEN_4 ? 3'h1 : _GEN_3 ? 3'h0 : _GEN_1 ? 3'h1 : _csignals_T_33 ? 3'h3 : 3'h0;
wire _op1_data_T = csignals_1 == 2'h1;
wire _op1_data_T_1 = csignals_1 == 2'h2;
wire [31:0] op1_data = _op1_data_T ? rs_data : _op1_data_T_1 ? pc_reg : 32'h0;
wire [31:0] op2_data =
_csignals_T_85 == 3'h1
csignals_2 == 3'h1
? rt_data
: _csignals_T_85 == 3'h2
: csignals_2 == 3'h2
? {{16{io_imem_inst[15]}}, io_imem_inst[15:0]}
: _csignals_T_85 == 3'h4 ? {4'h0, io_imem_inst[25:0], 2'h0} : 32'h0;
: csignals_2 == 3'h4 ? {4'h0, io_imem_inst[25:0], 2'h0} : 32'h0;
wire _alu_out_T = csignals_0 == 5'h1;
wire [31:0] _alu_out_T_1 = op1_data + op2_data;
wire _alu_out_T_3 = csignals_0 == 5'h2;
@ -148,13 +167,13 @@ module Core(
wire _alu_out_T_12 = csignals_0 == 5'h6;
wire [62:0] _alu_out_T_14 = {31'h0, op1_data} << op2_data[4:0];
wire _alu_out_T_16 = csignals_0 == 5'h7;
wire [31:0] _GEN_6 = {27'h0, op2_data[4:0]};
wire [31:0] _alu_out_T_18 = op1_data >> _GEN_6;
wire [31:0] _GEN_5 = {27'h0, op2_data[4:0]};
wire [31:0] _alu_out_T_18 = op1_data >> _GEN_5;
wire _alu_out_T_19 = csignals_0 == 5'h8;
wire [31:0] _alu_out_T_22 = $signed($signed(op1_data) >>> _GEN_6);
wire [31:0] _alu_out_T_22 = $signed($signed(op1_data) >>> _GEN_5);
wire _alu_out_T_24 = csignals_0 == 5'h9;
wire _alu_out_T_28 = csignals_0 == 5'hD;
wire [31:0] _GEN_7 = {31'h0, $signed(op1_data) < $signed(op2_data)};
wire [31:0] _GEN_6 = {31'h0, $signed(op1_data) < $signed(op2_data)};
wire [31:0] alu_out =
_alu_out_T
? _alu_out_T_1
@ -173,24 +192,34 @@ module Core(
: _alu_out_T_19
? _alu_out_T_22
: _alu_out_T_24
? _GEN_7
? _GEN_6
: _alu_out_T_28 ? op1_data : 32'h0;
wire _br_flg_T_3 = op1_data == op2_data;
wire br_flg =
csignals_0 == 5'hB ? _br_flg_T_3 : csignals_0 == 5'hC & ~_br_flg_T_3;
wire [31:0] br_target = {{14{io_imem_inst[15]}}, io_imem_inst[15:0], 2'h0} + pc_reg;
wire [31:0] wb_data =
_csignals_T_136 == 2'h2 ? io_dmem_rdata : (&_csignals_T_136) ? _pc_plus4_T : alu_out;
csignals_5 == 3'h2 ? io_dmem_rdata : csignals_5 == 3'h3 ? _pc_plus4_T : alu_out;
wire [4:0] wb_addr =
csignals_5 == 3'h1 & io_imem_inst[31:26] == 6'h0
? io_imem_inst[15:11]
: io_imem_inst[31:26] == 6'h3 ? 5'h1F : io_imem_inst[20:16];
`ifndef SYNTHESIS
always @(posedge clock) begin
if ((`PRINTF_COND_) & ~reset) begin
$fwrite(32'h80000002, "---------------\n");
$fwrite(32'h80000002, "io.pc: 0x%x\ninst: 0x%x \n", pc_reg, io_imem_inst);
$fwrite(32'h80000002, "io.imem.inst: 0x%x\n", io_imem_inst);
$fwrite(32'h80000002, "io.pc: 0x%x\ninst: 0x%b \n", pc_reg, io_imem_inst);
$fwrite(32'h80000002, "pc_next: 0x%x\n",
br_flg ? br_target : jmp_flg ? alu_out : _pc_plus4_T);
$fwrite(32'h80000002, "exe_fun: 0x%x\n", csignals_0);
$fwrite(32'h80000002, "rs_addr: 0x%x\n", io_imem_inst[25:21]);
$fwrite(32'h80000002, "rt_addr: 0x%x\n", io_imem_inst[20:16]);
$fwrite(32'h80000002, "rd_addr: 0x%x\n", io_imem_inst[15:11]);
$fwrite(32'h80000002, "reg: 0x%x\n", _regfile_ext_R1_data);
$fwrite(32'h80000002, "rf_wen: 0x%x\n", csignals_4);
$fwrite(32'h80000002, "rs_data: 0x%x\n", rs_data);
$fwrite(32'h80000002, "rt_data: 0x%x\n", rt_data);
$fwrite(32'h80000002, "wb_data: 0x%x\n", wb_data);
$fwrite(32'h80000002, "---------------\n");
end
@ -219,7 +248,7 @@ module Core(
else if (_alu_out_T_19)
pc_reg <= _alu_out_T_22;
else if (_alu_out_T_24)
pc_reg <= _GEN_7;
pc_reg <= _GEN_6;
else if (_alu_out_T_28) begin
if (_op1_data_T)
pc_reg <= rs_data;
@ -233,24 +262,22 @@ module Core(
pc_reg <= _pc_plus4_T;
end // always @(posedge)
regfile_32x32 regfile_ext (
.R0_addr (io_imem_inst[20:16]),
.R0_addr (io_imem_inst[25:21]),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_regfile_ext_R0_data),
.R1_addr (io_imem_inst[25:21]),
.R1_addr (io_imem_inst[20:16]),
.R1_en (1'h1),
.R1_clk (clock),
.R1_data (_regfile_ext_R1_data),
.W0_addr (io_imem_inst[15:11]),
.W0_en
(_GEN_5 | ~_GEN_4
& (_csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33)),
.W0_addr (wb_addr),
.W0_en (csignals_4 == 2'h1 & (|wb_addr)),
.W0_clk (clock),
.W0_data (wb_data)
);
assign io_imem_addr = pc_reg;
assign io_dmem_addr = alu_out;
assign io_dmem_wen = 1'h0;
assign io_dmem_wen = ~_csignals_T_1 & _csignals_T_3;
assign io_dmem_wdata = rt_data;
assign io_exit = io_imem_inst == 32'h114514;
endmodule
@ -320,7 +347,7 @@ module mem_4096x8(
end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_
initial
$readmemh("src/hex/addi.hex", Memory);
$readmemh("src/hex/mem.hex", Memory);
`endif // ENABLE_INITIAL_MEM_
assign R0_data = R0_en ? Memory[R0_addr] : 8'bx;
assign R1_data = R1_en ? Memory[R1_addr] : 8'bx;