Fix bugs in Sicore
This commit is contained in:
@ -50,83 +50,79 @@ circuit TopOrigin :
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reset => (UInt<1>("h0"), exe_reg_imm_b_sext) @[src/main/scala/micore/Core.scala 34:35]
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reg exe_reg_imm_u_shifted : UInt<32>, clock with :
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reset => (UInt<1>("h0"), exe_reg_imm_u_shifted) @[src/main/scala/micore/Core.scala 35:38]
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reg exe_reg_imm_z_uext : UInt<32>, clock with :
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reset => (UInt<1>("h0"), exe_reg_imm_z_uext) @[src/main/scala/micore/Core.scala 36:35]
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reg mem_reg_pc : UInt<32>, clock with :
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reset => (UInt<1>("h0"), mem_reg_pc) @[src/main/scala/micore/Core.scala 39:27]
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reset => (UInt<1>("h0"), mem_reg_pc) @[src/main/scala/micore/Core.scala 38:27]
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reg mem_reg_wb_addr : UInt<5>, clock with :
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reset => (UInt<1>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 40:32]
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reset => (UInt<1>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 39:32]
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reg mem_reg_op1_data : UInt<32>, clock with :
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reset => (UInt<1>("h0"), mem_reg_op1_data) @[src/main/scala/micore/Core.scala 41:33]
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reset => (UInt<1>("h0"), mem_reg_op1_data) @[src/main/scala/micore/Core.scala 40:33]
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reg mem_reg_rs2_data : UInt<32>, clock with :
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reset => (UInt<1>("h0"), mem_reg_rs2_data) @[src/main/scala/micore/Core.scala 42:33]
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reset => (UInt<1>("h0"), mem_reg_rs2_data) @[src/main/scala/micore/Core.scala 41:33]
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reg mem_reg_mem_wen : UInt<2>, clock with :
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reset => (UInt<1>("h0"), mem_reg_mem_wen) @[src/main/scala/micore/Core.scala 43:32]
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reset => (UInt<1>("h0"), mem_reg_mem_wen) @[src/main/scala/micore/Core.scala 42:32]
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reg mem_reg_rf_wen : UInt<2>, clock with :
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reset => (UInt<1>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 44:31]
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reset => (UInt<1>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 43:31]
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reg mem_reg_wb_sel : UInt<3>, clock with :
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reset => (UInt<1>("h0"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 45:31]
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reg mem_reg_imm_z_uext : UInt<32>, clock with :
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reset => (UInt<1>("h0"), mem_reg_imm_z_uext) @[src/main/scala/micore/Core.scala 46:35]
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reset => (UInt<1>("h0"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 44:31]
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reg mem_reg_alu_out : UInt<32>, clock with :
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reset => (UInt<1>("h0"), mem_reg_alu_out) @[src/main/scala/micore/Core.scala 47:32]
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reset => (UInt<1>("h0"), mem_reg_alu_out) @[src/main/scala/micore/Core.scala 45:32]
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reg wb_reg_wb_addr : UInt<5>, clock with :
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reset => (UInt<1>("h0"), wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 50:31]
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reset => (UInt<1>("h0"), wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 48:31]
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reg wb_reg_rf_wen : UInt<2>, clock with :
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reset => (UInt<1>("h0"), wb_reg_rf_wen) @[src/main/scala/micore/Core.scala 51:30]
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reset => (UInt<1>("h0"), wb_reg_rf_wen) @[src/main/scala/micore/Core.scala 49:30]
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reg wb_reg_wb_data : UInt<32>, clock with :
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reset => (UInt<1>("h0"), wb_reg_wb_data) @[src/main/scala/micore/Core.scala 52:31]
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reset => (UInt<1>("h0"), wb_reg_wb_data) @[src/main/scala/micore/Core.scala 50:31]
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reg if_reg_pc : UInt<32>, clock with :
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reset => (UInt<1>("h0"), if_reg_pc) @[src/main/scala/micore/Core.scala 55:26]
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node _if_pc_plus4_T = add(if_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 65:31]
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node if_pc_plus4 = tail(_if_pc_plus4_T, 1) @[src/main/scala/micore/Core.scala 65:31]
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node _id_rs1_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 92:21]
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node id_rs1_addr_b = bits(id_reg_inst, 25, 21) @[src/main/scala/micore/Core.scala 87:34]
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node _id_rs1_data_hazard_T_1 = neq(id_rs1_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 92:50]
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node _id_rs1_data_hazard_T_2 = and(_id_rs1_data_hazard_T, _id_rs1_data_hazard_T_1) @[src/main/scala/micore/Core.scala 92:32]
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node _id_rs1_data_hazard_T_3 = eq(id_rs1_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 92:77]
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node id_rs1_data_hazard = and(_id_rs1_data_hazard_T_2, _id_rs1_data_hazard_T_3) @[src/main/scala/micore/Core.scala 92:59]
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node _id_rs2_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 94:21]
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node id_rs2_addr_b = bits(id_reg_inst, 20, 16) @[src/main/scala/micore/Core.scala 88:34]
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node _id_rs2_data_hazard_T_1 = neq(id_rs2_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 94:50]
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node _id_rs2_data_hazard_T_2 = and(_id_rs2_data_hazard_T, _id_rs2_data_hazard_T_1) @[src/main/scala/micore/Core.scala 94:32]
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node _id_rs2_data_hazard_T_3 = eq(id_rs2_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 94:77]
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node id_rs2_data_hazard = and(_id_rs2_data_hazard_T_2, _id_rs2_data_hazard_T_3) @[src/main/scala/micore/Core.scala 94:59]
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node _stall_flg_T = or(id_rs1_data_hazard, id_rs2_data_hazard) @[src/main/scala/micore/Core.scala 95:36]
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node stall_flg = _stall_flg_T @[src/main/scala/micore/Core.scala 59:23 95:13]
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reset => (UInt<1>("h0"), if_reg_pc) @[src/main/scala/micore/Core.scala 53:26]
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node _if_pc_plus4_T = add(if_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 63:31]
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node if_pc_plus4 = tail(_if_pc_plus4_T, 1) @[src/main/scala/micore/Core.scala 63:31]
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node _id_rs1_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 90:21]
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node id_rs1_addr_b = bits(id_reg_inst, 25, 21) @[src/main/scala/micore/Core.scala 85:34]
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node _id_rs1_data_hazard_T_1 = neq(id_rs1_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 90:50]
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node _id_rs1_data_hazard_T_2 = and(_id_rs1_data_hazard_T, _id_rs1_data_hazard_T_1) @[src/main/scala/micore/Core.scala 90:32]
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node _id_rs1_data_hazard_T_3 = eq(id_rs1_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 90:77]
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node id_rs1_data_hazard = and(_id_rs1_data_hazard_T_2, _id_rs1_data_hazard_T_3) @[src/main/scala/micore/Core.scala 90:59]
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node _id_rs2_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 92:21]
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node id_rs2_addr_b = bits(id_reg_inst, 20, 16) @[src/main/scala/micore/Core.scala 86:34]
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node _id_rs2_data_hazard_T_1 = neq(id_rs2_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 92:50]
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node _id_rs2_data_hazard_T_2 = and(_id_rs2_data_hazard_T, _id_rs2_data_hazard_T_1) @[src/main/scala/micore/Core.scala 92:32]
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node _id_rs2_data_hazard_T_3 = eq(id_rs2_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 92:77]
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node id_rs2_data_hazard = and(_id_rs2_data_hazard_T_2, _id_rs2_data_hazard_T_3) @[src/main/scala/micore/Core.scala 92:59]
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node _stall_flg_T = or(id_rs1_data_hazard, id_rs2_data_hazard) @[src/main/scala/micore/Core.scala 93:36]
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node stall_flg = _stall_flg_T @[src/main/scala/micore/Core.scala 57:23 93:13]
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node _if_pc_next_T = mux(stall_flg, if_reg_pc, if_pc_plus4) @[src/main/scala/chisel3/util/Mux.scala 126:16]
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node _exe_jmp_flg_T = eq(exe_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 239:34]
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node exe_jmp_flg = _exe_jmp_flg_T @[src/main/scala/micore/Core.scala 239:15 62:25]
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node _exe_alu_out_T = eq(exe_reg_exe_fun, UInt<5>("h1")) @[src/main/scala/micore/Core.scala 204:24]
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node _exe_alu_out_T_1 = add(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 204:58]
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node _exe_alu_out_T_2 = tail(_exe_alu_out_T_1, 1) @[src/main/scala/micore/Core.scala 204:58]
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node _exe_alu_out_T_3 = eq(exe_reg_exe_fun, UInt<5>("h2")) @[src/main/scala/micore/Core.scala 205:24]
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node _exe_alu_out_T_4 = sub(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 205:58]
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node _exe_alu_out_T_5 = tail(_exe_alu_out_T_4, 1) @[src/main/scala/micore/Core.scala 205:58]
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node _exe_alu_out_T_6 = eq(exe_reg_exe_fun, UInt<5>("h3")) @[src/main/scala/micore/Core.scala 206:24]
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node _exe_alu_out_T_7 = and(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 206:58]
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node _exe_alu_out_T_8 = eq(exe_reg_exe_fun, UInt<5>("h4")) @[src/main/scala/micore/Core.scala 207:24]
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node _exe_alu_out_T_9 = or(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 207:57]
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node _exe_alu_out_T_10 = eq(exe_reg_exe_fun, UInt<5>("h5")) @[src/main/scala/micore/Core.scala 208:24]
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node _exe_alu_out_T_11 = xor(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 208:58]
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node _exe_alu_out_T_12 = eq(exe_reg_exe_fun, UInt<5>("h6")) @[src/main/scala/micore/Core.scala 209:24]
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node _exe_alu_out_T_13 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 209:77]
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node _exe_alu_out_T_14 = dshl(exe_reg_op1_data, _exe_alu_out_T_13) @[src/main/scala/micore/Core.scala 209:58]
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node _exe_alu_out_T_15 = bits(_exe_alu_out_T_14, 31, 0) @[src/main/scala/micore/Core.scala 212:9]
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node _exe_alu_out_T_16 = eq(exe_reg_exe_fun, UInt<5>("h7")) @[src/main/scala/micore/Core.scala 213:24]
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node _exe_alu_out_T_17 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 213:77]
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node _exe_alu_out_T_18 = dshr(exe_reg_op1_data, _exe_alu_out_T_17) @[src/main/scala/micore/Core.scala 213:58]
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node _exe_alu_out_T_19 = eq(exe_reg_exe_fun, UInt<5>("h8")) @[src/main/scala/micore/Core.scala 217:24]
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node _exe_alu_out_T_20 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 217:58]
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node _exe_alu_out_T_21 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 217:84]
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node _exe_alu_out_T_22 = dshr(_exe_alu_out_T_20, _exe_alu_out_T_21) @[src/main/scala/micore/Core.scala 217:65]
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node _exe_alu_out_T_23 = asUInt(_exe_alu_out_T_22) @[src/main/scala/micore/Core.scala 220:10]
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node _exe_alu_out_T_24 = eq(exe_reg_exe_fun, UInt<5>("h9")) @[src/main/scala/micore/Core.scala 221:24]
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node _exe_alu_out_T_25 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 221:58]
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node _exe_alu_out_T_26 = asSInt(exe_reg_op2_data) @[src/main/scala/micore/Core.scala 221:84]
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node _exe_alu_out_T_27 = lt(_exe_alu_out_T_25, _exe_alu_out_T_26) @[src/main/scala/micore/Core.scala 221:65]
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node _exe_alu_out_T_28 = eq(exe_reg_exe_fun, UInt<5>("ha")) @[src/main/scala/micore/Core.scala 222:24]
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node _exe_alu_out_T_29 = lt(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 222:59]
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node _exe_jmp_flg_T = eq(exe_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 243:34]
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node exe_jmp_flg = _exe_jmp_flg_T @[src/main/scala/micore/Core.scala 243:15 60:25]
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node _exe_alu_out_T = eq(exe_reg_exe_fun, UInt<5>("h1")) @[src/main/scala/micore/Core.scala 211:24]
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node _exe_alu_out_T_1 = add(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 211:58]
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node _exe_alu_out_T_2 = tail(_exe_alu_out_T_1, 1) @[src/main/scala/micore/Core.scala 211:58]
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node _exe_alu_out_T_3 = eq(exe_reg_exe_fun, UInt<5>("h2")) @[src/main/scala/micore/Core.scala 212:24]
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node _exe_alu_out_T_4 = sub(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 212:58]
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node _exe_alu_out_T_5 = tail(_exe_alu_out_T_4, 1) @[src/main/scala/micore/Core.scala 212:58]
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node _exe_alu_out_T_6 = eq(exe_reg_exe_fun, UInt<5>("h3")) @[src/main/scala/micore/Core.scala 213:24]
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node _exe_alu_out_T_7 = and(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 213:58]
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node _exe_alu_out_T_8 = eq(exe_reg_exe_fun, UInt<5>("h4")) @[src/main/scala/micore/Core.scala 214:24]
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node _exe_alu_out_T_9 = or(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 214:57]
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node _exe_alu_out_T_10 = eq(exe_reg_exe_fun, UInt<5>("h5")) @[src/main/scala/micore/Core.scala 215:24]
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node _exe_alu_out_T_11 = xor(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 215:58]
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node _exe_alu_out_T_12 = eq(exe_reg_exe_fun, UInt<5>("h6")) @[src/main/scala/micore/Core.scala 216:24]
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node _exe_alu_out_T_13 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 216:77]
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node _exe_alu_out_T_14 = dshl(exe_reg_op1_data, _exe_alu_out_T_13) @[src/main/scala/micore/Core.scala 216:58]
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node _exe_alu_out_T_15 = bits(_exe_alu_out_T_14, 31, 0) @[src/main/scala/micore/Core.scala 219:9]
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node _exe_alu_out_T_16 = eq(exe_reg_exe_fun, UInt<5>("h7")) @[src/main/scala/micore/Core.scala 220:24]
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node _exe_alu_out_T_17 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 220:77]
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node _exe_alu_out_T_18 = dshr(exe_reg_op1_data, _exe_alu_out_T_17) @[src/main/scala/micore/Core.scala 220:58]
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node _exe_alu_out_T_19 = eq(exe_reg_exe_fun, UInt<5>("h8")) @[src/main/scala/micore/Core.scala 224:24]
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node _exe_alu_out_T_20 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 224:58]
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node _exe_alu_out_T_21 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 224:84]
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node _exe_alu_out_T_22 = dshr(_exe_alu_out_T_20, _exe_alu_out_T_21) @[src/main/scala/micore/Core.scala 224:65]
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node _exe_alu_out_T_23 = asUInt(_exe_alu_out_T_22) @[src/main/scala/micore/Core.scala 227:10]
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node _exe_alu_out_T_24 = eq(exe_reg_exe_fun, UInt<5>("h9")) @[src/main/scala/micore/Core.scala 228:24]
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node _exe_alu_out_T_25 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 228:58]
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node _exe_alu_out_T_26 = asSInt(exe_reg_op2_data) @[src/main/scala/micore/Core.scala 228:84]
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node _exe_alu_out_T_27 = lt(_exe_alu_out_T_25, _exe_alu_out_T_26) @[src/main/scala/micore/Core.scala 228:65]
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node _exe_alu_out_T_28 = eq(exe_reg_exe_fun, UInt<5>("ha")) @[src/main/scala/micore/Core.scala 229:24]
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node _exe_alu_out_T_29 = lt(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 229:59]
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node _exe_alu_out_T_30 = mux(_exe_alu_out_T_28, _exe_alu_out_T_29, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
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node _exe_alu_out_T_31 = mux(_exe_alu_out_T_24, _exe_alu_out_T_27, _exe_alu_out_T_30) @[src/main/scala/chisel3/util/Mux.scala 126:16]
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node _exe_alu_out_T_32 = mux(_exe_alu_out_T_19, _exe_alu_out_T_23, _exe_alu_out_T_31) @[src/main/scala/chisel3/util/Mux.scala 126:16]
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@ -137,83 +133,90 @@ circuit TopOrigin :
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node _exe_alu_out_T_37 = mux(_exe_alu_out_T_6, _exe_alu_out_T_7, _exe_alu_out_T_36) @[src/main/scala/chisel3/util/Mux.scala 126:16]
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node _exe_alu_out_T_38 = mux(_exe_alu_out_T_3, _exe_alu_out_T_5, _exe_alu_out_T_37) @[src/main/scala/chisel3/util/Mux.scala 126:16]
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node _exe_alu_out_T_39 = mux(_exe_alu_out_T, _exe_alu_out_T_2, _exe_alu_out_T_38) @[src/main/scala/chisel3/util/Mux.scala 126:16]
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node exe_alu_out = _exe_alu_out_T_39 @[src/main/scala/micore/Core.scala 201:15 63:25]
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node exe_alu_out = _exe_alu_out_T_39 @[src/main/scala/micore/Core.scala 208:15 61:25]
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node _if_pc_next_T_1 = mux(exe_jmp_flg, exe_alu_out, _if_pc_next_T) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _exe_br_flg_T = eq(exe_reg_exe_fun, UInt<5>("hb")) @[src/main/scala/micore/Core.scala 232:24]
|
||||
node _exe_br_flg_T_1 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 232:57]
|
||||
node _exe_br_flg_T_2 = eq(exe_reg_exe_fun, UInt<5>("hc")) @[src/main/scala/micore/Core.scala 233:24]
|
||||
node _exe_br_flg_T_3 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 233:58]
|
||||
node _exe_br_flg_T_4 = eq(_exe_br_flg_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 233:39]
|
||||
node _exe_br_flg_T = eq(exe_reg_exe_fun, UInt<5>("hb")) @[src/main/scala/micore/Core.scala 236:24]
|
||||
node _exe_br_flg_T_1 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 236:57]
|
||||
node _exe_br_flg_T_2 = eq(exe_reg_exe_fun, UInt<5>("hc")) @[src/main/scala/micore/Core.scala 237:24]
|
||||
node _exe_br_flg_T_3 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 237:58]
|
||||
node _exe_br_flg_T_4 = eq(_exe_br_flg_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 237:39]
|
||||
node _exe_br_flg_T_5 = mux(_exe_br_flg_T_2, _exe_br_flg_T_4, UInt<1>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _exe_br_flg_T_6 = mux(_exe_br_flg_T, _exe_br_flg_T_1, _exe_br_flg_T_5) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node exe_br_flg = _exe_br_flg_T_6 @[src/main/scala/micore/Core.scala 229:14 60:24]
|
||||
node _exe_br_target_T = add(exe_reg_pc, exe_reg_imm_b_sext) @[src/main/scala/micore/Core.scala 237:31]
|
||||
node _exe_br_target_T_1 = tail(_exe_br_target_T, 1) @[src/main/scala/micore/Core.scala 237:31]
|
||||
node exe_br_target = _exe_br_target_T_1 @[src/main/scala/micore/Core.scala 237:17 61:27]
|
||||
node exe_br_flg = _exe_br_flg_T_6 @[src/main/scala/micore/Core.scala 233:14 58:24]
|
||||
node _exe_br_target_T = add(exe_reg_pc, exe_reg_imm_b_sext) @[src/main/scala/micore/Core.scala 241:31]
|
||||
node _exe_br_target_T_1 = tail(_exe_br_target_T, 1) @[src/main/scala/micore/Core.scala 241:31]
|
||||
node exe_br_target = _exe_br_target_T_1 @[src/main/scala/micore/Core.scala 241:17 59:27]
|
||||
node if_pc_next = mux(exe_br_flg, exe_br_target, _if_pc_next_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _id_reg_pc_T = mux(stall_flg, id_reg_pc, if_reg_pc) @[src/main/scala/micore/Core.scala 77:19]
|
||||
node _id_reg_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 81:19]
|
||||
node _id_reg_pc_T = mux(stall_flg, id_reg_pc, if_reg_pc) @[src/main/scala/micore/Core.scala 75:19]
|
||||
node _id_reg_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 79:19]
|
||||
node _id_reg_inst_T_1 = mux(stall_flg, id_reg_inst, io_imem_inst) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _id_reg_inst_T_2 = mux(_id_reg_inst_T, UInt<32>("h20000000"), _id_reg_inst_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _id_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 98:21]
|
||||
node _id_inst_T_1 = or(_id_inst_T, stall_flg) @[src/main/scala/micore/Core.scala 98:36]
|
||||
node id_inst = mux(_id_inst_T_1, UInt<32>("h20000000"), id_reg_inst) @[src/main/scala/micore/Core.scala 98:8]
|
||||
node id_rs1_addr = bits(id_inst, 25, 21) @[src/main/scala/micore/Core.scala 100:28]
|
||||
node id_rs2_addr = bits(id_inst, 20, 16) @[src/main/scala/micore/Core.scala 101:28]
|
||||
node id_wb_addr = bits(id_inst, 15, 11) @[src/main/scala/micore/Core.scala 102:27]
|
||||
node _id_rs1_data_T = eq(id_rs1_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 108:20]
|
||||
node _id_rs1_data_T_1 = eq(id_rs1_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 109:21]
|
||||
node _id_rs1_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 109:61]
|
||||
node _id_rs1_data_T_3 = and(_id_rs1_data_T_1, _id_rs1_data_T_2) @[src/main/scala/micore/Core.scala 109:42]
|
||||
node _id_rs1_data_T_4 = eq(id_rs1_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 110:21]
|
||||
node _id_rs1_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 110:59]
|
||||
node _id_rs1_data_T_6 = and(_id_rs1_data_T_4, _id_rs1_data_T_5) @[src/main/scala/micore/Core.scala 110:41]
|
||||
node _id_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 96:21]
|
||||
node _id_inst_T_1 = or(_id_inst_T, stall_flg) @[src/main/scala/micore/Core.scala 96:36]
|
||||
node id_inst = mux(_id_inst_T_1, UInt<32>("h20000000"), id_reg_inst) @[src/main/scala/micore/Core.scala 96:8]
|
||||
node id_rs1_addr = bits(id_inst, 25, 21) @[src/main/scala/micore/Core.scala 98:28]
|
||||
node id_rs2_addr = bits(id_inst, 20, 16) @[src/main/scala/micore/Core.scala 99:28]
|
||||
node _id_wb_addr_T = bits(id_inst, 20, 16) @[src/main/scala/micore/Core.scala 102:12]
|
||||
node _id_wb_addr_T_1 = bits(id_inst, 31, 26) @[src/main/scala/micore/Core.scala 104:15]
|
||||
node _id_wb_addr_T_2 = eq(_id_wb_addr_T_1, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 104:24]
|
||||
node _id_wb_addr_T_3 = bits(id_inst, 15, 11) @[src/main/scala/micore/Core.scala 104:51]
|
||||
node _id_wb_addr_T_4 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/micore/Core.scala 108:16]
|
||||
node _id_wb_addr_T_5 = eq(UInt<28>("hc000000"), _id_wb_addr_T_4) @[src/main/scala/micore/Core.scala 108:16]
|
||||
node _id_wb_addr_T_6 = mux(_id_wb_addr_T_5, UInt<5>("h1f"), _id_wb_addr_T) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node id_wb_addr = mux(_id_wb_addr_T_2, _id_wb_addr_T_3, _id_wb_addr_T_6) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _id_rs1_data_T = eq(id_rs1_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 116:20]
|
||||
node _id_rs1_data_T_1 = eq(id_rs1_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 117:21]
|
||||
node _id_rs1_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 117:61]
|
||||
node _id_rs1_data_T_3 = and(_id_rs1_data_T_1, _id_rs1_data_T_2) @[src/main/scala/micore/Core.scala 117:42]
|
||||
node _id_rs1_data_T_4 = eq(id_rs1_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 118:21]
|
||||
node _id_rs1_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 118:59]
|
||||
node _id_rs1_data_T_6 = and(_id_rs1_data_T_4, _id_rs1_data_T_5) @[src/main/scala/micore/Core.scala 118:41]
|
||||
node _id_rs1_data_T_7 = mux(_id_rs1_data_T_6, wb_reg_wb_data, regfile.id_rs1_data_MPORT.data) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _mem_wb_data_T = eq(mem_reg_wb_sel, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 260:23]
|
||||
node _mem_wb_data_T_1 = eq(mem_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 261:23]
|
||||
node _mem_wb_data_T_2 = add(mem_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 261:49]
|
||||
node _mem_wb_data_T_3 = tail(_mem_wb_data_T_2, 1) @[src/main/scala/micore/Core.scala 261:49]
|
||||
node _mem_wb_data_T = eq(mem_reg_wb_sel, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 263:23]
|
||||
node _mem_wb_data_T_1 = eq(mem_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 264:23]
|
||||
node _mem_wb_data_T_2 = add(mem_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 264:49]
|
||||
node _mem_wb_data_T_3 = tail(_mem_wb_data_T_2, 1) @[src/main/scala/micore/Core.scala 264:49]
|
||||
node _mem_wb_data_T_4 = mux(_mem_wb_data_T_1, _mem_wb_data_T_3, mem_reg_alu_out) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _mem_wb_data_T_5 = mux(_mem_wb_data_T, io_dmem_rdata, _mem_wb_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node mem_wb_data = _mem_wb_data_T_5 @[src/main/scala/micore/Core.scala 104:25 257:15]
|
||||
node mem_wb_data = _mem_wb_data_T_5 @[src/main/scala/micore/Core.scala 112:25 260:15]
|
||||
node _id_rs1_data_T_8 = mux(_id_rs1_data_T_3, mem_wb_data, _id_rs1_data_T_7) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node id_rs1_data = mux(_id_rs1_data_T, UInt<32>("h0"), _id_rs1_data_T_8) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _id_rs2_data_T = eq(id_rs2_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 116:20]
|
||||
node _id_rs2_data_T_1 = eq(id_rs2_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 117:21]
|
||||
node _id_rs2_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 117:61]
|
||||
node _id_rs2_data_T_3 = and(_id_rs2_data_T_1, _id_rs2_data_T_2) @[src/main/scala/micore/Core.scala 117:42]
|
||||
node _id_rs2_data_T_4 = eq(id_rs2_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 118:21]
|
||||
node _id_rs2_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 118:59]
|
||||
node _id_rs2_data_T_6 = and(_id_rs2_data_T_4, _id_rs2_data_T_5) @[src/main/scala/micore/Core.scala 118:41]
|
||||
node _id_rs2_data_T = eq(id_rs2_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 124:20]
|
||||
node _id_rs2_data_T_1 = eq(id_rs2_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 125:21]
|
||||
node _id_rs2_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 125:61]
|
||||
node _id_rs2_data_T_3 = and(_id_rs2_data_T_1, _id_rs2_data_T_2) @[src/main/scala/micore/Core.scala 125:42]
|
||||
node _id_rs2_data_T_4 = eq(id_rs2_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 126:21]
|
||||
node _id_rs2_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 126:59]
|
||||
node _id_rs2_data_T_6 = and(_id_rs2_data_T_4, _id_rs2_data_T_5) @[src/main/scala/micore/Core.scala 126:41]
|
||||
node _id_rs2_data_T_7 = mux(_id_rs2_data_T_6, wb_reg_wb_data, regfile.id_rs2_data_MPORT.data) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _id_rs2_data_T_8 = mux(_id_rs2_data_T_3, mem_wb_data, _id_rs2_data_T_7) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node id_rs2_data = mux(_id_rs2_data_T, UInt<32>("h0"), _id_rs2_data_T_8) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node id_imm_i = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 122:25]
|
||||
node _id_imm_i_sext_T = bits(id_imm_i, 15, 15) @[src/main/scala/micore/Core.scala 123:44]
|
||||
node _id_imm_i_sext_T_1 = mux(_id_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 123:31]
|
||||
node id_imm_i_sext = cat(_id_imm_i_sext_T_1, id_imm_i) @[src/main/scala/micore/Core.scala 123:26]
|
||||
node _id_imm_b_T = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 125:12]
|
||||
node id_imm_b = cat(_id_imm_b_T, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 124:21]
|
||||
node _id_imm_b_sext_T = bits(id_imm_b, 17, 17) @[src/main/scala/micore/Core.scala 128:44]
|
||||
node _id_imm_b_sext_T_1 = mux(_id_imm_b_sext_T, UInt<14>("h3fff"), UInt<14>("h0")) @[src/main/scala/micore/Core.scala 128:31]
|
||||
node id_imm_b_sext = cat(_id_imm_b_sext_T_1, id_imm_b) @[src/main/scala/micore/Core.scala 128:26]
|
||||
node _id_imm_j_T = bits(id_inst, 25, 0) @[src/main/scala/micore/Core.scala 130:12]
|
||||
node id_imm_j = cat(_id_imm_j_T, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 129:21]
|
||||
node _id_imm_j_sext_T = bits(id_imm_j, 25, 25) @[src/main/scala/micore/Core.scala 133:43]
|
||||
node _id_imm_j_sext_T_1 = mux(_id_imm_j_sext_T, UInt<6>("h3f"), UInt<6>("h0")) @[src/main/scala/micore/Core.scala 133:31]
|
||||
node id_imm_j_sext = cat(_id_imm_j_sext_T_1, id_imm_j) @[src/main/scala/micore/Core.scala 133:26]
|
||||
node id_imm_u = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 134:25]
|
||||
node _id_imm_u_shifted_T = mux(UInt<1>("h0"), UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 135:44]
|
||||
node id_imm_u_shifted = cat(id_imm_u, _id_imm_u_shifted_T) @[src/main/scala/micore/Core.scala 135:29]
|
||||
node id_imm_shamt = bits(id_inst, 10, 6) @[src/main/scala/micore/Core.scala 136:29]
|
||||
node _csignals_T = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_1 = eq(UInt<34>("h230000000"), _csignals_T) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_2 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_3 = eq(UInt<34>("h2b0000000"), _csignals_T_2) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node id_imm_i = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 130:25]
|
||||
node _id_imm_i_sext_T = bits(id_imm_i, 15, 15) @[src/main/scala/micore/Core.scala 131:44]
|
||||
node _id_imm_i_sext_T_1 = mux(_id_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 131:31]
|
||||
node id_imm_i_sext = cat(_id_imm_i_sext_T_1, id_imm_i) @[src/main/scala/micore/Core.scala 131:26]
|
||||
node _id_imm_b_T = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 133:12]
|
||||
node id_imm_b = cat(_id_imm_b_T, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 132:21]
|
||||
node _id_imm_b_sext_T = bits(id_imm_b, 17, 17) @[src/main/scala/micore/Core.scala 136:44]
|
||||
node _id_imm_b_sext_T_1 = mux(_id_imm_b_sext_T, UInt<14>("h3fff"), UInt<14>("h0")) @[src/main/scala/micore/Core.scala 136:31]
|
||||
node id_imm_b_sext = cat(_id_imm_b_sext_T_1, id_imm_b) @[src/main/scala/micore/Core.scala 136:26]
|
||||
node _id_imm_j_T = bits(id_inst, 25, 0) @[src/main/scala/micore/Core.scala 138:12]
|
||||
node id_imm_j = cat(_id_imm_j_T, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 137:21]
|
||||
node _id_imm_j_sext_T = bits(id_imm_j, 25, 25) @[src/main/scala/micore/Core.scala 141:43]
|
||||
node _id_imm_j_sext_T_1 = mux(_id_imm_j_sext_T, UInt<6>("h3f"), UInt<6>("h0")) @[src/main/scala/micore/Core.scala 141:31]
|
||||
node id_imm_j_sext = cat(_id_imm_j_sext_T_1, id_imm_j) @[src/main/scala/micore/Core.scala 141:26]
|
||||
node id_imm_u = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 142:25]
|
||||
node _id_imm_u_shifted_T = mux(UInt<1>("h0"), UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 143:44]
|
||||
node id_imm_u_shifted = cat(id_imm_u, _id_imm_u_shifted_T) @[src/main/scala/micore/Core.scala 143:29]
|
||||
node id_imm_shamt = bits(id_inst, 10, 6) @[src/main/scala/micore/Core.scala 144:29]
|
||||
node _csignals_T = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_1 = eq(UInt<32>("h8c000000"), _csignals_T) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_2 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_3 = eq(UInt<32>("hac000000"), _csignals_T_2) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_4 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_5 = eq(UInt<6>("h20"), _csignals_T_4) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_6 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_7 = eq(UInt<32>("h80000000"), _csignals_T_6) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_6 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_7 = eq(UInt<30>("h20000000"), _csignals_T_6) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_8 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_9 = eq(UInt<6>("h22"), _csignals_T_8) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_10 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
@ -222,26 +225,26 @@ circuit TopOrigin :
|
||||
node _csignals_T_13 = eq(UInt<6>("h25"), _csignals_T_12) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_14 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_15 = eq(UInt<6>("h26"), _csignals_T_14) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_16 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_17 = eq(UInt<32>("hc0000000"), _csignals_T_16) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_18 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_19 = eq(UInt<32>("hd0000000"), _csignals_T_18) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_16 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_17 = eq(UInt<30>("h30000000"), _csignals_T_16) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_18 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_19 = eq(UInt<30>("h34000000"), _csignals_T_18) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_20 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_21 = eq(UInt<6>("h2a"), _csignals_T_20) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_22 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_23 = eq(UInt<31>("h40000000"), _csignals_T_22) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_24 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_25 = eq(UInt<31>("h50000000"), _csignals_T_24) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_22 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_23 = eq(UInt<29>("h10000000"), _csignals_T_22) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_24 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_25 = eq(UInt<29>("h14000000"), _csignals_T_24) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_26 = and(id_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_27 = eq(UInt<1>("h0"), _csignals_T_26) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_28 = and(id_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_29 = eq(UInt<2>("h2"), _csignals_T_28) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_30 = and(id_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_31 = eq(UInt<2>("h3"), _csignals_T_30) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_32 = and(id_inst, UInt<34>("h3f000003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_32 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_33 = eq(UInt<4>("h8"), _csignals_T_32) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_34 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_35 = eq(UInt<30>("h30000000"), _csignals_T_34) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_34 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_35 = eq(UInt<28>("hc000000"), _csignals_T_34) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_36 = and(id_inst, UInt<32>("hffffffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_37 = eq(UInt<30>("h20000000"), _csignals_T_36) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_38 = mux(_csignals_T_37, UInt<5>("h0"), UInt<5>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
@ -358,124 +361,124 @@ circuit TopOrigin :
|
||||
node _csignals_T_144 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_143) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node _csignals_T_145 = mux(_csignals_T_3, UInt<3>("h2"), _csignals_T_144) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node csignals_5 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_145) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node _id_op1_data_T = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 171:19]
|
||||
node _id_op1_data_T_1 = eq(csignals_1, UInt<2>("h2")) @[src/main/scala/micore/Core.scala 172:19]
|
||||
node _id_op1_data_T = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 178:19]
|
||||
node _id_op1_data_T_1 = eq(csignals_1, UInt<2>("h2")) @[src/main/scala/micore/Core.scala 179:19]
|
||||
node _id_op1_data_T_2 = mux(_id_op1_data_T_1, id_reg_pc, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node id_op1_data = mux(_id_op1_data_T, id_rs1_data, _id_op1_data_T_2) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _id_op2_data_T = eq(csignals_2, UInt<3>("h1")) @[src/main/scala/micore/Core.scala 179:19]
|
||||
node _id_op2_data_T_1 = eq(csignals_2, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 180:19]
|
||||
node _id_op2_data_T_2 = eq(csignals_2, UInt<3>("h4")) @[src/main/scala/micore/Core.scala 181:19]
|
||||
node _id_op2_data_T_3 = eq(csignals_2, UInt<3>("h5")) @[src/main/scala/micore/Core.scala 182:19]
|
||||
node _id_op2_data_T = eq(csignals_2, UInt<3>("h1")) @[src/main/scala/micore/Core.scala 186:19]
|
||||
node _id_op2_data_T_1 = eq(csignals_2, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 187:19]
|
||||
node _id_op2_data_T_2 = eq(csignals_2, UInt<3>("h4")) @[src/main/scala/micore/Core.scala 188:19]
|
||||
node _id_op2_data_T_3 = eq(csignals_2, UInt<3>("h5")) @[src/main/scala/micore/Core.scala 189:19]
|
||||
node _id_op2_data_T_4 = mux(_id_op2_data_T_3, id_imm_u_shifted, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _id_op2_data_T_5 = mux(_id_op2_data_T_2, id_imm_j_sext, _id_op2_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _id_op2_data_T_6 = mux(_id_op2_data_T_1, id_imm_i_sext, _id_op2_data_T_5) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node id_op2_data = mux(_id_op2_data_T, id_rs2_data, _id_op2_data_T_6) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _T = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 271:22]
|
||||
node _GEN_0 = validif(_T, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 271:{33,42}]
|
||||
node _GEN_1 = validif(_T, clock) @[src/main/scala/micore/Core.scala 271:{33,42}]
|
||||
node _GEN_2 = mux(_T, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Core.scala 15:20 271:{33,42}]
|
||||
node _GEN_3 = validif(_T, UInt<1>("h1")) @[src/main/scala/micore/Core.scala 271:{33,59}]
|
||||
node _GEN_4 = validif(_T, wb_reg_wb_data) @[src/main/scala/micore/Core.scala 271:{33,59}]
|
||||
node _io_exit_T = eq(id_reg_inst, UInt<32>("h114514")) @[src/main/scala/micore/Core.scala 274:27]
|
||||
node _T_1 = asUInt(reset) @[src/main/scala/micore/Core.scala 275:9]
|
||||
node _T_2 = eq(_T_1, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 275:9]
|
||||
node _T_3 = asUInt(reset) @[src/main/scala/micore/Core.scala 276:9]
|
||||
node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 276:9]
|
||||
node _T_5 = asUInt(reset) @[src/main/scala/micore/Core.scala 277:9]
|
||||
node _T_6 = eq(_T_5, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 277:9]
|
||||
node _T_7 = asUInt(reset) @[src/main/scala/micore/Core.scala 278:9]
|
||||
node _T_8 = eq(_T_7, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 278:9]
|
||||
node _T_9 = asUInt(reset) @[src/main/scala/micore/Core.scala 279:9]
|
||||
node _T_10 = eq(_T_9, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 279:9]
|
||||
node _T_11 = asUInt(reset) @[src/main/scala/micore/Core.scala 280:9]
|
||||
node _T_12 = eq(_T_11, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 280:9]
|
||||
node _T_13 = asUInt(reset) @[src/main/scala/micore/Core.scala 281:9]
|
||||
node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 281:9]
|
||||
node _T_15 = asUInt(reset) @[src/main/scala/micore/Core.scala 282:9]
|
||||
node _T_16 = eq(_T_15, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 282:9]
|
||||
node _T_17 = asUInt(reset) @[src/main/scala/micore/Core.scala 283:9]
|
||||
node _T_18 = eq(_T_17, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 283:9]
|
||||
node _T_19 = asUInt(reset) @[src/main/scala/micore/Core.scala 284:9]
|
||||
node _T_20 = eq(_T_19, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 284:9]
|
||||
node _T_21 = asUInt(reset) @[src/main/scala/micore/Core.scala 285:9]
|
||||
node _T_22 = eq(_T_21, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 285:9]
|
||||
node _T_23 = asUInt(reset) @[src/main/scala/micore/Core.scala 286:9]
|
||||
node _T_24 = eq(_T_23, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 286:9]
|
||||
node _T_25 = asUInt(reset) @[src/main/scala/micore/Core.scala 287:9]
|
||||
node _T_26 = eq(_T_25, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 287:9]
|
||||
node _T_27 = asUInt(reset) @[src/main/scala/micore/Core.scala 288:9]
|
||||
node _T_28 = eq(_T_27, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 288:9]
|
||||
node _T_29 = asUInt(reset) @[src/main/scala/micore/Core.scala 289:9]
|
||||
node _T_30 = eq(_T_29, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 289:9]
|
||||
node _T_31 = asUInt(reset) @[src/main/scala/micore/Core.scala 290:9]
|
||||
node _T_32 = eq(_T_31, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 290:9]
|
||||
node _T_33 = asUInt(reset) @[src/main/scala/micore/Core.scala 291:9]
|
||||
node _T_34 = eq(_T_33, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 291:9]
|
||||
node _T_35 = asUInt(reset) @[src/main/scala/micore/Core.scala 292:9]
|
||||
node _T_36 = eq(_T_35, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 292:9]
|
||||
io_imem_addr <= if_reg_pc @[src/main/scala/micore/Core.scala 56:16]
|
||||
io_dmem_addr <= mem_reg_alu_out @[src/main/scala/micore/Core.scala 253:16]
|
||||
io_dmem_wen <= bits(mem_reg_mem_wen, 0, 0) @[src/main/scala/micore/Core.scala 254:15]
|
||||
io_dmem_wdata <= mem_reg_rs2_data @[src/main/scala/micore/Core.scala 255:17]
|
||||
io_exit <= _io_exit_T @[src/main/scala/micore/Core.scala 274:11]
|
||||
regfile.id_rs1_data_MPORT.addr <= id_rs1_addr @[src/main/scala/micore/Core.scala 106:12]
|
||||
regfile.id_rs1_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 106:12]
|
||||
regfile.id_rs1_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 106:12]
|
||||
regfile.id_rs2_data_MPORT.addr <= id_rs2_addr @[src/main/scala/micore/Core.scala 114:12]
|
||||
regfile.id_rs2_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 114:12]
|
||||
regfile.id_rs2_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 114:12]
|
||||
node _T = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 275:22]
|
||||
node _T_1 = neq(wb_reg_wb_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 275:50]
|
||||
node _T_2 = and(_T, _T_1) @[src/main/scala/micore/Core.scala 275:32]
|
||||
node _GEN_0 = validif(_T_2, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 275:59 276:12]
|
||||
node _GEN_1 = validif(_T_2, clock) @[src/main/scala/micore/Core.scala 275:59 276:12]
|
||||
node _GEN_2 = mux(_T_2, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Core.scala 275:59 276:12 15:20]
|
||||
node _GEN_3 = validif(_T_2, UInt<1>("h1")) @[src/main/scala/micore/Core.scala 275:59 276:29]
|
||||
node _GEN_4 = validif(_T_2, wb_reg_wb_data) @[src/main/scala/micore/Core.scala 275:59 276:29]
|
||||
node _io_exit_T = eq(id_reg_inst, UInt<32>("h114514")) @[src/main/scala/micore/Core.scala 280:27]
|
||||
node _T_3 = asUInt(reset) @[src/main/scala/micore/Core.scala 281:9]
|
||||
node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 281:9]
|
||||
node _T_5 = asUInt(reset) @[src/main/scala/micore/Core.scala 282:9]
|
||||
node _T_6 = eq(_T_5, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 282:9]
|
||||
node _T_7 = asUInt(reset) @[src/main/scala/micore/Core.scala 283:9]
|
||||
node _T_8 = eq(_T_7, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 283:9]
|
||||
node _T_9 = asUInt(reset) @[src/main/scala/micore/Core.scala 284:9]
|
||||
node _T_10 = eq(_T_9, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 284:9]
|
||||
node _T_11 = asUInt(reset) @[src/main/scala/micore/Core.scala 285:9]
|
||||
node _T_12 = eq(_T_11, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 285:9]
|
||||
node _T_13 = asUInt(reset) @[src/main/scala/micore/Core.scala 286:9]
|
||||
node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 286:9]
|
||||
node _T_15 = asUInt(reset) @[src/main/scala/micore/Core.scala 287:9]
|
||||
node _T_16 = eq(_T_15, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 287:9]
|
||||
node _T_17 = asUInt(reset) @[src/main/scala/micore/Core.scala 288:9]
|
||||
node _T_18 = eq(_T_17, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 288:9]
|
||||
node _T_19 = asUInt(reset) @[src/main/scala/micore/Core.scala 289:9]
|
||||
node _T_20 = eq(_T_19, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 289:9]
|
||||
node _T_21 = asUInt(reset) @[src/main/scala/micore/Core.scala 290:9]
|
||||
node _T_22 = eq(_T_21, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 290:9]
|
||||
node _T_23 = asUInt(reset) @[src/main/scala/micore/Core.scala 291:9]
|
||||
node _T_24 = eq(_T_23, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 291:9]
|
||||
node _T_25 = asUInt(reset) @[src/main/scala/micore/Core.scala 292:9]
|
||||
node _T_26 = eq(_T_25, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 292:9]
|
||||
node _T_27 = asUInt(reset) @[src/main/scala/micore/Core.scala 293:9]
|
||||
node _T_28 = eq(_T_27, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 293:9]
|
||||
node _T_29 = asUInt(reset) @[src/main/scala/micore/Core.scala 294:9]
|
||||
node _T_30 = eq(_T_29, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 294:9]
|
||||
node _T_31 = asUInt(reset) @[src/main/scala/micore/Core.scala 295:9]
|
||||
node _T_32 = eq(_T_31, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 295:9]
|
||||
node _T_33 = asUInt(reset) @[src/main/scala/micore/Core.scala 296:9]
|
||||
node _T_34 = eq(_T_33, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 296:9]
|
||||
node _T_35 = asUInt(reset) @[src/main/scala/micore/Core.scala 297:9]
|
||||
node _T_36 = eq(_T_35, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 297:9]
|
||||
node _T_37 = asUInt(reset) @[src/main/scala/micore/Core.scala 298:9]
|
||||
node _T_38 = eq(_T_37, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 298:9]
|
||||
io_imem_addr <= if_reg_pc @[src/main/scala/micore/Core.scala 54:16]
|
||||
io_dmem_addr <= mem_reg_alu_out @[src/main/scala/micore/Core.scala 256:16]
|
||||
io_dmem_wen <= bits(mem_reg_mem_wen, 0, 0) @[src/main/scala/micore/Core.scala 257:15]
|
||||
io_dmem_wdata <= mem_reg_rs2_data @[src/main/scala/micore/Core.scala 258:17]
|
||||
io_exit <= _io_exit_T @[src/main/scala/micore/Core.scala 280:11]
|
||||
regfile.id_rs1_data_MPORT.addr <= id_rs1_addr @[src/main/scala/micore/Core.scala 114:12]
|
||||
regfile.id_rs1_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 114:12]
|
||||
regfile.id_rs1_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 114:12]
|
||||
regfile.id_rs2_data_MPORT.addr <= id_rs2_addr @[src/main/scala/micore/Core.scala 122:12]
|
||||
regfile.id_rs2_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 122:12]
|
||||
regfile.id_rs2_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 122:12]
|
||||
regfile.MPORT.addr <= _GEN_0
|
||||
regfile.MPORT.en <= _GEN_2
|
||||
regfile.MPORT.clk <= _GEN_1
|
||||
regfile.MPORT.data <= _GEN_4
|
||||
regfile.MPORT.mask <= _GEN_3
|
||||
id_reg_pc <= mux(reset, UInt<32>("h0"), _id_reg_pc_T) @[src/main/scala/micore/Core.scala 19:{26,26} 77:13]
|
||||
id_reg_inst <= mux(reset, UInt<32>("h0"), _id_reg_inst_T_2) @[src/main/scala/micore/Core.scala 20:{28,28} 78:15]
|
||||
exe_reg_pc <= mux(reset, UInt<32>("h0"), id_reg_pc) @[src/main/scala/micore/Core.scala 187:14 23:{27,27}]
|
||||
exe_reg_wb_addr <= mux(reset, UInt<5>("h0"), id_wb_addr) @[src/main/scala/micore/Core.scala 191:19 24:{32,32}]
|
||||
exe_reg_op1_data <= mux(reset, UInt<32>("h0"), id_op1_data) @[src/main/scala/micore/Core.scala 188:20 25:{33,33}]
|
||||
exe_reg_op2_data <= bits(mux(reset, UInt<32>("h0"), id_op2_data), 31, 0) @[src/main/scala/micore/Core.scala 189:20 26:{33,33}]
|
||||
exe_reg_rs2_data <= mux(reset, UInt<32>("h0"), id_rs2_data) @[src/main/scala/micore/Core.scala 190:20 27:{33,33}]
|
||||
exe_reg_exe_fun <= mux(reset, UInt<5>("h0"), csignals_0) @[src/main/scala/micore/Core.scala 198:19 28:{32,32}]
|
||||
exe_reg_mem_wen <= mux(reset, UInt<2>("h0"), csignals_3) @[src/main/scala/micore/Core.scala 193:19 29:{32,32}]
|
||||
exe_reg_rf_wen <= mux(reset, UInt<2>("h0"), csignals_4) @[src/main/scala/micore/Core.scala 194:18 30:{31,31}]
|
||||
exe_reg_wb_sel <= mux(reset, UInt<3>("h0"), csignals_5) @[src/main/scala/micore/Core.scala 192:18 31:{31,31}]
|
||||
exe_reg_imm_i_sext <= mux(reset, UInt<32>("h0"), id_imm_i_sext) @[src/main/scala/micore/Core.scala 195:22 32:{35,35}]
|
||||
id_reg_pc <= mux(reset, UInt<32>("h0"), _id_reg_pc_T) @[src/main/scala/micore/Core.scala 19:{26,26} 75:13]
|
||||
id_reg_inst <= mux(reset, UInt<32>("h0"), _id_reg_inst_T_2) @[src/main/scala/micore/Core.scala 20:{28,28} 76:15]
|
||||
exe_reg_pc <= mux(reset, UInt<32>("h0"), id_reg_pc) @[src/main/scala/micore/Core.scala 194:14 23:{27,27}]
|
||||
exe_reg_wb_addr <= mux(reset, UInt<5>("h0"), id_wb_addr) @[src/main/scala/micore/Core.scala 198:19 24:{32,32}]
|
||||
exe_reg_op1_data <= mux(reset, UInt<32>("h0"), id_op1_data) @[src/main/scala/micore/Core.scala 195:20 25:{33,33}]
|
||||
exe_reg_op2_data <= bits(mux(reset, UInt<32>("h0"), id_op2_data), 31, 0) @[src/main/scala/micore/Core.scala 196:20 26:{33,33}]
|
||||
exe_reg_rs2_data <= mux(reset, UInt<32>("h0"), id_rs2_data) @[src/main/scala/micore/Core.scala 197:20 27:{33,33}]
|
||||
exe_reg_exe_fun <= mux(reset, UInt<5>("h0"), csignals_0) @[src/main/scala/micore/Core.scala 205:19 28:{32,32}]
|
||||
exe_reg_mem_wen <= mux(reset, UInt<2>("h0"), csignals_3) @[src/main/scala/micore/Core.scala 200:19 29:{32,32}]
|
||||
exe_reg_rf_wen <= mux(reset, UInt<2>("h0"), csignals_4) @[src/main/scala/micore/Core.scala 201:18 30:{31,31}]
|
||||
exe_reg_wb_sel <= mux(reset, UInt<3>("h0"), csignals_5) @[src/main/scala/micore/Core.scala 199:18 31:{31,31}]
|
||||
exe_reg_imm_i_sext <= mux(reset, UInt<32>("h0"), id_imm_i_sext) @[src/main/scala/micore/Core.scala 202:22 32:{35,35}]
|
||||
exe_reg_imm_s_sext <= mux(reset, UInt<32>("h0"), exe_reg_imm_s_sext) @[src/main/scala/micore/Core.scala 33:{35,35,35}]
|
||||
exe_reg_imm_b_sext <= mux(reset, UInt<32>("h0"), id_imm_b_sext) @[src/main/scala/micore/Core.scala 196:22 34:{35,35}]
|
||||
exe_reg_imm_u_shifted <= mux(reset, UInt<32>("h0"), id_imm_u_shifted) @[src/main/scala/micore/Core.scala 197:25 35:{38,38}]
|
||||
exe_reg_imm_z_uext <= mux(reset, UInt<32>("h0"), exe_reg_imm_z_uext) @[src/main/scala/micore/Core.scala 36:{35,35,35}]
|
||||
mem_reg_pc <= mux(reset, UInt<32>("h0"), exe_reg_pc) @[src/main/scala/micore/Core.scala 242:14 39:{27,27}]
|
||||
mem_reg_wb_addr <= mux(reset, UInt<5>("h0"), exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 245:19 40:{32,32}]
|
||||
mem_reg_op1_data <= mux(reset, UInt<32>("h0"), exe_reg_op1_data) @[src/main/scala/micore/Core.scala 243:20 41:{33,33}]
|
||||
mem_reg_rs2_data <= mux(reset, UInt<32>("h0"), exe_reg_rs2_data) @[src/main/scala/micore/Core.scala 244:20 42:{33,33}]
|
||||
mem_reg_mem_wen <= mux(reset, UInt<2>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 250:19 43:{32,32}]
|
||||
mem_reg_rf_wen <= mux(reset, UInt<2>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 247:18 44:{31,31}]
|
||||
mem_reg_wb_sel <= mux(reset, UInt<3>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 248:18 45:{31,31}]
|
||||
mem_reg_imm_z_uext <= mux(reset, UInt<32>("h0"), exe_reg_imm_z_uext) @[src/main/scala/micore/Core.scala 249:22 46:{35,35}]
|
||||
mem_reg_alu_out <= mux(reset, UInt<32>("h0"), exe_alu_out) @[src/main/scala/micore/Core.scala 246:19 47:{32,32}]
|
||||
wb_reg_wb_addr <= mux(reset, UInt<5>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 268:18 50:{31,31}]
|
||||
wb_reg_rf_wen <= mux(reset, UInt<2>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 267:17 51:{30,30}]
|
||||
wb_reg_wb_data <= mux(reset, UInt<32>("h0"), mem_wb_data) @[src/main/scala/micore/Core.scala 266:18 52:{31,31}]
|
||||
if_reg_pc <= mux(reset, UInt<32>("h0"), if_pc_next) @[src/main/scala/micore/Core.scala 55:{26,26} 74:13]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_2), UInt<1>("h1")), "---------------------\n") : printf @[src/main/scala/micore/Core.scala 275:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "if_reg_pc: 0x%x\n", if_reg_pc) : printf_1 @[src/main/scala/micore/Core.scala 276:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "id_reg_pc: 0x%x\n", id_reg_pc) : printf_2 @[src/main/scala/micore/Core.scala 277:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_8), UInt<1>("h1")), "id_reg_inst: 0x%x\n", id_reg_inst) : printf_3 @[src/main/scala/micore/Core.scala 278:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "id_inst: 0x%x\n", id_inst) : printf_4 @[src/main/scala/micore/Core.scala 279:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "id_rs1_data: 0x%x\n", id_rs1_data) : printf_5 @[src/main/scala/micore/Core.scala 280:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "id_rs2_data: 0x%x\n", id_rs2_data) : printf_6 @[src/main/scala/micore/Core.scala 281:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "id_exe_fun: 0x%x\n", csignals_0) : printf_7 @[src/main/scala/micore/Core.scala 282:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "id_op1_sel: 0x%x\n", csignals_1) : printf_8 @[src/main/scala/micore/Core.scala 283:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_20), UInt<1>("h1")), "id_op2_sel: 0x%x\n", csignals_2) : printf_9 @[src/main/scala/micore/Core.scala 284:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_22), UInt<1>("h1")), "exe_reg_pc: 0x%x\n", exe_reg_pc) : printf_10 @[src/main/scala/micore/Core.scala 285:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_24), UInt<1>("h1")), "exe_reg_op1_data: 0x%x\n", id_op1_data) : printf_11 @[src/main/scala/micore/Core.scala 286:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_26), UInt<1>("h1")), "exe_reg_op2_data: 0x%x\n", id_op2_data) : printf_12 @[src/main/scala/micore/Core.scala 287:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_28), UInt<1>("h1")), "exe_alu_out: 0x%x\n", exe_alu_out) : printf_13 @[src/main/scala/micore/Core.scala 288:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_30), UInt<1>("h1")), "mem_reg_pc: 0x%x\n", mem_reg_pc) : printf_14 @[src/main/scala/micore/Core.scala 289:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_32), UInt<1>("h1")), "mem_wb_data: 0x%x\n", mem_wb_data) : printf_15 @[src/main/scala/micore/Core.scala 290:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_34), UInt<1>("h1")), "wb_reg_wb_data: 0x%x\n", wb_reg_wb_data) : printf_16 @[src/main/scala/micore/Core.scala 291:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_36), UInt<1>("h1")), "---------------------\n") : printf_17 @[src/main/scala/micore/Core.scala 292:9]
|
||||
exe_reg_imm_b_sext <= mux(reset, UInt<32>("h0"), id_imm_b_sext) @[src/main/scala/micore/Core.scala 203:22 34:{35,35}]
|
||||
exe_reg_imm_u_shifted <= mux(reset, UInt<32>("h0"), id_imm_u_shifted) @[src/main/scala/micore/Core.scala 204:25 35:{38,38}]
|
||||
mem_reg_pc <= mux(reset, UInt<32>("h0"), exe_reg_pc) @[src/main/scala/micore/Core.scala 246:14 38:{27,27}]
|
||||
mem_reg_wb_addr <= mux(reset, UInt<5>("h0"), exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 249:19 39:{32,32}]
|
||||
mem_reg_op1_data <= mux(reset, UInt<32>("h0"), exe_reg_op1_data) @[src/main/scala/micore/Core.scala 247:20 40:{33,33}]
|
||||
mem_reg_rs2_data <= mux(reset, UInt<32>("h0"), exe_reg_rs2_data) @[src/main/scala/micore/Core.scala 248:20 41:{33,33}]
|
||||
mem_reg_mem_wen <= mux(reset, UInt<2>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 253:19 42:{32,32}]
|
||||
mem_reg_rf_wen <= mux(reset, UInt<2>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 251:18 43:{31,31}]
|
||||
mem_reg_wb_sel <= mux(reset, UInt<3>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 252:18 44:{31,31}]
|
||||
mem_reg_alu_out <= mux(reset, UInt<32>("h0"), exe_alu_out) @[src/main/scala/micore/Core.scala 250:19 45:{32,32}]
|
||||
wb_reg_wb_addr <= mux(reset, UInt<5>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 271:18 48:{31,31}]
|
||||
wb_reg_rf_wen <= mux(reset, UInt<2>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 270:17 49:{30,30}]
|
||||
wb_reg_wb_data <= mux(reset, UInt<32>("h0"), mem_wb_data) @[src/main/scala/micore/Core.scala 269:18 50:{31,31}]
|
||||
if_reg_pc <= mux(reset, UInt<32>("h0"), if_pc_next) @[src/main/scala/micore/Core.scala 53:{26,26} 72:13]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "---------------------\n") : printf @[src/main/scala/micore/Core.scala 281:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "if_reg_pc: 0x%x\n", if_reg_pc) : printf_1 @[src/main/scala/micore/Core.scala 282:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_8), UInt<1>("h1")), "id_reg_pc: 0x%x\n", id_reg_pc) : printf_2 @[src/main/scala/micore/Core.scala 283:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "id_reg_inst: 0x%x\n", id_reg_inst) : printf_3 @[src/main/scala/micore/Core.scala 284:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "id_inst: 0x%x\n", id_inst) : printf_4 @[src/main/scala/micore/Core.scala 285:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "id_rs1_data: 0x%x\n", id_rs1_data) : printf_5 @[src/main/scala/micore/Core.scala 286:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "id_rs2_data: 0x%x\n", id_rs2_data) : printf_6 @[src/main/scala/micore/Core.scala 287:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "id_exe_fun: 0x%x\n", csignals_0) : printf_7 @[src/main/scala/micore/Core.scala 288:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_20), UInt<1>("h1")), "id_op1_sel: 0x%x\n", csignals_1) : printf_8 @[src/main/scala/micore/Core.scala 289:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_22), UInt<1>("h1")), "id_op2_sel: 0x%x\n", csignals_2) : printf_9 @[src/main/scala/micore/Core.scala 290:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_24), UInt<1>("h1")), "exe_reg_pc: 0x%x\n", exe_reg_pc) : printf_10 @[src/main/scala/micore/Core.scala 291:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_26), UInt<1>("h1")), "exe_reg_op1_data: 0x%x\n", id_op1_data) : printf_11 @[src/main/scala/micore/Core.scala 292:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_28), UInt<1>("h1")), "exe_reg_op2_data: 0x%x\n", id_op2_data) : printf_12 @[src/main/scala/micore/Core.scala 293:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_30), UInt<1>("h1")), "exe_alu_out: 0x%x\n", exe_alu_out) : printf_13 @[src/main/scala/micore/Core.scala 294:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_32), UInt<1>("h1")), "mem_reg_pc: 0x%x\n", mem_reg_pc) : printf_14 @[src/main/scala/micore/Core.scala 295:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_34), UInt<1>("h1")), "mem_wb_data: 0x%x\n", mem_wb_data) : printf_15 @[src/main/scala/micore/Core.scala 296:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_36), UInt<1>("h1")), "wb_reg_wb_data: 0x%x\n", wb_reg_wb_data) : printf_16 @[src/main/scala/micore/Core.scala 297:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_38), UInt<1>("h1")), "---------------------\n") : printf_17 @[src/main/scala/micore/Core.scala 298:9]
|
||||
|
||||
module Memory : @[src/main/scala/micore/Memory.scala 24:7]
|
||||
input clock : Clock @[src/main/scala/micore/Memory.scala 24:7]
|
||||
|
||||
@ -1,42 +1,43 @@
|
||||
FIRRTL version 1.2.0
|
||||
circuit TopOrigin :
|
||||
module Core : @[src/main/scala/sicore/Core.scala 8:7]
|
||||
input clock : Clock @[src/main/scala/sicore/Core.scala 8:7]
|
||||
input reset : UInt<1> @[src/main/scala/sicore/Core.scala 8:7]
|
||||
output io_imem_addr : UInt<32> @[src/main/scala/sicore/Core.scala 9:14]
|
||||
input io_imem_inst : UInt<32> @[src/main/scala/sicore/Core.scala 9:14]
|
||||
output io_dmem_addr : UInt<32> @[src/main/scala/sicore/Core.scala 9:14]
|
||||
input io_dmem_rdata : UInt<32> @[src/main/scala/sicore/Core.scala 9:14]
|
||||
output io_dmem_wen : UInt<1> @[src/main/scala/sicore/Core.scala 9:14]
|
||||
output io_dmem_wdata : UInt<32> @[src/main/scala/sicore/Core.scala 9:14]
|
||||
output io_exit : UInt<1> @[src/main/scala/sicore/Core.scala 9:14]
|
||||
module Core : @[src/main/scala/sicore/Core.scala 9:7]
|
||||
input clock : Clock @[src/main/scala/sicore/Core.scala 9:7]
|
||||
input reset : UInt<1> @[src/main/scala/sicore/Core.scala 9:7]
|
||||
output io_imem_addr : UInt<32> @[src/main/scala/sicore/Core.scala 10:14]
|
||||
input io_imem_inst : UInt<32> @[src/main/scala/sicore/Core.scala 10:14]
|
||||
output io_dmem_addr : UInt<32> @[src/main/scala/sicore/Core.scala 10:14]
|
||||
input io_dmem_rdata : UInt<32> @[src/main/scala/sicore/Core.scala 10:14]
|
||||
output io_dmem_wen : UInt<1> @[src/main/scala/sicore/Core.scala 10:14]
|
||||
output io_dmem_wdata : UInt<32> @[src/main/scala/sicore/Core.scala 10:14]
|
||||
output io_exit : UInt<1> @[src/main/scala/sicore/Core.scala 10:14]
|
||||
|
||||
mem regfile : @[src/main/scala/sicore/Core.scala 16:20]
|
||||
mem regfile : @[src/main/scala/sicore/Core.scala 17:20]
|
||||
data-type => UInt<32>
|
||||
depth => 32
|
||||
read-latency => 0
|
||||
write-latency => 1
|
||||
reader => rs_data_MPORT
|
||||
reader => rt_data_MPORT
|
||||
reader => MPORT_1
|
||||
writer => MPORT
|
||||
read-under-write => undefined
|
||||
reg pc_reg : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), pc_reg) @[src/main/scala/sicore/Core.scala 19:23]
|
||||
node _pc_plus4_T = add(pc_reg, UInt<32>("h4")) @[src/main/scala/sicore/Core.scala 22:25]
|
||||
node pc_plus4 = tail(_pc_plus4_T, 1) @[src/main/scala/sicore/Core.scala 22:25]
|
||||
node _jmp_flg_T = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/sicore/Core.scala 25:23]
|
||||
node _jmp_flg_T_1 = eq(UInt<30>("h30000000"), _jmp_flg_T) @[src/main/scala/sicore/Core.scala 25:23]
|
||||
node _jmp_flg_T_2 = and(io_imem_inst, UInt<34>("h3f000003f")) @[src/main/scala/sicore/Core.scala 25:39]
|
||||
node _jmp_flg_T_3 = eq(UInt<4>("h8"), _jmp_flg_T_2) @[src/main/scala/sicore/Core.scala 25:39]
|
||||
node jmp_flg = or(_jmp_flg_T_1, _jmp_flg_T_3) @[src/main/scala/sicore/Core.scala 25:31]
|
||||
node _csignals_T = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_1 = eq(UInt<34>("h230000000"), _csignals_T) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_2 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_3 = eq(UInt<34>("h2b0000000"), _csignals_T_2) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
reset => (UInt<1>("h0"), pc_reg) @[src/main/scala/sicore/Core.scala 20:23]
|
||||
node _pc_plus4_T = add(pc_reg, UInt<32>("h4")) @[src/main/scala/sicore/Core.scala 23:25]
|
||||
node pc_plus4 = tail(_pc_plus4_T, 1) @[src/main/scala/sicore/Core.scala 23:25]
|
||||
node _jmp_flg_T = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/sicore/Core.scala 26:23]
|
||||
node _jmp_flg_T_1 = eq(UInt<28>("hc000000"), _jmp_flg_T) @[src/main/scala/sicore/Core.scala 26:23]
|
||||
node _jmp_flg_T_2 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/sicore/Core.scala 26:39]
|
||||
node _jmp_flg_T_3 = eq(UInt<4>("h8"), _jmp_flg_T_2) @[src/main/scala/sicore/Core.scala 26:39]
|
||||
node jmp_flg = or(_jmp_flg_T_1, _jmp_flg_T_3) @[src/main/scala/sicore/Core.scala 26:31]
|
||||
node _csignals_T = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_1 = eq(UInt<32>("h8c000000"), _csignals_T) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_2 = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_3 = eq(UInt<32>("hac000000"), _csignals_T_2) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_4 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_5 = eq(UInt<6>("h20"), _csignals_T_4) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_6 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_7 = eq(UInt<32>("h80000000"), _csignals_T_6) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_6 = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_7 = eq(UInt<30>("h20000000"), _csignals_T_6) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_8 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_9 = eq(UInt<6>("h22"), _csignals_T_8) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_10 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
@ -45,25 +46,25 @@ circuit TopOrigin :
|
||||
node _csignals_T_13 = eq(UInt<6>("h25"), _csignals_T_12) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_14 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_15 = eq(UInt<6>("h26"), _csignals_T_14) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_16 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_17 = eq(UInt<32>("hc0000000"), _csignals_T_16) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_18 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_19 = eq(UInt<32>("hd0000000"), _csignals_T_18) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_16 = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_17 = eq(UInt<30>("h30000000"), _csignals_T_16) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_18 = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_19 = eq(UInt<30>("h34000000"), _csignals_T_18) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_20 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_21 = eq(UInt<6>("h2a"), _csignals_T_20) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_22 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_23 = eq(UInt<31>("h40000000"), _csignals_T_22) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_24 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_25 = eq(UInt<31>("h50000000"), _csignals_T_24) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_22 = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_23 = eq(UInt<29>("h10000000"), _csignals_T_22) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_24 = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_25 = eq(UInt<29>("h14000000"), _csignals_T_24) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_26 = and(io_imem_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_27 = eq(UInt<1>("h0"), _csignals_T_26) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_28 = and(io_imem_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_29 = eq(UInt<2>("h2"), _csignals_T_28) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_30 = and(io_imem_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_31 = eq(UInt<2>("h3"), _csignals_T_30) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_32 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_33 = eq(UInt<30>("h30000000"), _csignals_T_32) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_34 = and(io_imem_inst, UInt<34>("h3f000003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_32 = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_33 = eq(UInt<28>("hc000000"), _csignals_T_32) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_34 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_35 = eq(UInt<4>("h8"), _csignals_T_34) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
|
||||
node _csignals_T_36 = mux(_csignals_T_35, UInt<5>("hd"), UInt<5>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node _csignals_T_37 = mux(_csignals_T_33, UInt<5>("h1"), _csignals_T_36) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
@ -83,7 +84,7 @@ circuit TopOrigin :
|
||||
node _csignals_T_51 = mux(_csignals_T_5, UInt<5>("h1"), _csignals_T_50) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node _csignals_T_52 = mux(_csignals_T_3, UInt<5>("h1"), _csignals_T_51) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node csignals_0 = mux(_csignals_T_1, UInt<5>("h1"), _csignals_T_52) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node _alu_out_T = eq(csignals_0, UInt<5>("h1")) @[src/main/scala/sicore/Core.scala 97:16]
|
||||
node _alu_out_T = eq(csignals_0, UInt<5>("h1")) @[src/main/scala/sicore/Core.scala 98:16]
|
||||
node _csignals_T_53 = mux(_csignals_T_35, UInt<2>("h1"), UInt<2>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node _csignals_T_54 = mux(_csignals_T_33, UInt<2>("h2"), _csignals_T_53) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node _csignals_T_55 = mux(_csignals_T_31, UInt<2>("h1"), _csignals_T_54) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
@ -102,11 +103,11 @@ circuit TopOrigin :
|
||||
node _csignals_T_68 = mux(_csignals_T_5, UInt<2>("h1"), _csignals_T_67) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node _csignals_T_69 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_68) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node csignals_1 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_69) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node _op1_data_T = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/sicore/Core.scala 79:16]
|
||||
node rs_addr = bits(io_imem_inst, 25, 21) @[src/main/scala/sicore/Core.scala 39:21]
|
||||
node _rs_data_T = neq(rs_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 42:30]
|
||||
node rs_data = mux(_rs_data_T, regfile.rs_data_MPORT.data, UInt<32>("h0")) @[src/main/scala/sicore/Core.scala 42:20]
|
||||
node _op1_data_T_1 = eq(csignals_1, UInt<2>("h2")) @[src/main/scala/sicore/Core.scala 80:16]
|
||||
node _op1_data_T = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/sicore/Core.scala 80:16]
|
||||
node rs_addr = bits(io_imem_inst, 25, 21) @[src/main/scala/sicore/Core.scala 40:21]
|
||||
node _rs_data_T = neq(rs_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 43:30]
|
||||
node rs_data = mux(_rs_data_T, regfile.rs_data_MPORT.data, UInt<32>("h0")) @[src/main/scala/sicore/Core.scala 43:20]
|
||||
node _op1_data_T_1 = eq(csignals_1, UInt<2>("h2")) @[src/main/scala/sicore/Core.scala 81:16]
|
||||
node _op1_data_T_2 = mux(_op1_data_T_1, pc_reg, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node op1_data = mux(_op1_data_T, rs_data, _op1_data_T_2) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _csignals_T_70 = mux(_csignals_T_35, UInt<3>("h0"), UInt<3>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
@ -127,50 +128,50 @@ circuit TopOrigin :
|
||||
node _csignals_T_85 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_84) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node _csignals_T_86 = mux(_csignals_T_3, UInt<3>("h2"), _csignals_T_85) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node csignals_2 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_86) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node _op2_data_T = eq(csignals_2, UInt<3>("h1")) @[src/main/scala/sicore/Core.scala 87:16]
|
||||
node rt_addr = bits(io_imem_inst, 20, 16) @[src/main/scala/sicore/Core.scala 40:21]
|
||||
node _rt_data_T = neq(rt_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 43:30]
|
||||
node rt_data = mux(_rt_data_T, regfile.rt_data_MPORT.data, UInt<32>("h0")) @[src/main/scala/sicore/Core.scala 43:20]
|
||||
node _op2_data_T_1 = eq(csignals_2, UInt<3>("h2")) @[src/main/scala/sicore/Core.scala 88:16]
|
||||
node imm_i = bits(io_imem_inst, 15, 0) @[src/main/scala/sicore/Core.scala 44:19]
|
||||
node _imm_i_sext_T = bits(imm_i, 15, 15) @[src/main/scala/sicore/Core.scala 45:38]
|
||||
node _imm_i_sext_T_1 = mux(_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/sicore/Core.scala 45:28]
|
||||
node imm_i_sext = cat(_imm_i_sext_T_1, imm_i) @[src/main/scala/sicore/Core.scala 45:23]
|
||||
node _op2_data_T_2 = eq(csignals_2, UInt<3>("h4")) @[src/main/scala/sicore/Core.scala 89:16]
|
||||
node _imm_j_T = bits(io_imem_inst, 25, 0) @[src/main/scala/sicore/Core.scala 46:23]
|
||||
node _imm_j_T_1 = mux(UInt<1>("h0"), UInt<2>("h3"), UInt<2>("h0")) @[src/main/scala/sicore/Core.scala 46:36]
|
||||
node imm_j = cat(_imm_j_T, _imm_j_T_1) @[src/main/scala/sicore/Core.scala 46:18]
|
||||
node _op2_data_T = eq(csignals_2, UInt<3>("h1")) @[src/main/scala/sicore/Core.scala 88:16]
|
||||
node rt_addr = bits(io_imem_inst, 20, 16) @[src/main/scala/sicore/Core.scala 41:21]
|
||||
node _rt_data_T = neq(rt_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 44:30]
|
||||
node rt_data = mux(_rt_data_T, regfile.rt_data_MPORT.data, UInt<32>("h0")) @[src/main/scala/sicore/Core.scala 44:20]
|
||||
node _op2_data_T_1 = eq(csignals_2, UInt<3>("h2")) @[src/main/scala/sicore/Core.scala 89:16]
|
||||
node imm_i = bits(io_imem_inst, 15, 0) @[src/main/scala/sicore/Core.scala 45:19]
|
||||
node _imm_i_sext_T = bits(imm_i, 15, 15) @[src/main/scala/sicore/Core.scala 46:38]
|
||||
node _imm_i_sext_T_1 = mux(_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/sicore/Core.scala 46:28]
|
||||
node imm_i_sext = cat(_imm_i_sext_T_1, imm_i) @[src/main/scala/sicore/Core.scala 46:23]
|
||||
node _op2_data_T_2 = eq(csignals_2, UInt<3>("h4")) @[src/main/scala/sicore/Core.scala 90:16]
|
||||
node _imm_j_T = bits(io_imem_inst, 25, 0) @[src/main/scala/sicore/Core.scala 47:23]
|
||||
node _imm_j_T_1 = mux(UInt<1>("h0"), UInt<2>("h3"), UInt<2>("h0")) @[src/main/scala/sicore/Core.scala 47:36]
|
||||
node imm_j = cat(_imm_j_T, _imm_j_T_1) @[src/main/scala/sicore/Core.scala 47:18]
|
||||
node _op2_data_T_3 = mux(_op2_data_T_2, imm_j, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _op2_data_T_4 = mux(_op2_data_T_1, imm_i_sext, _op2_data_T_3) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node op2_data = mux(_op2_data_T, rt_data, _op2_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _alu_out_T_1 = add(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 97:42]
|
||||
node _alu_out_T_2 = tail(_alu_out_T_1, 1) @[src/main/scala/sicore/Core.scala 97:42]
|
||||
node _alu_out_T_3 = eq(csignals_0, UInt<5>("h2")) @[src/main/scala/sicore/Core.scala 98:16]
|
||||
node _alu_out_T_4 = sub(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 98:42]
|
||||
node _alu_out_T_5 = tail(_alu_out_T_4, 1) @[src/main/scala/sicore/Core.scala 98:42]
|
||||
node _alu_out_T_6 = eq(csignals_0, UInt<5>("h3")) @[src/main/scala/sicore/Core.scala 99:16]
|
||||
node _alu_out_T_7 = and(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 99:42]
|
||||
node _alu_out_T_8 = eq(csignals_0, UInt<5>("h4")) @[src/main/scala/sicore/Core.scala 100:16]
|
||||
node _alu_out_T_9 = or(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 100:41]
|
||||
node _alu_out_T_10 = eq(csignals_0, UInt<5>("h5")) @[src/main/scala/sicore/Core.scala 101:16]
|
||||
node _alu_out_T_11 = xor(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 101:42]
|
||||
node _alu_out_T_12 = eq(csignals_0, UInt<5>("h6")) @[src/main/scala/sicore/Core.scala 102:16]
|
||||
node _alu_out_T_13 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 102:53]
|
||||
node _alu_out_T_14 = dshl(op1_data, _alu_out_T_13) @[src/main/scala/sicore/Core.scala 102:42]
|
||||
node _alu_out_T_15 = bits(_alu_out_T_14, 31, 0) @[src/main/scala/sicore/Core.scala 102:60]
|
||||
node _alu_out_T_16 = eq(csignals_0, UInt<5>("h7")) @[src/main/scala/sicore/Core.scala 103:16]
|
||||
node _alu_out_T_17 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 103:53]
|
||||
node _alu_out_T_18 = dshr(op1_data, _alu_out_T_17) @[src/main/scala/sicore/Core.scala 103:42]
|
||||
node _alu_out_T_19 = eq(csignals_0, UInt<5>("h8")) @[src/main/scala/sicore/Core.scala 104:16]
|
||||
node _alu_out_T_20 = asSInt(op1_data) @[src/main/scala/sicore/Core.scala 104:42]
|
||||
node _alu_out_T_21 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 104:60]
|
||||
node _alu_out_T_22 = dshr(_alu_out_T_20, _alu_out_T_21) @[src/main/scala/sicore/Core.scala 104:49]
|
||||
node _alu_out_T_23 = asUInt(_alu_out_T_22) @[src/main/scala/sicore/Core.scala 104:68]
|
||||
node _alu_out_T_24 = eq(csignals_0, UInt<5>("h9")) @[src/main/scala/sicore/Core.scala 105:16]
|
||||
node _alu_out_T_25 = asSInt(op1_data) @[src/main/scala/sicore/Core.scala 105:42]
|
||||
node _alu_out_T_26 = asSInt(op2_data) @[src/main/scala/sicore/Core.scala 105:60]
|
||||
node _alu_out_T_27 = lt(_alu_out_T_25, _alu_out_T_26) @[src/main/scala/sicore/Core.scala 105:49]
|
||||
node _alu_out_T_28 = eq(csignals_0, UInt<5>("hd")) @[src/main/scala/sicore/Core.scala 106:16]
|
||||
node _alu_out_T_1 = add(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 98:42]
|
||||
node _alu_out_T_2 = tail(_alu_out_T_1, 1) @[src/main/scala/sicore/Core.scala 98:42]
|
||||
node _alu_out_T_3 = eq(csignals_0, UInt<5>("h2")) @[src/main/scala/sicore/Core.scala 99:16]
|
||||
node _alu_out_T_4 = sub(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 99:42]
|
||||
node _alu_out_T_5 = tail(_alu_out_T_4, 1) @[src/main/scala/sicore/Core.scala 99:42]
|
||||
node _alu_out_T_6 = eq(csignals_0, UInt<5>("h3")) @[src/main/scala/sicore/Core.scala 100:16]
|
||||
node _alu_out_T_7 = and(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 100:42]
|
||||
node _alu_out_T_8 = eq(csignals_0, UInt<5>("h4")) @[src/main/scala/sicore/Core.scala 101:16]
|
||||
node _alu_out_T_9 = or(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 101:41]
|
||||
node _alu_out_T_10 = eq(csignals_0, UInt<5>("h5")) @[src/main/scala/sicore/Core.scala 102:16]
|
||||
node _alu_out_T_11 = xor(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 102:42]
|
||||
node _alu_out_T_12 = eq(csignals_0, UInt<5>("h6")) @[src/main/scala/sicore/Core.scala 103:16]
|
||||
node _alu_out_T_13 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 103:53]
|
||||
node _alu_out_T_14 = dshl(op1_data, _alu_out_T_13) @[src/main/scala/sicore/Core.scala 103:42]
|
||||
node _alu_out_T_15 = bits(_alu_out_T_14, 31, 0) @[src/main/scala/sicore/Core.scala 103:60]
|
||||
node _alu_out_T_16 = eq(csignals_0, UInt<5>("h7")) @[src/main/scala/sicore/Core.scala 104:16]
|
||||
node _alu_out_T_17 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 104:53]
|
||||
node _alu_out_T_18 = dshr(op1_data, _alu_out_T_17) @[src/main/scala/sicore/Core.scala 104:42]
|
||||
node _alu_out_T_19 = eq(csignals_0, UInt<5>("h8")) @[src/main/scala/sicore/Core.scala 105:16]
|
||||
node _alu_out_T_20 = asSInt(op1_data) @[src/main/scala/sicore/Core.scala 105:42]
|
||||
node _alu_out_T_21 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 105:60]
|
||||
node _alu_out_T_22 = dshr(_alu_out_T_20, _alu_out_T_21) @[src/main/scala/sicore/Core.scala 105:49]
|
||||
node _alu_out_T_23 = asUInt(_alu_out_T_22) @[src/main/scala/sicore/Core.scala 105:68]
|
||||
node _alu_out_T_24 = eq(csignals_0, UInt<5>("h9")) @[src/main/scala/sicore/Core.scala 106:16]
|
||||
node _alu_out_T_25 = asSInt(op1_data) @[src/main/scala/sicore/Core.scala 106:42]
|
||||
node _alu_out_T_26 = asSInt(op2_data) @[src/main/scala/sicore/Core.scala 106:60]
|
||||
node _alu_out_T_27 = lt(_alu_out_T_25, _alu_out_T_26) @[src/main/scala/sicore/Core.scala 106:49]
|
||||
node _alu_out_T_28 = eq(csignals_0, UInt<5>("hd")) @[src/main/scala/sicore/Core.scala 107:16]
|
||||
node _alu_out_T_29 = mux(_alu_out_T_28, op1_data, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _alu_out_T_30 = mux(_alu_out_T_24, _alu_out_T_27, _alu_out_T_29) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _alu_out_T_31 = mux(_alu_out_T_19, _alu_out_T_23, _alu_out_T_30) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
@ -181,22 +182,22 @@ circuit TopOrigin :
|
||||
node _alu_out_T_36 = mux(_alu_out_T_6, _alu_out_T_7, _alu_out_T_35) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _alu_out_T_37 = mux(_alu_out_T_3, _alu_out_T_5, _alu_out_T_36) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _alu_out_T_38 = mux(_alu_out_T, _alu_out_T_2, _alu_out_T_37) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node alu_out = _alu_out_T_38 @[src/main/scala/sicore/Core.scala 26:21 94:11]
|
||||
node alu_out = _alu_out_T_38 @[src/main/scala/sicore/Core.scala 27:21 95:11]
|
||||
node _pc_next_T = mux(jmp_flg, alu_out, pc_plus4) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _br_flg_T = eq(csignals_0, UInt<5>("hb")) @[src/main/scala/sicore/Core.scala 113:16]
|
||||
node _br_flg_T_1 = eq(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 113:41]
|
||||
node _br_flg_T_2 = eq(csignals_0, UInt<5>("hc")) @[src/main/scala/sicore/Core.scala 114:16]
|
||||
node _br_flg_T_3 = eq(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 114:42]
|
||||
node _br_flg_T_4 = eq(_br_flg_T_3, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 114:31]
|
||||
node _br_flg_T = eq(csignals_0, UInt<5>("hb")) @[src/main/scala/sicore/Core.scala 114:16]
|
||||
node _br_flg_T_1 = eq(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 114:41]
|
||||
node _br_flg_T_2 = eq(csignals_0, UInt<5>("hc")) @[src/main/scala/sicore/Core.scala 115:16]
|
||||
node _br_flg_T_3 = eq(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 115:42]
|
||||
node _br_flg_T_4 = eq(_br_flg_T_3, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 115:31]
|
||||
node _br_flg_T_5 = mux(_br_flg_T_2, _br_flg_T_4, UInt<1>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _br_flg_T_6 = mux(_br_flg_T, _br_flg_T_1, _br_flg_T_5) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node br_flg = _br_flg_T_6 @[src/main/scala/sicore/Core.scala 110:10 23:20]
|
||||
node _br_target_T = dshl(imm_i_sext, UInt<5>("h2")) @[src/main/scala/sicore/Core.scala 119:37]
|
||||
node _br_target_T_1 = add(pc_reg, _br_target_T) @[src/main/scala/sicore/Core.scala 119:23]
|
||||
node _br_target_T_2 = tail(_br_target_T_1, 1) @[src/main/scala/sicore/Core.scala 119:23]
|
||||
node br_target = bits(_br_target_T_2, 31, 0) @[src/main/scala/sicore/Core.scala 119:13 24:23]
|
||||
node br_flg = _br_flg_T_6 @[src/main/scala/sicore/Core.scala 111:10 24:20]
|
||||
node _br_target_T = dshl(imm_i_sext, UInt<5>("h2")) @[src/main/scala/sicore/Core.scala 120:37]
|
||||
node _br_target_T_1 = add(pc_reg, _br_target_T) @[src/main/scala/sicore/Core.scala 120:23]
|
||||
node _br_target_T_2 = tail(_br_target_T_1, 1) @[src/main/scala/sicore/Core.scala 120:23]
|
||||
node br_target = bits(_br_target_T_2, 31, 0) @[src/main/scala/sicore/Core.scala 120:13 25:23]
|
||||
node pc_next = mux(br_flg, br_target, _pc_next_T) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node rd_addr = bits(io_imem_inst, 15, 11) @[src/main/scala/sicore/Core.scala 41:21]
|
||||
node rd_addr = bits(io_imem_inst, 15, 11) @[src/main/scala/sicore/Core.scala 42:21]
|
||||
node _csignals_T_87 = mux(_csignals_T_35, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node _csignals_T_88 = mux(_csignals_T_33, UInt<2>("h0"), _csignals_T_87) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node _csignals_T_89 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_88) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
@ -251,60 +252,89 @@ circuit TopOrigin :
|
||||
node _csignals_T_136 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_135) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node _csignals_T_137 = mux(_csignals_T_3, UInt<3>("h0"), _csignals_T_136) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node csignals_5 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_137) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
|
||||
node _wb_data_T = eq(csignals_5, UInt<3>("h2")) @[src/main/scala/sicore/Core.scala 130:15]
|
||||
node _wb_data_T_1 = eq(csignals_5, UInt<3>("h3")) @[src/main/scala/sicore/Core.scala 131:15]
|
||||
node _wb_data_T = eq(csignals_5, UInt<3>("h2")) @[src/main/scala/sicore/Core.scala 131:15]
|
||||
node _wb_data_T_1 = eq(csignals_5, UInt<3>("h3")) @[src/main/scala/sicore/Core.scala 132:15]
|
||||
node _wb_data_T_2 = mux(_wb_data_T_1, pc_plus4, alu_out) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node wb_data = mux(_wb_data_T, io_dmem_rdata, _wb_data_T_2) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _T = eq(csignals_4, UInt<2>("h1")) @[src/main/scala/sicore/Core.scala 136:15]
|
||||
node _T_1 = neq(rd_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 136:36]
|
||||
node _T_2 = and(_T, _T_1) @[src/main/scala/sicore/Core.scala 136:25]
|
||||
node _GEN_0 = validif(_T_2, rd_addr) @[src/main/scala/sicore/Core.scala 136:45 137:12]
|
||||
node _GEN_1 = validif(_T_2, clock) @[src/main/scala/sicore/Core.scala 136:45 137:12]
|
||||
node _GEN_2 = mux(_T_2, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 136:45 137:12 16:20]
|
||||
node _GEN_3 = validif(_T_2, UInt<1>("h1")) @[src/main/scala/sicore/Core.scala 136:45 137:22]
|
||||
node _GEN_4 = validif(_T_2, wb_data) @[src/main/scala/sicore/Core.scala 136:45 137:22]
|
||||
node _io_exit_T = eq(io_imem_inst, UInt<32>("h114514")) @[src/main/scala/sicore/Core.scala 140:20]
|
||||
node _T_3 = asUInt(reset) @[src/main/scala/sicore/Core.scala 143:9]
|
||||
node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 143:9]
|
||||
node _T_5 = asUInt(reset) @[src/main/scala/sicore/Core.scala 144:9]
|
||||
node _T_6 = eq(_T_5, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 144:9]
|
||||
node _T_7 = asUInt(reset) @[src/main/scala/sicore/Core.scala 145:9]
|
||||
node _T_8 = eq(_T_7, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 145:9]
|
||||
node _T_9 = asUInt(reset) @[src/main/scala/sicore/Core.scala 146:9]
|
||||
node _T_10 = eq(_T_9, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 146:9]
|
||||
node _T_11 = asUInt(reset) @[src/main/scala/sicore/Core.scala 147:9]
|
||||
node _T_12 = eq(_T_11, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 147:9]
|
||||
node _T_13 = asUInt(reset) @[src/main/scala/sicore/Core.scala 148:9]
|
||||
node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 148:9]
|
||||
node _T_15 = asUInt(reset) @[src/main/scala/sicore/Core.scala 149:9]
|
||||
node _T_16 = eq(_T_15, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 149:9]
|
||||
node _T_17 = asUInt(reset) @[src/main/scala/sicore/Core.scala 150:9]
|
||||
node _T_18 = eq(_T_17, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 150:9]
|
||||
io_imem_addr <= pc_reg @[src/main/scala/sicore/Core.scala 20:16]
|
||||
io_dmem_addr <= alu_out @[src/main/scala/sicore/Core.scala 122:16]
|
||||
io_dmem_wen <= bits(csignals_3, 0, 0) @[src/main/scala/sicore/Core.scala 123:15]
|
||||
io_dmem_wdata <= rt_data @[src/main/scala/sicore/Core.scala 124:17]
|
||||
io_exit <= _io_exit_T @[src/main/scala/sicore/Core.scala 140:11]
|
||||
regfile.rs_data_MPORT.addr <= rs_addr @[src/main/scala/sicore/Core.scala 42:47]
|
||||
regfile.rs_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Core.scala 42:47]
|
||||
regfile.rs_data_MPORT.clk <= clock @[src/main/scala/sicore/Core.scala 42:47]
|
||||
regfile.rt_data_MPORT.addr <= rt_addr @[src/main/scala/sicore/Core.scala 43:47]
|
||||
regfile.rt_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Core.scala 43:47]
|
||||
regfile.rt_data_MPORT.clk <= clock @[src/main/scala/sicore/Core.scala 43:47]
|
||||
node _wb_addr_T = eq(csignals_5, UInt<3>("h1")) @[src/main/scala/sicore/Core.scala 140:15]
|
||||
node _wb_addr_T_1 = bits(io_imem_inst, 31, 26) @[src/main/scala/sicore/Core.scala 140:33]
|
||||
node _wb_addr_T_2 = eq(_wb_addr_T_1, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 140:42]
|
||||
node _wb_addr_T_3 = and(_wb_addr_T, _wb_addr_T_2) @[src/main/scala/sicore/Core.scala 140:26]
|
||||
node _wb_addr_T_4 = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/sicore/Core.scala 141:13]
|
||||
node _wb_addr_T_5 = eq(UInt<28>("hc000000"), _wb_addr_T_4) @[src/main/scala/sicore/Core.scala 141:13]
|
||||
node _wb_addr_T_6 = mux(_wb_addr_T_5, UInt<5>("h1f"), rt_addr) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node wb_addr = mux(_wb_addr_T_3, rd_addr, _wb_addr_T_6) @[src/main/scala/chisel3/util/Mux.scala 126:16]
|
||||
node _T = eq(csignals_4, UInt<2>("h1")) @[src/main/scala/sicore/Core.scala 146:15]
|
||||
node _T_1 = neq(wb_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 146:36]
|
||||
node _T_2 = and(_T, _T_1) @[src/main/scala/sicore/Core.scala 146:25]
|
||||
node _GEN_0 = validif(_T_2, wb_addr) @[src/main/scala/sicore/Core.scala 146:45 147:12]
|
||||
node _GEN_1 = validif(_T_2, clock) @[src/main/scala/sicore/Core.scala 146:45 147:12]
|
||||
node _GEN_2 = mux(_T_2, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 146:45 147:12 17:20]
|
||||
node _GEN_3 = validif(_T_2, UInt<1>("h1")) @[src/main/scala/sicore/Core.scala 146:45 147:22]
|
||||
node _GEN_4 = validif(_T_2, wb_data) @[src/main/scala/sicore/Core.scala 146:45 147:22]
|
||||
node _io_exit_T = eq(io_imem_inst, UInt<32>("h114514")) @[src/main/scala/sicore/Core.scala 150:20]
|
||||
node _T_3 = asUInt(reset) @[src/main/scala/sicore/Core.scala 153:9]
|
||||
node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 153:9]
|
||||
node _T_5 = asUInt(reset) @[src/main/scala/sicore/Core.scala 154:9]
|
||||
node _T_6 = eq(_T_5, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 154:9]
|
||||
node _T_7 = asUInt(reset) @[src/main/scala/sicore/Core.scala 155:9]
|
||||
node _T_8 = eq(_T_7, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 155:9]
|
||||
node _T_9 = asUInt(reset) @[src/main/scala/sicore/Core.scala 156:9]
|
||||
node _T_10 = eq(_T_9, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 156:9]
|
||||
node _T_11 = asUInt(reset) @[src/main/scala/sicore/Core.scala 157:9]
|
||||
node _T_12 = eq(_T_11, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 157:9]
|
||||
node _T_13 = asUInt(reset) @[src/main/scala/sicore/Core.scala 158:9]
|
||||
node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 158:9]
|
||||
node _T_15 = asUInt(reset) @[src/main/scala/sicore/Core.scala 159:9]
|
||||
node _T_16 = eq(_T_15, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 159:9]
|
||||
node _T_17 = asUInt(reset) @[src/main/scala/sicore/Core.scala 160:9]
|
||||
node _T_18 = eq(_T_17, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 160:9]
|
||||
node _T_19 = asUInt(reset) @[src/main/scala/sicore/Core.scala 161:9]
|
||||
node _T_20 = eq(_T_19, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 161:9]
|
||||
node _T_21 = asUInt(reset) @[src/main/scala/sicore/Core.scala 162:9]
|
||||
node _T_22 = eq(_T_21, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 162:9]
|
||||
node _T_23 = asUInt(reset) @[src/main/scala/sicore/Core.scala 164:9]
|
||||
node _T_24 = eq(_T_23, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 164:9]
|
||||
node _T_25 = asUInt(reset) @[src/main/scala/sicore/Core.scala 165:9]
|
||||
node _T_26 = eq(_T_25, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 165:9]
|
||||
node _T_27 = asUInt(reset) @[src/main/scala/sicore/Core.scala 166:9]
|
||||
node _T_28 = eq(_T_27, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 166:9]
|
||||
node _T_29 = asUInt(reset) @[src/main/scala/sicore/Core.scala 167:9]
|
||||
node _T_30 = eq(_T_29, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 167:9]
|
||||
io_imem_addr <= pc_reg @[src/main/scala/sicore/Core.scala 21:16]
|
||||
io_dmem_addr <= alu_out @[src/main/scala/sicore/Core.scala 123:16]
|
||||
io_dmem_wen <= bits(csignals_3, 0, 0) @[src/main/scala/sicore/Core.scala 124:15]
|
||||
io_dmem_wdata <= rt_data @[src/main/scala/sicore/Core.scala 125:17]
|
||||
io_exit <= _io_exit_T @[src/main/scala/sicore/Core.scala 150:11]
|
||||
regfile.rs_data_MPORT.addr <= rs_addr @[src/main/scala/sicore/Core.scala 43:47]
|
||||
regfile.rs_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Core.scala 43:47]
|
||||
regfile.rs_data_MPORT.clk <= clock @[src/main/scala/sicore/Core.scala 43:47]
|
||||
regfile.rt_data_MPORT.addr <= rt_addr @[src/main/scala/sicore/Core.scala 44:47]
|
||||
regfile.rt_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Core.scala 44:47]
|
||||
regfile.rt_data_MPORT.clk <= clock @[src/main/scala/sicore/Core.scala 44:47]
|
||||
regfile.MPORT_1.addr <= rt_addr @[src/main/scala/sicore/Core.scala 161:40]
|
||||
regfile.MPORT_1.en <= UInt<1>("h1") @[src/main/scala/sicore/Core.scala 161:40]
|
||||
regfile.MPORT_1.clk <= clock @[src/main/scala/sicore/Core.scala 161:40]
|
||||
regfile.MPORT.addr <= _GEN_0
|
||||
regfile.MPORT.en <= _GEN_2
|
||||
regfile.MPORT.clk <= _GEN_1
|
||||
regfile.MPORT.data <= _GEN_4
|
||||
regfile.MPORT.mask <= _GEN_3
|
||||
pc_reg <= mux(reset, UInt<32>("h0"), pc_next) @[src/main/scala/sicore/Core.scala 19:{23,23} 36:10]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "---------------\n") : printf @[src/main/scala/sicore/Core.scala 143:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "io.pc: 0x%x\ninst: 0x%x \n", pc_reg, io_imem_inst) : printf_1 @[src/main/scala/sicore/Core.scala 144:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_8), UInt<1>("h1")), "pc_next: 0x%x\n", pc_next) : printf_2 @[src/main/scala/sicore/Core.scala 145:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "rs_addr: 0x%x\n", rs_addr) : printf_3 @[src/main/scala/sicore/Core.scala 146:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "rd_addr: 0x%x\n", rd_addr) : printf_4 @[src/main/scala/sicore/Core.scala 147:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "rs_data: 0x%x\n", rs_data) : printf_5 @[src/main/scala/sicore/Core.scala 148:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "wb_data: 0x%x\n", wb_data) : printf_6 @[src/main/scala/sicore/Core.scala 149:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "---------------\n") : printf_7 @[src/main/scala/sicore/Core.scala 150:9]
|
||||
pc_reg <= mux(reset, UInt<32>("h0"), pc_next) @[src/main/scala/sicore/Core.scala 20:{23,23} 37:10]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "---------------\n") : printf @[src/main/scala/sicore/Core.scala 153:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "io.imem.inst: 0x%x\n", io_imem_inst) : printf_1 @[src/main/scala/sicore/Core.scala 154:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_8), UInt<1>("h1")), "io.pc: 0x%x\ninst: 0x%b \n", pc_reg, io_imem_inst) : printf_2 @[src/main/scala/sicore/Core.scala 155:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "pc_next: 0x%x\n", pc_next) : printf_3 @[src/main/scala/sicore/Core.scala 156:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "exe_fun: 0x%x\n", csignals_0) : printf_4 @[src/main/scala/sicore/Core.scala 157:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "rs_addr: 0x%x\n", rs_addr) : printf_5 @[src/main/scala/sicore/Core.scala 158:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "rt_addr: 0x%x\n", rt_addr) : printf_6 @[src/main/scala/sicore/Core.scala 159:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "rd_addr: 0x%x\n", rd_addr) : printf_7 @[src/main/scala/sicore/Core.scala 160:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_20), UInt<1>("h1")), "reg: 0x%x\n", regfile.MPORT_1.data) : printf_8 @[src/main/scala/sicore/Core.scala 161:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_22), UInt<1>("h1")), "rf_wen: 0x%x\n", csignals_4) : printf_9 @[src/main/scala/sicore/Core.scala 162:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_24), UInt<1>("h1")), "rs_data: 0x%x\n", rs_data) : printf_10 @[src/main/scala/sicore/Core.scala 164:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_26), UInt<1>("h1")), "rt_data: 0x%x\n", rt_data) : printf_11 @[src/main/scala/sicore/Core.scala 165:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_28), UInt<1>("h1")), "wb_data: 0x%x\n", wb_data) : printf_12 @[src/main/scala/sicore/Core.scala 166:9]
|
||||
printf(clock, and(and(UInt<1>("h1"), _T_30), UInt<1>("h1")), "---------------\n") : printf_13 @[src/main/scala/sicore/Core.scala 167:9]
|
||||
|
||||
module Memory : @[src/main/scala/sicore/Memory.scala 24:7]
|
||||
input clock : Clock @[src/main/scala/sicore/Memory.scala 24:7]
|
||||
|
||||
Reference in New Issue
Block a user