Fix bugs in Sicore
This commit is contained in:
133
TopOrigin.sv
133
TopOrigin.sv
@ -51,30 +51,31 @@ module Core(
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wire [31:0] _regfile_ext_R1_data;
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reg [31:0] pc_reg;
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wire [31:0] _pc_plus4_T = pc_reg + 32'h4;
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wire [9:0] _GEN = {io_imem_inst[31:28], io_imem_inst[5:0]};
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wire jmp_flg = io_imem_inst[31:28] == 4'h3 | _GEN == 10'h8;
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wire [31:0] rs_data = (|(io_imem_inst[25:21])) ? _regfile_ext_R1_data : 32'h0;
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wire [31:0] rt_data = (|(io_imem_inst[20:16])) ? _regfile_ext_R0_data : 32'h0;
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wire [11:0] _GEN_0 = {io_imem_inst[31:26], io_imem_inst[5:0]};
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wire _csignals_T_5 = _GEN_0 == 12'h20;
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wire _csignals_T_7 = io_imem_inst[31:28] == 4'h8;
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wire _csignals_T_9 = _GEN_0 == 12'h22;
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wire _csignals_T_11 = _GEN_0 == 12'h24;
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wire _csignals_T_13 = _GEN_0 == 12'h25;
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wire _csignals_T_15 = _GEN_0 == 12'h26;
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wire _csignals_T_17 = io_imem_inst[31:28] == 4'hC;
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wire _csignals_T_19 = io_imem_inst[31:28] == 4'hD;
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wire _csignals_T_21 = _GEN_0 == 12'h2A;
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wire _csignals_T_23 = io_imem_inst[31:28] == 4'h4;
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wire _csignals_T_25 = io_imem_inst[31:28] == 4'h5;
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wire [16:0] _GEN_1 = {io_imem_inst[31:21], io_imem_inst[5:0]};
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wire _csignals_T_27 = _GEN_1 == 17'h0;
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wire _csignals_T_29 = _GEN_1 == 17'h2;
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wire _csignals_T_31 = _GEN_1 == 17'h3;
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wire _csignals_T_33 = io_imem_inst[31:28] == 4'h3;
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wire _csignals_T_35 = _GEN == 10'h8;
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wire [11:0] _GEN = {io_imem_inst[31:26], io_imem_inst[5:0]};
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wire jmp_flg = io_imem_inst[31:26] == 6'h3 | _GEN == 12'h8;
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wire [31:0] rs_data = (|(io_imem_inst[25:21])) ? _regfile_ext_R0_data : 32'h0;
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wire [31:0] rt_data = (|(io_imem_inst[20:16])) ? _regfile_ext_R1_data : 32'h0;
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wire _csignals_T_1 = io_imem_inst[31:26] == 6'h23;
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wire _csignals_T_3 = io_imem_inst[31:26] == 6'h2B;
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wire _csignals_T_5 = _GEN == 12'h20;
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wire _csignals_T_7 = io_imem_inst[31:26] == 6'h8;
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wire _csignals_T_9 = _GEN == 12'h22;
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wire _csignals_T_11 = _GEN == 12'h24;
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wire _csignals_T_13 = _GEN == 12'h25;
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wire _csignals_T_15 = _GEN == 12'h26;
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wire _csignals_T_17 = io_imem_inst[31:26] == 6'hC;
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wire _csignals_T_19 = io_imem_inst[31:26] == 6'hD;
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wire _csignals_T_21 = _GEN == 12'h2A;
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wire _csignals_T_23 = io_imem_inst[31:26] == 6'h4;
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wire _csignals_T_25 = io_imem_inst[31:26] == 6'h5;
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wire [16:0] _GEN_0 = {io_imem_inst[31:21], io_imem_inst[5:0]};
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wire _csignals_T_27 = _GEN_0 == 17'h0;
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wire _csignals_T_29 = _GEN_0 == 17'h2;
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wire _csignals_T_31 = _GEN_0 == 17'h3;
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wire _csignals_T_33 = io_imem_inst[31:26] == 6'h3;
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wire _csignals_T_35 = _GEN == 12'h8;
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wire [4:0] csignals_0 =
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_csignals_T_5 | _csignals_T_7
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_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7
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? 5'h1
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: _csignals_T_9
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? 5'h2
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@ -103,15 +104,18 @@ module Core(
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: _csignals_T_33
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? 5'h1
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: _csignals_T_35 ? 5'hD : 5'h0;
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wire _GEN_2 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31;
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wire _GEN_3 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_2;
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wire _GEN_1 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31;
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wire _GEN_2 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_1;
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wire [1:0] csignals_1 =
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_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
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| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3 | ~_csignals_T_33
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_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7 | _csignals_T_9
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| _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17 | _csignals_T_19
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| _GEN_2 | ~_csignals_T_33
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? 2'h1
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: 2'h2;
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wire [2:0] _csignals_T_85 =
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_csignals_T_5
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wire [2:0] csignals_2 =
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_csignals_T_1 | _csignals_T_3
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? 3'h2
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: _csignals_T_5
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? 3'h1
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: _csignals_T_7
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? 3'h2
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@ -119,22 +123,37 @@ module Core(
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? 3'h1
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: _csignals_T_17 | _csignals_T_19
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? 3'h2
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: _GEN_3 ? 3'h1 : _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35};
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wire _GEN_4 = _csignals_T_23 | _csignals_T_25;
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wire _GEN_5 =
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: _GEN_2 ? 3'h1 : _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35};
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wire _GEN_3 = _csignals_T_23 | _csignals_T_25;
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wire _GEN_4 =
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_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
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| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21;
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wire [1:0] _csignals_T_136 =
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_GEN_5 ? 2'h1 : _GEN_4 ? 2'h0 : _GEN_2 ? 2'h1 : {2{_csignals_T_33}};
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wire [1:0] csignals_4 =
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_csignals_T_1
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? 2'h1
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: _csignals_T_3
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? 2'h0
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: _GEN_4
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? 2'h1
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: _GEN_3
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? 2'h0
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: {1'h0,
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_csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33};
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wire [2:0] csignals_5 =
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_csignals_T_1
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? 3'h2
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: _csignals_T_3
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? 3'h0
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: _GEN_4 ? 3'h1 : _GEN_3 ? 3'h0 : _GEN_1 ? 3'h1 : _csignals_T_33 ? 3'h3 : 3'h0;
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wire _op1_data_T = csignals_1 == 2'h1;
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wire _op1_data_T_1 = csignals_1 == 2'h2;
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wire [31:0] op1_data = _op1_data_T ? rs_data : _op1_data_T_1 ? pc_reg : 32'h0;
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wire [31:0] op2_data =
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_csignals_T_85 == 3'h1
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csignals_2 == 3'h1
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? rt_data
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: _csignals_T_85 == 3'h2
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: csignals_2 == 3'h2
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? {{16{io_imem_inst[15]}}, io_imem_inst[15:0]}
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: _csignals_T_85 == 3'h4 ? {4'h0, io_imem_inst[25:0], 2'h0} : 32'h0;
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: csignals_2 == 3'h4 ? {4'h0, io_imem_inst[25:0], 2'h0} : 32'h0;
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wire _alu_out_T = csignals_0 == 5'h1;
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wire [31:0] _alu_out_T_1 = op1_data + op2_data;
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wire _alu_out_T_3 = csignals_0 == 5'h2;
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@ -148,13 +167,13 @@ module Core(
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wire _alu_out_T_12 = csignals_0 == 5'h6;
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wire [62:0] _alu_out_T_14 = {31'h0, op1_data} << op2_data[4:0];
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wire _alu_out_T_16 = csignals_0 == 5'h7;
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wire [31:0] _GEN_6 = {27'h0, op2_data[4:0]};
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wire [31:0] _alu_out_T_18 = op1_data >> _GEN_6;
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wire [31:0] _GEN_5 = {27'h0, op2_data[4:0]};
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wire [31:0] _alu_out_T_18 = op1_data >> _GEN_5;
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wire _alu_out_T_19 = csignals_0 == 5'h8;
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wire [31:0] _alu_out_T_22 = $signed($signed(op1_data) >>> _GEN_6);
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wire [31:0] _alu_out_T_22 = $signed($signed(op1_data) >>> _GEN_5);
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wire _alu_out_T_24 = csignals_0 == 5'h9;
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wire _alu_out_T_28 = csignals_0 == 5'hD;
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wire [31:0] _GEN_7 = {31'h0, $signed(op1_data) < $signed(op2_data)};
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wire [31:0] _GEN_6 = {31'h0, $signed(op1_data) < $signed(op2_data)};
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wire [31:0] alu_out =
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_alu_out_T
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? _alu_out_T_1
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@ -173,24 +192,34 @@ module Core(
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: _alu_out_T_19
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? _alu_out_T_22
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: _alu_out_T_24
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? _GEN_7
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? _GEN_6
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: _alu_out_T_28 ? op1_data : 32'h0;
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wire _br_flg_T_3 = op1_data == op2_data;
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wire br_flg =
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csignals_0 == 5'hB ? _br_flg_T_3 : csignals_0 == 5'hC & ~_br_flg_T_3;
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wire [31:0] br_target = {{14{io_imem_inst[15]}}, io_imem_inst[15:0], 2'h0} + pc_reg;
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wire [31:0] wb_data =
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_csignals_T_136 == 2'h2 ? io_dmem_rdata : (&_csignals_T_136) ? _pc_plus4_T : alu_out;
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csignals_5 == 3'h2 ? io_dmem_rdata : csignals_5 == 3'h3 ? _pc_plus4_T : alu_out;
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wire [4:0] wb_addr =
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csignals_5 == 3'h1 & io_imem_inst[31:26] == 6'h0
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? io_imem_inst[15:11]
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: io_imem_inst[31:26] == 6'h3 ? 5'h1F : io_imem_inst[20:16];
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`ifndef SYNTHESIS
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always @(posedge clock) begin
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if ((`PRINTF_COND_) & ~reset) begin
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$fwrite(32'h80000002, "---------------\n");
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$fwrite(32'h80000002, "io.pc: 0x%x\ninst: 0x%x \n", pc_reg, io_imem_inst);
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$fwrite(32'h80000002, "io.imem.inst: 0x%x\n", io_imem_inst);
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$fwrite(32'h80000002, "io.pc: 0x%x\ninst: 0x%b \n", pc_reg, io_imem_inst);
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$fwrite(32'h80000002, "pc_next: 0x%x\n",
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br_flg ? br_target : jmp_flg ? alu_out : _pc_plus4_T);
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$fwrite(32'h80000002, "exe_fun: 0x%x\n", csignals_0);
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$fwrite(32'h80000002, "rs_addr: 0x%x\n", io_imem_inst[25:21]);
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$fwrite(32'h80000002, "rt_addr: 0x%x\n", io_imem_inst[20:16]);
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$fwrite(32'h80000002, "rd_addr: 0x%x\n", io_imem_inst[15:11]);
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$fwrite(32'h80000002, "reg: 0x%x\n", _regfile_ext_R1_data);
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$fwrite(32'h80000002, "rf_wen: 0x%x\n", csignals_4);
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$fwrite(32'h80000002, "rs_data: 0x%x\n", rs_data);
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$fwrite(32'h80000002, "rt_data: 0x%x\n", rt_data);
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$fwrite(32'h80000002, "wb_data: 0x%x\n", wb_data);
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$fwrite(32'h80000002, "---------------\n");
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end
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@ -219,7 +248,7 @@ module Core(
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else if (_alu_out_T_19)
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pc_reg <= _alu_out_T_22;
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else if (_alu_out_T_24)
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pc_reg <= _GEN_7;
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pc_reg <= _GEN_6;
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else if (_alu_out_T_28) begin
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if (_op1_data_T)
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pc_reg <= rs_data;
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@ -233,24 +262,22 @@ module Core(
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pc_reg <= _pc_plus4_T;
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end // always @(posedge)
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regfile_32x32 regfile_ext (
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.R0_addr (io_imem_inst[20:16]),
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.R0_addr (io_imem_inst[25:21]),
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.R0_en (1'h1),
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.R0_clk (clock),
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.R0_data (_regfile_ext_R0_data),
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.R1_addr (io_imem_inst[25:21]),
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.R1_addr (io_imem_inst[20:16]),
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.R1_en (1'h1),
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.R1_clk (clock),
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.R1_data (_regfile_ext_R1_data),
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.W0_addr (io_imem_inst[15:11]),
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.W0_en
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(_GEN_5 | ~_GEN_4
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& (_csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33)),
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.W0_addr (wb_addr),
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.W0_en (csignals_4 == 2'h1 & (|wb_addr)),
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.W0_clk (clock),
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.W0_data (wb_data)
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);
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assign io_imem_addr = pc_reg;
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assign io_dmem_addr = alu_out;
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assign io_dmem_wen = 1'h0;
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assign io_dmem_wen = ~_csignals_T_1 & _csignals_T_3;
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assign io_dmem_wdata = rt_data;
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assign io_exit = io_imem_inst == 32'h114514;
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endmodule
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@ -320,7 +347,7 @@ module mem_4096x8(
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end // always @(posedge)
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`ifdef ENABLE_INITIAL_MEM_
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initial
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$readmemh("src/hex/addi.hex", Memory);
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$readmemh("src/hex/mem.hex", Memory);
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`endif // ENABLE_INITIAL_MEM_
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assign R0_data = R0_en ? Memory[R0_addr] : 8'bx;
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assign R1_data = R1_en ? Memory[R1_addr] : 8'bx;
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@ -1 +0,0 @@
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[[{},{}],{}]
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@ -1 +0,0 @@
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-2109952146
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-2132504562
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@ -1 +0,0 @@
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{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":3342},"type":"LinePosition"}}
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@ -1,3 +0,0 @@
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[0m[[0m[0mdebug[0m] [0m[0mnot up to date. inChanged = true, force = false[0m
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[0m[[0m[0mdebug[0m] [0m[0mUpdating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/"), "micore-build-build-build")...[0m
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[0m[[0m[0mdebug[0m] [0m[0mDone updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/"), "micore-build-build-build")[0m
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@ -1 +0,0 @@
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["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]
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@ -1 +0,0 @@
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[]
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@ -1,6 +0,0 @@
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[0m[[0m[0mdebug[0m] [0m[0m[zinc] IncrementalCompile -----------[0m
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[0m[[0m[0mdebug[0m] [0m[0mIncrementalCompile.incrementalCompile[0m
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[0m[[0m[0mdebug[0m] [0m[0mprevious = Stamps for: 0 products, 0 sources, 0 libraries[0m
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[0m[[0m[0mdebug[0m] [0m[0mcurrent source = Set()[0m
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[0m[[0m[0mdebug[0m] [0m[0m> initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set())[0m
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[0m[[0m[0mdebug[0m] [0m[0mFull compilation, no sources in previous analysis.[0m
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@ -1,2 +0,0 @@
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[0m[[0m[0mdebug[0m] [0m[0mCopy resource mappings: [0m
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[0m[[0m[0mdebug[0m] [0m[0m [0m
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@ -1 +0,0 @@
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/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
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@ -1,5 +0,0 @@
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[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
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[0m[[0m[0mdebug[0m] [0m[0mAbout to delete class files:[0m
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[0m[[0m[0mdebug[0m] [0m[0mWe backup class files:[0m
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[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
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[0m[[0m[0mdebug[0m] [0m[0mRemoving the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
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@ -1 +0,0 @@
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/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
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/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
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[[{},{}],{}]
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-2083014398
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-2132504562
|
||||
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||||
{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":3342},"type":"LinePosition"}}
|
||||
@ -1,3 +0,0 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0mnot up to date. inChanged = true, force = false[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mUpdating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build")...[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mDone updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build")[0m
|
||||
@ -1 +0,0 @@
|
||||
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]
|
||||
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|
||||
[]
|
||||
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|
||||
[0m[[0m[0mdebug[0m] [0m[0m[zinc] IncrementalCompile -----------[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mIncrementalCompile.incrementalCompile[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mprevious = Stamps for: 0 products, 0 sources, 0 libraries[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mcurrent source = Set()[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m> initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set())[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mFull compilation, no sources in previous analysis.[0m
|
||||
@ -1,2 +0,0 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0mCopy resource mappings: [0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m [0m
|
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/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes
|
||||
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|
||||
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mAbout to delete class files:[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mWe backup class files:[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mRemoving the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
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|
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|
||||
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/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes
|
||||
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/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes
|
||||
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||||
|
||||
@ -1 +0,0 @@
|
||||
|
||||
0
project/target/config-classes/$948efd6ee3ba8f09824e.cache → project/target/config-classes/$87709882d327edfdfbe4.cache
Executable file → Normal file
0
project/target/config-classes/$948efd6ee3ba8f09824e.cache → project/target/config-classes/$87709882d327edfdfbe4.cache
Executable file → Normal file
0
project/target/config-classes/$2b8c65d0a3a3f42e1015.cache → project/target/config-classes/$92eace74df3dd60b2407.cache
Executable file → Normal file
0
project/target/config-classes/$2b8c65d0a3a3f42e1015.cache → project/target/config-classes/$92eace74df3dd60b2407.cache
Executable file → Normal file
0
project/target/config-classes/$add241eb0c1a6339f011.cache → project/target/config-classes/$b99baa0e80f987ddc888.cache
Executable file → Normal file
0
project/target/config-classes/$add241eb0c1a6339f011.cache → project/target/config-classes/$b99baa0e80f987ddc888.cache
Executable file → Normal file
0
project/target/config-classes/$eac2b8278586e49cb092.cache → project/target/config-classes/$bc99ac17cdce7fb9c74c.cache
Executable file → Normal file
0
project/target/config-classes/$eac2b8278586e49cb092.cache → project/target/config-classes/$bc99ac17cdce7fb9c74c.cache
Executable file → Normal file
0
project/target/scala-2.12/sbt-1.0/sync/copy-resource
Executable file → Normal file
0
project/target/scala-2.12/sbt-1.0/sync/copy-resource
Executable file → Normal file
0
project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs
Executable file → Normal file
0
project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs
Executable file → Normal file
0
project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/output
Executable file → Normal file
0
project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/output
Executable file → Normal file
0
project/target/streams/_global/_global/_global/streams/out
Executable file → Normal file
0
project/target/streams/_global/_global/_global/streams/out
Executable file → Normal file
0
project/target/streams/_global/csrConfiguration/_global/streams/out
Executable file → Normal file
0
project/target/streams/_global/csrConfiguration/_global/streams/out
Executable file → Normal file
0
project/target/streams/_global/csrProject/_global/streams/out
Executable file → Normal file
0
project/target/streams/_global/csrProject/_global/streams/out
Executable file → Normal file
0
project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp
Executable file → Normal file
0
project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp
Executable file → Normal file
2
project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp
Executable file → Normal file
2
project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp
Executable file → Normal file
@ -1 +1 @@
|
||||
{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}
|
||||
{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/project/ddca/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/project/ddca/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user