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Try to rebuild the core

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This commit is contained in:
CGH0S7
2024-12-30 20:09:10 +08:00
parent e8e6b6ddb3
commit de44f7d8d3
141 changed files with 817 additions and 855 deletions
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@ -53,52 +53,47 @@ module Core(
output [31:0] io_gp
);
wire [31:0] mem_wb_data;
wire exe_jmp_flg;
wire exe_br_flg;
wire [31:0] _regfile_ext_R1_data;
wire [31:0] _regfile_ext_R2_data;
reg [31:0] id_reg_pc;
reg [31:0] id_reg_inst;
reg [31:0] exe_reg_pc;
reg [4:0] exe_reg_wb_addr;
reg [31:0] exe_reg_op1_data;
reg [31:0] exe_reg_op2_data;
reg [31:0] exe_reg_rs2_data;
reg [4:0] exe_reg_exe_fun;
reg [1:0] exe_reg_mem_wen;
reg [1:0] exe_reg_rf_wen;
reg [2:0] exe_reg_wb_sel;
reg [31:0] exe_reg_imm_b_sext;
reg [31:0] mem_reg_pc;
reg [4:0] mem_reg_wb_addr;
reg [31:0] mem_reg_rs2_data;
reg [1:0] mem_reg_mem_wen;
reg [1:0] mem_reg_rf_wen;
reg [2:0] mem_reg_wb_sel;
reg [31:0] mem_reg_alu_out;
reg [4:0] wb_reg_wb_addr;
reg [1:0] wb_reg_rf_wen;
reg [31:0] wb_reg_wb_data;
reg [31:0] if_reg_pc;
wire _id_inst_T = exe_br_flg | exe_jmp_flg;
wire _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1;
wire stall_flg =
wire [31:0] mem_wb_data;
wire exe_jmp_flg;
wire exe_br_flg;
wire [31:0] _regfile_ext_R1_data;
wire [31:0] _regfile_ext_R2_data;
reg [31:0] id_reg_pc;
reg [31:0] id_reg_inst;
reg [31:0] exe_reg_pc;
reg [4:0] exe_reg_wb_addr;
reg [31:0] exe_reg_op1_data;
reg [31:0] exe_reg_op2_data;
reg [31:0] exe_reg_rs2_data;
reg [4:0] exe_reg_exe_fun;
reg [1:0] exe_reg_mem_wen;
reg [1:0] exe_reg_rf_wen;
reg [2:0] exe_reg_wb_sel;
reg [31:0] exe_reg_imm_b_sext;
reg [31:0] mem_reg_pc;
reg [4:0] mem_reg_wb_addr;
reg [31:0] mem_reg_rs2_data;
reg [1:0] mem_reg_mem_wen;
reg [1:0] mem_reg_rf_wen;
reg [2:0] mem_reg_wb_sel;
reg [31:0] mem_reg_alu_out;
reg [4:0] wb_reg_wb_addr;
reg [1:0] wb_reg_rf_wen;
reg [31:0] wb_reg_wb_data;
reg [31:0] if_reg_pc;
wire _id_inst_T = exe_br_flg | exe_jmp_flg;
wire _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1;
wire stall_flg =
_id_rs2_data_hazard_T & (|(id_reg_inst[25:21]))
& id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T
& (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst;
wire _id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1;
wire _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1;
wire [31:0] id_rs1_data =
id_inst[25:21] == 5'h0
? 32'h0
: id_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2
? mem_wb_data
: id_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5
? wb_reg_wb_data
: _regfile_ext_R2_data;
wire [31:0] id_rs2_data =
wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst;
wire _id_rs1_data_T = id_inst[25:21] == 5'h0;
wire _id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1;
wire _id_rs1_data_T_3 = id_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2;
wire _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1;
wire _id_rs1_data_T_6 = id_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5;
wire [31:0] id_rs2_data =
id_inst[20:16] == 5'h0
? 32'h0
: id_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2
@ -106,24 +101,31 @@ module Core(
: id_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5
? wb_reg_wb_data
: _regfile_ext_R1_data;
wire [16:0] _GEN = {id_inst[31:26], id_inst[10:0]};
wire _csignals_T_5 = _GEN == 17'h20;
wire [19:0] _GEN_0 = {id_inst[31:28], id_inst[15:0]};
wire _csignals_T_7 = _GEN_0 == 20'h80000;
wire _csignals_T_9 = _GEN == 17'h22;
wire _csignals_T_11 = _GEN == 17'h24;
wire _csignals_T_13 = _GEN == 17'h25;
wire _csignals_T_15 = _GEN == 17'h26;
wire _csignals_T_17 = _GEN_0 == 20'hC0000;
wire _csignals_T_19 = _GEN_0 == 20'hD0000;
wire _csignals_T_21 = _GEN == 17'h2A;
wire _csignals_T_23 = _GEN_0 == 20'h40000;
wire _csignals_T_25 = _GEN_0 == 20'h50000;
wire _csignals_T_27 = id_inst == 32'hC000000;
wire _csignals_T_29 = {id_inst[31:22], id_inst[9:0]} == 20'h78000;
wire _GEN_1 = _csignals_T_23 | _csignals_T_25;
wire _GEN_2 = _csignals_T_21 | _GEN_1;
wire [2:0] _csignals_T_70 =
wire [16:0] _GEN = {id_inst[31:26], id_inst[10:0]};
wire _csignals_T_5 = _GEN == 17'h20;
wire _csignals_T_7 = id_inst[31:28] == 4'h8;
wire _csignals_T_9 = _GEN == 17'h22;
wire _csignals_T_11 = _GEN == 17'h24;
wire _csignals_T_13 = _GEN == 17'h25;
wire _csignals_T_15 = _GEN == 17'h26;
wire _csignals_T_17 = id_inst[31:28] == 4'hC;
wire _csignals_T_19 = id_inst[31:28] == 4'hD;
wire _csignals_T_21 = _GEN == 17'h2A;
wire _csignals_T_23 = id_inst[31:28] == 4'h4;
wire _csignals_T_25 = id_inst[31:28] == 4'h5;
wire _csignals_T_27 = id_inst[31:28] == 4'h3;
wire _csignals_T_29 = id_inst[31:23] == 9'h1E0;
wire _GEN_0 = _csignals_T_27 | _csignals_T_29;
wire [4:0] _csignals_T_31 = {4'h0, _GEN_0};
wire _GEN_1 = _csignals_T_5 | _csignals_T_7;
wire _GEN_2 = _csignals_T_23 | _csignals_T_25;
wire _GEN_3 = _csignals_T_21 | _GEN_2;
wire [1:0] csignals_1 =
_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3
? 2'h1
: _csignals_T_27 ? 2'h2 : {1'h0, ~_csignals_T_29};
wire [2:0] _csignals_T_70 =
_csignals_T_5
? 3'h1
: _csignals_T_7
@ -132,28 +134,28 @@ module Core(
? 3'h1
: _csignals_T_17 | _csignals_T_19
? 3'h2
: _GEN_2 ? 3'h1 : _csignals_T_27 ? 3'h4 : {_csignals_T_29, 2'h1};
wire [3:0][31:0] _GEN_3 =
{{{27'h0, id_inst[15:11]}}, {32'h0}, {id_reg_pc}, {id_rs1_data}};
wire [31:0] id_op1_data =
_GEN_3[_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_2
? 2'h0
: _csignals_T_27 ? 2'h1 : {_csignals_T_29, 1'h0}];
wire [33:0] id_op2_data =
: _GEN_3 ? 3'h1 : _csignals_T_27 ? 3'h4 : {_csignals_T_29, 2'h1};
wire [1:0] _csignals_T_87 = {1'h0, _GEN_0};
wire _GEN_4 =
_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21;
wire [2:0] _csignals_T_100 = {2'h0, _csignals_T_29};
wire _id_op1_data_T = csignals_1 == 2'h1;
wire _id_op1_data_T_1 = csignals_1 == 2'h2;
wire [35:0] id_op2_data =
_csignals_T_70 == 3'h1
? {2'h0, id_rs2_data}
? {4'h0, id_rs2_data}
: _csignals_T_70 == 3'h2
? {2'h0, {16{id_inst[15]}}, id_inst[15:0]}
? {4'h0, {16{id_inst[15]}}, id_inst[15:0]}
: _csignals_T_70 == 3'h3
? {2'h0, {22{id_inst[15]}}, id_inst[15:11], id_inst[25:21]}
? {4'h0, {22{id_inst[15]}}, id_inst[15:11], id_inst[25:21]}
: _csignals_T_70 == 3'h4
? {{6{id_inst[23]}}, id_inst[25:0], 2'h0}
: {2'h0, _csignals_T_70 == 3'h5 ? {id_inst[15:0], 16'h0} : 32'h0};
wire [31:0] _exe_alu_out_T_30 = exe_reg_op1_data + exe_reg_op2_data;
wire [62:0] _exe_alu_out_T_14 = {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
wire [31:0] _GEN_4 = {27'h0, exe_reg_op2_data[4:0]};
wire [31:0] _exe_alu_out_T_46 =
? {{6{id_inst[23]}}, id_inst[25:0], 4'h0}
: {4'h0, _csignals_T_70 == 3'h5 ? {id_inst[15:0], 16'h0} : 32'h0};
wire [31:0] _exe_alu_out_T_30 = exe_reg_op1_data + exe_reg_op2_data;
wire [62:0] _exe_alu_out_T_14 = {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
wire [31:0] _GEN_5 = {27'h0, exe_reg_op2_data[4:0]};
wire [31:0] _exe_alu_out_T_46 =
exe_reg_exe_fun == 5'h1
? _exe_alu_out_T_30
: exe_reg_exe_fun == 5'h2
@ -167,9 +169,9 @@ module Core(
: exe_reg_exe_fun == 5'h6
? _exe_alu_out_T_14[31:0]
: exe_reg_exe_fun == 5'h7
? exe_reg_op1_data >> _GEN_4
? exe_reg_op1_data >> _GEN_5
: exe_reg_exe_fun == 5'h8
? $signed($signed(exe_reg_op1_data) >>> _GEN_4)
? $signed($signed(exe_reg_op1_data) >>> _GEN_5)
: exe_reg_exe_fun == 5'h9
? {31'h0,
$signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)}
@ -180,7 +182,7 @@ module Core(
: exe_reg_exe_fun == 5'h12
? exe_reg_op1_data
: 32'h0;
wire _exe_br_flg_T_3 = exe_reg_op1_data == exe_reg_op2_data;
wire _exe_br_flg_T_3 = exe_reg_op1_data == exe_reg_op2_data;
assign exe_br_flg =
exe_reg_exe_fun == 5'hB
? _exe_br_flg_T_3
@ -193,18 +195,56 @@ module Core(
`ifndef SYNTHESIS
always @(posedge clock) begin
if ((`PRINTF_COND_) & ~reset) begin
automatic logic [31:0] id_rs1_data =
_id_rs1_data_T
? 32'h0
: _id_rs1_data_T_3
? mem_wb_data
: _id_rs1_data_T_6 ? wb_reg_wb_data : _regfile_ext_R2_data;
$fwrite(32'h80000002, "---------------------\n");
$fwrite(32'h80000002, "if_reg_pc: 0x%x\n", if_reg_pc);
$fwrite(32'h80000002, "id_reg_pc: 0x%x\n", id_reg_pc);
$fwrite(32'h80000002, "id_reg_inst: 0x%x\n", id_reg_inst);
$fwrite(32'h80000002, "id_inst: 0x%x\n", id_inst);
$fwrite(32'h80000002, "id_rs1_addr: 0x%x\n", id_inst[25:21]);
$fwrite(32'h80000002, "id_rs2_addr: 0x%x\n", id_inst[20:16]);
$fwrite(32'h80000002, "id_wb_addr: 0x%x\n", id_inst[15:11]);
$fwrite(32'h80000002, "id_exe_fun: 0x%x\n",
_GEN_1
? 5'h1
: _csignals_T_9
? 5'h2
: _csignals_T_11
? 5'h3
: _csignals_T_13
? 5'h4
: _csignals_T_15
? 5'h5
: _csignals_T_17
? 5'h3
: _csignals_T_19
? 5'h4
: _csignals_T_21
? 5'h9
: _csignals_T_23
? 5'hB
: _csignals_T_25
? 5'hC
: _csignals_T_31);
$fwrite(32'h80000002, "id_op1_sel: 0x%x\n", csignals_1);
$fwrite(32'h80000002, "id_op1_data: 0x%x\n",
_id_op1_data_T ? id_rs1_data : _id_op1_data_T_1 ? id_reg_pc : 32'h0);
$fwrite(32'h80000002, "id_op2_sel: 0x%x\n", _csignals_T_70);
$fwrite(32'h80000002, "id_op2_data: 0x%x\n", id_op2_data);
$fwrite(32'h80000002, "id_mem_wen: 0x%x\n", 2'h0);
$fwrite(32'h80000002, "id_rf_wen: 0x%x\n",
_GEN_4 ? 2'h1 : _GEN_2 ? 2'h0 : _csignals_T_87);
$fwrite(32'h80000002, "id_wb_sel: 0x%x\n",
_GEN_4 ? 3'h1 : _GEN_2 ? 3'h0 : _csignals_T_27 ? 3'h3 : _csignals_T_100);
$fwrite(32'h80000002, "id_rs1_data: 0x%x\n", id_rs1_data);
$fwrite(32'h80000002, "id_rs2_data: 0x%x\n", id_rs2_data);
$fwrite(32'h80000002, "exe_reg_pc: 0x%x\n", exe_reg_pc);
$fwrite(32'h80000002, "exe_reg_op1_data: 0x%x\n", id_op1_data);
$fwrite(32'h80000002, "exe_reg_op2_data: 0x%x\n", id_op2_data);
$fwrite(32'h80000002, "exe_alu_out: 0x%x\n", _exe_alu_out_T_46);
$fwrite(32'h80000002, "mem_reg_pc: 0x%x\n", mem_reg_pc);
$fwrite(32'h80000002, "mem_reg_alu_out: 0x%x\n", mem_reg_alu_out);
$fwrite(32'h80000002, "mem_wb_data: 0x%x\n", mem_wb_data);
$fwrite(32'h80000002, "wb_reg_wb_data: 0%x\n", wb_reg_wb_data);
$fwrite(32'h80000002, "---------------------\n");
@ -238,8 +278,6 @@ module Core(
if_reg_pc <= 32'h400000;
end
else begin
automatic logic _GEN_5;
_GEN_5 = _csignals_T_27 | _csignals_T_29;
if (~stall_flg)
id_reg_pc <= if_reg_pc;
if (_id_inst_T)
@ -248,10 +286,23 @@ module Core(
id_reg_inst <= io_imem_inst;
exe_reg_pc <= id_reg_pc;
exe_reg_wb_addr <= id_inst[15:11];
exe_reg_op1_data <= id_op1_data;
if (_id_op1_data_T) begin
if (_id_rs1_data_T)
exe_reg_op1_data <= 32'h0;
else if (_id_rs1_data_T_3)
exe_reg_op1_data <= mem_wb_data;
else if (_id_rs1_data_T_6)
exe_reg_op1_data <= wb_reg_wb_data;
else
exe_reg_op1_data <= _regfile_ext_R2_data;
end
else if (_id_op1_data_T_1)
exe_reg_op1_data <= id_reg_pc;
else
exe_reg_op1_data <= 32'h0;
exe_reg_op2_data <= id_op2_data[31:0];
exe_reg_rs2_data <= id_rs2_data;
if (_csignals_T_5 | _csignals_T_7)
if (_GEN_1)
exe_reg_exe_fun <= 5'h1;
else if (_csignals_T_9)
exe_reg_exe_fun <= 5'h2;
@ -272,23 +323,22 @@ module Core(
else if (_csignals_T_25)
exe_reg_exe_fun <= 5'hC;
else
exe_reg_exe_fun <= {4'h0, _GEN_5};
exe_reg_exe_fun <= _csignals_T_31;
exe_reg_mem_wen <= 2'h0;
if (_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21) begin
if (_GEN_4) begin
exe_reg_rf_wen <= 2'h1;
exe_reg_wb_sel <= 3'h1;
end
else if (_GEN_1) begin
else if (_GEN_2) begin
exe_reg_rf_wen <= 2'h0;
exe_reg_wb_sel <= 3'h0;
end
else begin
exe_reg_rf_wen <= {1'h0, _GEN_5};
exe_reg_rf_wen <= _csignals_T_87;
if (_csignals_T_27)
exe_reg_wb_sel <= 3'h3;
else
exe_reg_wb_sel <= {2'h0, _csignals_T_29};
exe_reg_wb_sel <= _csignals_T_100;
end
exe_reg_imm_b_sext <= {{14{id_inst[15]}}, id_inst[15:0], 2'h0};
mem_reg_pc <= exe_reg_pc;