Try to rebuild the core
This commit is contained in:
242
TopOrigin.sv
242
TopOrigin.sv
@ -53,52 +53,47 @@ module Core(
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output [31:0] io_gp
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);
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wire [31:0] mem_wb_data;
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wire exe_jmp_flg;
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wire exe_br_flg;
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wire [31:0] _regfile_ext_R1_data;
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wire [31:0] _regfile_ext_R2_data;
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reg [31:0] id_reg_pc;
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reg [31:0] id_reg_inst;
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reg [31:0] exe_reg_pc;
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reg [4:0] exe_reg_wb_addr;
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reg [31:0] exe_reg_op1_data;
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reg [31:0] exe_reg_op2_data;
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reg [31:0] exe_reg_rs2_data;
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reg [4:0] exe_reg_exe_fun;
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reg [1:0] exe_reg_mem_wen;
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reg [1:0] exe_reg_rf_wen;
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reg [2:0] exe_reg_wb_sel;
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reg [31:0] exe_reg_imm_b_sext;
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reg [31:0] mem_reg_pc;
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reg [4:0] mem_reg_wb_addr;
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reg [31:0] mem_reg_rs2_data;
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reg [1:0] mem_reg_mem_wen;
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reg [1:0] mem_reg_rf_wen;
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reg [2:0] mem_reg_wb_sel;
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reg [31:0] mem_reg_alu_out;
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reg [4:0] wb_reg_wb_addr;
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reg [1:0] wb_reg_rf_wen;
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reg [31:0] wb_reg_wb_data;
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reg [31:0] if_reg_pc;
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wire _id_inst_T = exe_br_flg | exe_jmp_flg;
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wire _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1;
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wire stall_flg =
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wire [31:0] mem_wb_data;
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wire exe_jmp_flg;
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wire exe_br_flg;
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wire [31:0] _regfile_ext_R1_data;
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wire [31:0] _regfile_ext_R2_data;
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reg [31:0] id_reg_pc;
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reg [31:0] id_reg_inst;
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reg [31:0] exe_reg_pc;
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reg [4:0] exe_reg_wb_addr;
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reg [31:0] exe_reg_op1_data;
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reg [31:0] exe_reg_op2_data;
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reg [31:0] exe_reg_rs2_data;
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reg [4:0] exe_reg_exe_fun;
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reg [1:0] exe_reg_mem_wen;
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reg [1:0] exe_reg_rf_wen;
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reg [2:0] exe_reg_wb_sel;
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reg [31:0] exe_reg_imm_b_sext;
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reg [31:0] mem_reg_pc;
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reg [4:0] mem_reg_wb_addr;
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reg [31:0] mem_reg_rs2_data;
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reg [1:0] mem_reg_mem_wen;
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reg [1:0] mem_reg_rf_wen;
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reg [2:0] mem_reg_wb_sel;
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reg [31:0] mem_reg_alu_out;
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reg [4:0] wb_reg_wb_addr;
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reg [1:0] wb_reg_rf_wen;
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reg [31:0] wb_reg_wb_data;
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reg [31:0] if_reg_pc;
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wire _id_inst_T = exe_br_flg | exe_jmp_flg;
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wire _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1;
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wire stall_flg =
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_id_rs2_data_hazard_T & (|(id_reg_inst[25:21]))
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& id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T
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& (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
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wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst;
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wire _id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1;
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wire _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1;
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wire [31:0] id_rs1_data =
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id_inst[25:21] == 5'h0
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? 32'h0
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: id_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2
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? mem_wb_data
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: id_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5
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? wb_reg_wb_data
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: _regfile_ext_R2_data;
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wire [31:0] id_rs2_data =
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wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst;
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wire _id_rs1_data_T = id_inst[25:21] == 5'h0;
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wire _id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1;
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wire _id_rs1_data_T_3 = id_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2;
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wire _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1;
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wire _id_rs1_data_T_6 = id_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5;
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wire [31:0] id_rs2_data =
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id_inst[20:16] == 5'h0
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? 32'h0
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: id_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2
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@ -106,24 +101,31 @@ module Core(
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: id_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5
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? wb_reg_wb_data
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: _regfile_ext_R1_data;
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wire [16:0] _GEN = {id_inst[31:26], id_inst[10:0]};
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wire _csignals_T_5 = _GEN == 17'h20;
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wire [19:0] _GEN_0 = {id_inst[31:28], id_inst[15:0]};
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wire _csignals_T_7 = _GEN_0 == 20'h80000;
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wire _csignals_T_9 = _GEN == 17'h22;
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wire _csignals_T_11 = _GEN == 17'h24;
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wire _csignals_T_13 = _GEN == 17'h25;
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wire _csignals_T_15 = _GEN == 17'h26;
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wire _csignals_T_17 = _GEN_0 == 20'hC0000;
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wire _csignals_T_19 = _GEN_0 == 20'hD0000;
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wire _csignals_T_21 = _GEN == 17'h2A;
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wire _csignals_T_23 = _GEN_0 == 20'h40000;
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wire _csignals_T_25 = _GEN_0 == 20'h50000;
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wire _csignals_T_27 = id_inst == 32'hC000000;
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wire _csignals_T_29 = {id_inst[31:22], id_inst[9:0]} == 20'h78000;
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wire _GEN_1 = _csignals_T_23 | _csignals_T_25;
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wire _GEN_2 = _csignals_T_21 | _GEN_1;
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wire [2:0] _csignals_T_70 =
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wire [16:0] _GEN = {id_inst[31:26], id_inst[10:0]};
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wire _csignals_T_5 = _GEN == 17'h20;
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wire _csignals_T_7 = id_inst[31:28] == 4'h8;
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wire _csignals_T_9 = _GEN == 17'h22;
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wire _csignals_T_11 = _GEN == 17'h24;
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wire _csignals_T_13 = _GEN == 17'h25;
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wire _csignals_T_15 = _GEN == 17'h26;
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wire _csignals_T_17 = id_inst[31:28] == 4'hC;
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wire _csignals_T_19 = id_inst[31:28] == 4'hD;
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wire _csignals_T_21 = _GEN == 17'h2A;
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wire _csignals_T_23 = id_inst[31:28] == 4'h4;
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wire _csignals_T_25 = id_inst[31:28] == 4'h5;
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wire _csignals_T_27 = id_inst[31:28] == 4'h3;
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wire _csignals_T_29 = id_inst[31:23] == 9'h1E0;
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wire _GEN_0 = _csignals_T_27 | _csignals_T_29;
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wire [4:0] _csignals_T_31 = {4'h0, _GEN_0};
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wire _GEN_1 = _csignals_T_5 | _csignals_T_7;
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wire _GEN_2 = _csignals_T_23 | _csignals_T_25;
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wire _GEN_3 = _csignals_T_21 | _GEN_2;
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wire [1:0] csignals_1 =
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_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
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| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3
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? 2'h1
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: _csignals_T_27 ? 2'h2 : {1'h0, ~_csignals_T_29};
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wire [2:0] _csignals_T_70 =
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_csignals_T_5
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? 3'h1
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: _csignals_T_7
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@ -132,28 +134,28 @@ module Core(
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? 3'h1
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: _csignals_T_17 | _csignals_T_19
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? 3'h2
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: _GEN_2 ? 3'h1 : _csignals_T_27 ? 3'h4 : {_csignals_T_29, 2'h1};
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wire [3:0][31:0] _GEN_3 =
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{{{27'h0, id_inst[15:11]}}, {32'h0}, {id_reg_pc}, {id_rs1_data}};
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wire [31:0] id_op1_data =
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_GEN_3[_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
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| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_2
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? 2'h0
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: _csignals_T_27 ? 2'h1 : {_csignals_T_29, 1'h0}];
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wire [33:0] id_op2_data =
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: _GEN_3 ? 3'h1 : _csignals_T_27 ? 3'h4 : {_csignals_T_29, 2'h1};
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wire [1:0] _csignals_T_87 = {1'h0, _GEN_0};
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wire _GEN_4 =
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_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
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| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21;
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wire [2:0] _csignals_T_100 = {2'h0, _csignals_T_29};
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wire _id_op1_data_T = csignals_1 == 2'h1;
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wire _id_op1_data_T_1 = csignals_1 == 2'h2;
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wire [35:0] id_op2_data =
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_csignals_T_70 == 3'h1
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? {2'h0, id_rs2_data}
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? {4'h0, id_rs2_data}
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: _csignals_T_70 == 3'h2
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? {2'h0, {16{id_inst[15]}}, id_inst[15:0]}
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? {4'h0, {16{id_inst[15]}}, id_inst[15:0]}
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: _csignals_T_70 == 3'h3
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? {2'h0, {22{id_inst[15]}}, id_inst[15:11], id_inst[25:21]}
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? {4'h0, {22{id_inst[15]}}, id_inst[15:11], id_inst[25:21]}
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: _csignals_T_70 == 3'h4
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? {{6{id_inst[23]}}, id_inst[25:0], 2'h0}
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: {2'h0, _csignals_T_70 == 3'h5 ? {id_inst[15:0], 16'h0} : 32'h0};
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wire [31:0] _exe_alu_out_T_30 = exe_reg_op1_data + exe_reg_op2_data;
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wire [62:0] _exe_alu_out_T_14 = {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
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wire [31:0] _GEN_4 = {27'h0, exe_reg_op2_data[4:0]};
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wire [31:0] _exe_alu_out_T_46 =
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? {{6{id_inst[23]}}, id_inst[25:0], 4'h0}
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: {4'h0, _csignals_T_70 == 3'h5 ? {id_inst[15:0], 16'h0} : 32'h0};
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wire [31:0] _exe_alu_out_T_30 = exe_reg_op1_data + exe_reg_op2_data;
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wire [62:0] _exe_alu_out_T_14 = {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
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wire [31:0] _GEN_5 = {27'h0, exe_reg_op2_data[4:0]};
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wire [31:0] _exe_alu_out_T_46 =
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exe_reg_exe_fun == 5'h1
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? _exe_alu_out_T_30
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: exe_reg_exe_fun == 5'h2
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@ -167,9 +169,9 @@ module Core(
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: exe_reg_exe_fun == 5'h6
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? _exe_alu_out_T_14[31:0]
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: exe_reg_exe_fun == 5'h7
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? exe_reg_op1_data >> _GEN_4
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? exe_reg_op1_data >> _GEN_5
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: exe_reg_exe_fun == 5'h8
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? $signed($signed(exe_reg_op1_data) >>> _GEN_4)
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? $signed($signed(exe_reg_op1_data) >>> _GEN_5)
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: exe_reg_exe_fun == 5'h9
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? {31'h0,
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$signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)}
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@ -180,7 +182,7 @@ module Core(
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: exe_reg_exe_fun == 5'h12
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? exe_reg_op1_data
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: 32'h0;
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wire _exe_br_flg_T_3 = exe_reg_op1_data == exe_reg_op2_data;
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wire _exe_br_flg_T_3 = exe_reg_op1_data == exe_reg_op2_data;
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assign exe_br_flg =
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exe_reg_exe_fun == 5'hB
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? _exe_br_flg_T_3
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@ -193,18 +195,56 @@ module Core(
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`ifndef SYNTHESIS
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always @(posedge clock) begin
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if ((`PRINTF_COND_) & ~reset) begin
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automatic logic [31:0] id_rs1_data =
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_id_rs1_data_T
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? 32'h0
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: _id_rs1_data_T_3
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? mem_wb_data
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: _id_rs1_data_T_6 ? wb_reg_wb_data : _regfile_ext_R2_data;
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$fwrite(32'h80000002, "---------------------\n");
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$fwrite(32'h80000002, "if_reg_pc: 0x%x\n", if_reg_pc);
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$fwrite(32'h80000002, "id_reg_pc: 0x%x\n", id_reg_pc);
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$fwrite(32'h80000002, "id_reg_inst: 0x%x\n", id_reg_inst);
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$fwrite(32'h80000002, "id_inst: 0x%x\n", id_inst);
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$fwrite(32'h80000002, "id_rs1_addr: 0x%x\n", id_inst[25:21]);
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$fwrite(32'h80000002, "id_rs2_addr: 0x%x\n", id_inst[20:16]);
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$fwrite(32'h80000002, "id_wb_addr: 0x%x\n", id_inst[15:11]);
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$fwrite(32'h80000002, "id_exe_fun: 0x%x\n",
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_GEN_1
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? 5'h1
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: _csignals_T_9
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? 5'h2
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: _csignals_T_11
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? 5'h3
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: _csignals_T_13
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? 5'h4
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: _csignals_T_15
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? 5'h5
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: _csignals_T_17
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? 5'h3
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: _csignals_T_19
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? 5'h4
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: _csignals_T_21
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? 5'h9
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: _csignals_T_23
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? 5'hB
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: _csignals_T_25
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? 5'hC
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: _csignals_T_31);
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$fwrite(32'h80000002, "id_op1_sel: 0x%x\n", csignals_1);
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$fwrite(32'h80000002, "id_op1_data: 0x%x\n",
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_id_op1_data_T ? id_rs1_data : _id_op1_data_T_1 ? id_reg_pc : 32'h0);
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$fwrite(32'h80000002, "id_op2_sel: 0x%x\n", _csignals_T_70);
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$fwrite(32'h80000002, "id_op2_data: 0x%x\n", id_op2_data);
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$fwrite(32'h80000002, "id_mem_wen: 0x%x\n", 2'h0);
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$fwrite(32'h80000002, "id_rf_wen: 0x%x\n",
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_GEN_4 ? 2'h1 : _GEN_2 ? 2'h0 : _csignals_T_87);
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$fwrite(32'h80000002, "id_wb_sel: 0x%x\n",
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_GEN_4 ? 3'h1 : _GEN_2 ? 3'h0 : _csignals_T_27 ? 3'h3 : _csignals_T_100);
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$fwrite(32'h80000002, "id_rs1_data: 0x%x\n", id_rs1_data);
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$fwrite(32'h80000002, "id_rs2_data: 0x%x\n", id_rs2_data);
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$fwrite(32'h80000002, "exe_reg_pc: 0x%x\n", exe_reg_pc);
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$fwrite(32'h80000002, "exe_reg_op1_data: 0x%x\n", id_op1_data);
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$fwrite(32'h80000002, "exe_reg_op2_data: 0x%x\n", id_op2_data);
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$fwrite(32'h80000002, "exe_alu_out: 0x%x\n", _exe_alu_out_T_46);
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$fwrite(32'h80000002, "mem_reg_pc: 0x%x\n", mem_reg_pc);
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$fwrite(32'h80000002, "mem_reg_alu_out: 0x%x\n", mem_reg_alu_out);
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$fwrite(32'h80000002, "mem_wb_data: 0x%x\n", mem_wb_data);
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$fwrite(32'h80000002, "wb_reg_wb_data: 0%x\n", wb_reg_wb_data);
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$fwrite(32'h80000002, "---------------------\n");
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@ -238,8 +278,6 @@ module Core(
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if_reg_pc <= 32'h400000;
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end
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else begin
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automatic logic _GEN_5;
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_GEN_5 = _csignals_T_27 | _csignals_T_29;
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if (~stall_flg)
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id_reg_pc <= if_reg_pc;
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if (_id_inst_T)
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@ -248,10 +286,23 @@ module Core(
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id_reg_inst <= io_imem_inst;
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exe_reg_pc <= id_reg_pc;
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exe_reg_wb_addr <= id_inst[15:11];
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exe_reg_op1_data <= id_op1_data;
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if (_id_op1_data_T) begin
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if (_id_rs1_data_T)
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exe_reg_op1_data <= 32'h0;
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else if (_id_rs1_data_T_3)
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exe_reg_op1_data <= mem_wb_data;
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else if (_id_rs1_data_T_6)
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exe_reg_op1_data <= wb_reg_wb_data;
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else
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exe_reg_op1_data <= _regfile_ext_R2_data;
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end
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||||
else if (_id_op1_data_T_1)
|
||||
exe_reg_op1_data <= id_reg_pc;
|
||||
else
|
||||
exe_reg_op1_data <= 32'h0;
|
||||
exe_reg_op2_data <= id_op2_data[31:0];
|
||||
exe_reg_rs2_data <= id_rs2_data;
|
||||
if (_csignals_T_5 | _csignals_T_7)
|
||||
if (_GEN_1)
|
||||
exe_reg_exe_fun <= 5'h1;
|
||||
else if (_csignals_T_9)
|
||||
exe_reg_exe_fun <= 5'h2;
|
||||
@ -272,23 +323,22 @@ module Core(
|
||||
else if (_csignals_T_25)
|
||||
exe_reg_exe_fun <= 5'hC;
|
||||
else
|
||||
exe_reg_exe_fun <= {4'h0, _GEN_5};
|
||||
exe_reg_exe_fun <= _csignals_T_31;
|
||||
exe_reg_mem_wen <= 2'h0;
|
||||
if (_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
|
||||
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21) begin
|
||||
if (_GEN_4) begin
|
||||
exe_reg_rf_wen <= 2'h1;
|
||||
exe_reg_wb_sel <= 3'h1;
|
||||
end
|
||||
else if (_GEN_1) begin
|
||||
else if (_GEN_2) begin
|
||||
exe_reg_rf_wen <= 2'h0;
|
||||
exe_reg_wb_sel <= 3'h0;
|
||||
end
|
||||
else begin
|
||||
exe_reg_rf_wen <= {1'h0, _GEN_5};
|
||||
exe_reg_rf_wen <= _csignals_T_87;
|
||||
if (_csignals_T_27)
|
||||
exe_reg_wb_sel <= 3'h3;
|
||||
else
|
||||
exe_reg_wb_sel <= {2'h0, _csignals_T_29};
|
||||
exe_reg_wb_sel <= _csignals_T_100;
|
||||
end
|
||||
exe_reg_imm_b_sext <= {{14{id_inst[15]}}, id_inst[15:0], 2'h0};
|
||||
mem_reg_pc <= exe_reg_pc;
|
||||
|
||||
@ -1,8 +0,0 @@
|
||||
// format: off
|
||||
// DO NOT EDIT! This file is auto-generated.
|
||||
|
||||
// This file enables sbt-bloop to create bloop config files.
|
||||
|
||||
addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "2.0.6")
|
||||
|
||||
// format: on
|
||||
@ -1,8 +0,0 @@
|
||||
// format: off
|
||||
// DO NOT EDIT! This file is auto-generated.
|
||||
|
||||
// This file enables sbt-bloop to create bloop config files.
|
||||
|
||||
addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "2.0.6")
|
||||
|
||||
// format: on
|
||||
@ -1 +0,0 @@
|
||||
[[{},{}],{}]
|
||||
@ -1 +0,0 @@
|
||||
-1633561639
|
||||
File diff suppressed because one or more lines are too long
@ -1 +0,0 @@
|
||||
644413116
|
||||
@ -1 +0,0 @@
|
||||
{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}
|
||||
@ -1,8 +0,0 @@
|
||||
[0m[[0m[33mwarn[0m] [0m[0msbt-bloop_2.12_1.0-2.0.6.jar no longer exists at /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mnot up to date. inChanged = false, force = false[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mUpdating ProjectRef(uri("file:/home/gh0s7/nfs/project/micore/project/project/project/"), "micore-build-build-build")...[0m
|
||||
[0m[[0m[0minfo[0m] [0m[0mUpdating [0m
|
||||
[0m[[0m[0minfo[0m] [0m[0mResolved dependencies[0m
|
||||
[0m[[0m[0minfo[0m] [0m[0mFetching artifacts of [0m
|
||||
[0m[[0m[0minfo[0m] [0m[0mFetched artifacts of [0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mDone updating ProjectRef(uri("file:/home/gh0s7/nfs/project/micore/project/project/project/"), "micore-build-build-build")[0m
|
||||
@ -1 +0,0 @@
|
||||
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]
|
||||
@ -1 +0,0 @@
|
||||
[]
|
||||
@ -1,6 +0,0 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0m[zinc] IncrementalCompile -----------[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mIncrementalCompile.incrementalCompile[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mprevious = Stamps for: 0 products, 0 sources, 0 libraries[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mcurrent source = Set()[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m> initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set())[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mFull compilation, no sources in previous analysis.[0m
|
||||
@ -1,2 +0,0 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0mCopy resource mappings: [0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m [0m
|
||||
File diff suppressed because one or more lines are too long
@ -1 +0,0 @@
|
||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
|
||||
File diff suppressed because one or more lines are too long
@ -1,5 +0,0 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mAbout to delete class files:[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mWe backup class files:[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mRemoving the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
@ -1 +0,0 @@
|
||||
|
||||
File diff suppressed because one or more lines are too long
@ -1 +0,0 @@
|
||||
|
||||
@ -1 +0,0 @@
|
||||
|
||||
File diff suppressed because one or more lines are too long
@ -1 +0,0 @@
|
||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@ -1 +0,0 @@
|
||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
|
||||
File diff suppressed because one or more lines are too long
@ -1 +0,0 @@
|
||||
|
||||
@ -1 +0,0 @@
|
||||
|
||||
@ -1 +0,0 @@
|
||||
[[{},{}],{}]
|
||||
@ -1 +0,0 @@
|
||||
-756073079
|
||||
File diff suppressed because one or more lines are too long
@ -1 +0,0 @@
|
||||
644413116
|
||||
@ -1 +0,0 @@
|
||||
{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}
|
||||
@ -1,3 +0,0 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0mnot up to date. inChanged = true, force = false[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mUpdating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/project/"), "micore-build-build")...[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mDone updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/project/"), "micore-build-build")[0m
|
||||
@ -1,6 +0,0 @@
|
||||
[0m[[0m[33mwarn[0m] [0m[0msbt-bloop_2.12_1.0-2.0.6-sources.jar no longer exists at /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6-sources.jar[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mnot up to date. inChanged = false, force = false[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mUpdating ProjectRef(uri("file:/home/gh0s7/nfs/project/micore/project/project/"), "micore-build-build")...[0m
|
||||
[0m[[0m[0minfo[0m] [0m[0mFetching artifacts of [0m
|
||||
[0m[[0m[0minfo[0m] [0m[0mFetched artifacts of [0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mDone updating ProjectRef(uri("file:/home/gh0s7/nfs/project/micore/project/project/"), "micore-build-build")[0m
|
||||
@ -1 +0,0 @@
|
||||
1606726032
|
||||
File diff suppressed because one or more lines are too long
@ -1,2 +0,0 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0mOther repositories:[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mDefault repositories:[0m
|
||||
@ -1 +0,0 @@
|
||||
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]
|
||||
@ -1 +0,0 @@
|
||||
[]
|
||||
@ -1,4 +0,0 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0m[micore-build-build] Classpath dependencies List()[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m[micore-build-build] Dependencies from configurations List()[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mBloop wrote the configuration of project 'micore-build-build' to '/run/media/gh0s7/Data/project/ddca2024/micore/project/project/.bloop/micore-build-build.json'[0m
|
||||
[0m[[0m[32msuccess[0m] [0m[0mGenerated .bloop/micore-build-build.json[0m
|
||||
@ -1 +0,0 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0mRunning postGenerate for micore-build-build[0m
|
||||
@ -1,6 +0,0 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0m[zinc] IncrementalCompile -----------[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mIncrementalCompile.incrementalCompile[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mprevious = Stamps for: 0 products, 0 sources, 0 libraries[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mcurrent source = Set()[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m> initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set())[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mFull compilation, no sources in previous analysis.[0m
|
||||
@ -1,2 +0,0 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0mCopy resource mappings: [0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m [0m
|
||||
File diff suppressed because one or more lines are too long
@ -1 +0,0 @@
|
||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes
|
||||
File diff suppressed because one or more lines are too long
@ -1,5 +0,0 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mAbout to delete class files:[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mWe backup class files:[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mRemoving the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
@ -1 +0,0 @@
|
||||
|
||||
File diff suppressed because one or more lines are too long
@ -1 +0,0 @@
|
||||
|
||||
@ -1 +0,0 @@
|
||||
|
||||
@ -1 +0,0 @@
|
||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
|
||||
@ -1 +0,0 @@
|
||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes
|
||||
@ -1 +0,0 @@
|
||||
/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
|
||||
@ -1 +0,0 @@
|
||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
|
||||
@ -1 +0,0 @@
|
||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes
|
||||
@ -1 +0,0 @@
|
||||
/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
|
||||
@ -1 +0,0 @@
|
||||
|
||||
@ -1 +0,0 @@
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user