Compare commits
2 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
| b4e64b8f52 | |||
| 106519d1ab |
2
.gitignore
vendored
2
.gitignore
vendored
@ -8,6 +8,8 @@
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*.code-workspace
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*.code-workspace
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target/*
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target/*
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.vscode
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.vscode
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test_run_dir
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target
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# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
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# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
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hs_err_pid*
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hs_err_pid*
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2
Core.sv
2
Core.sv
@ -31,7 +31,7 @@ module Core(
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output [3:0] io_anodes,
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output [3:0] io_anodes,
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output [6:0] io_segments,
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output [6:0] io_segments,
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output io_exit
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output io_exit
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);
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);
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wire exe_jmp_flg;
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wire exe_jmp_flg;
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wire exe_br_flg;
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wire exe_br_flg;
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171
Memory.sv
171
Memory.sv
@ -18,83 +18,8 @@
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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module mem_4096x8(
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input [11:0] R0_addr,
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input R0_en,
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R0_clk,
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output [7:0] R0_data,
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input [11:0] R1_addr,
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input R1_en,
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R1_clk,
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output [7:0] R1_data,
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input [11:0] R2_addr,
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input R2_en,
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R2_clk,
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output [7:0] R2_data,
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input [11:0] R3_addr,
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input R3_en,
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R3_clk,
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output [7:0] R3_data,
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input [11:0] R4_addr,
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input R4_en,
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R4_clk,
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output [7:0] R4_data,
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input [11:0] R5_addr,
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input R5_en,
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R5_clk,
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output [7:0] R5_data,
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input [11:0] R6_addr,
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input R6_en,
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R6_clk,
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output [7:0] R6_data,
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input [11:0] R7_addr,
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input R7_en,
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R7_clk,
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output [7:0] R7_data,
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input [11:0] W0_addr,
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input W0_en,
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W0_clk,
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input [7:0] W0_data,
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input [11:0] W1_addr,
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input W1_en,
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W1_clk,
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input [7:0] W1_data,
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input [11:0] W2_addr,
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input W2_en,
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W2_clk,
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input [7:0] W2_data,
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input [11:0] W3_addr,
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input W3_en,
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W3_clk,
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input [7:0] W3_data
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);
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reg [7:0] Memory[0:4095];
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always @(posedge W0_clk) begin
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if (W0_en & 1'h1)
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Memory[W0_addr] <= W0_data;
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if (W1_en & 1'h1)
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Memory[W1_addr] <= W1_data;
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if (W2_en & 1'h1)
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Memory[W2_addr] <= W2_data;
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if (W3_en & 1'h1)
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Memory[W3_addr] <= W3_data;
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end // always @(posedge)
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`ifdef ENABLE_INITIAL_MEM_
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initial
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$readmemh("src/hex/mem.hex", Memory);
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`endif // ENABLE_INITIAL_MEM_
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assign R0_data = R0_en ? Memory[R0_addr] : 8'bx;
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assign R1_data = R1_en ? Memory[R1_addr] : 8'bx;
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assign R2_data = R2_en ? Memory[R2_addr] : 8'bx;
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assign R3_data = R3_en ? Memory[R3_addr] : 8'bx;
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assign R4_data = R4_en ? Memory[R4_addr] : 8'bx;
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assign R5_data = R5_en ? Memory[R5_addr] : 8'bx;
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assign R6_data = R6_en ? Memory[R6_addr] : 8'bx;
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assign R7_data = R7_en ? Memory[R7_addr] : 8'bx;
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endmodule
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// VCS coverage exclude_file
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module Memory(
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module Memory(
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input clock,
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input clock,
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input [31:0] io_imem_addr,
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input [31:0] io_imem_addr,
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@ -103,71 +28,33 @@ module Memory(
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output [31:0] io_dmem_rdata,
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output [31:0] io_dmem_rdata,
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input io_dmem_wen,
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input io_dmem_wen,
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input [31:0] io_dmem_wdata
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input [31:0] io_dmem_wdata
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);
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);
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wire [7:0] _mem_ext_R0_data;
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wire [7:0] _mem_ext_R1_data;
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reg [31:0] mem [0:63];
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wire [7:0] _mem_ext_R2_data;
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wire [7:0] _mem_ext_R3_data;
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wire [7:0] _mem_ext_R4_data;
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initial begin
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wire [7:0] _mem_ext_R5_data;
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mem[0] = 32'h20080001; // addi $t0, $zero, 1
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wire [7:0] _mem_ext_R6_data;
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mem[1] = 32'h20100000; // addi $s0, $zero, 0
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wire [7:0] _mem_ext_R7_data;
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mem[2] = 32'h20120065; // addi $s2, $zero, 101
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wire [11:0] _io_dmem_rdata_T = io_dmem_addr[11:0] + 12'h3;
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mem[3] = 32'h02088020; // add $s0, $s0, $t0
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wire [11:0] _io_dmem_rdata_T_3 = io_dmem_addr[11:0] + 12'h2;
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mem[4] = 32'h21080001; // addi $t0, $t0, 1
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wire [11:0] _io_dmem_rdata_T_6 = io_dmem_addr[11:0] + 12'h1;
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mem[5] = 32'h0112502a; // slt $t2, $t0, $s2
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mem_4096x8 mem_ext (
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mem[6] = 32'h1540fffc; // bne $t2, $zero, -4
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.R0_addr (io_imem_addr[11:0]),
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mem[7] = 32'h00000000; // nop
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.R0_en (1'h1),
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mem[8] = 32'h00114514; // exit
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.R0_clk (clock),
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end
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.R0_data (_mem_ext_R0_data),
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.R1_addr (io_imem_addr[11:0] + 12'h1),
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.R1_en (1'h1),
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assign io_imem_inst = mem[io_imem_addr[7:2]];
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.R1_clk (clock),
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.R1_data (_mem_ext_R1_data),
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assign io_dmem_rdata = mem[io_dmem_addr[7:2]];
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.R2_addr (io_imem_addr[11:0] + 12'h2),
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.R2_en (1'h1),
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.R2_clk (clock),
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always @(posedge clock) begin
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.R2_data (_mem_ext_R2_data),
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if (io_dmem_wen) begin
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.R3_addr (io_imem_addr[11:0] + 12'h3),
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mem[io_dmem_addr[7:2]] <= io_dmem_wdata;
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.R3_en (1'h1),
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end
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.R3_clk (clock),
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end
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.R3_data (_mem_ext_R3_data),
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.R4_addr (io_dmem_addr[11:0]),
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.R4_en (1'h1),
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.R4_clk (clock),
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.R4_data (_mem_ext_R4_data),
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.R5_addr (_io_dmem_rdata_T_6),
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.R5_en (1'h1),
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.R5_clk (clock),
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.R5_data (_mem_ext_R5_data),
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.R6_addr (_io_dmem_rdata_T_3),
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.R6_en (1'h1),
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.R6_clk (clock),
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.R6_data (_mem_ext_R6_data),
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.R7_addr (_io_dmem_rdata_T),
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.R7_en (1'h1),
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.R7_clk (clock),
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.R7_data (_mem_ext_R7_data),
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.W0_addr (_io_dmem_rdata_T),
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.W0_en (io_dmem_wen),
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.W0_clk (clock),
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.W0_data (io_dmem_wdata[31:24]),
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.W1_addr (_io_dmem_rdata_T_3),
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.W1_en (io_dmem_wen),
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.W1_clk (clock),
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.W1_data (io_dmem_wdata[23:16]),
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.W2_addr (_io_dmem_rdata_T_6),
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.W2_en (io_dmem_wen),
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.W2_clk (clock),
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.W2_data (io_dmem_wdata[15:8]),
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.W3_addr (io_dmem_addr[11:0]),
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.W3_en (io_dmem_wen),
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.W3_clk (clock),
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.W3_data (io_dmem_wdata[7:0])
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);
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assign io_imem_inst =
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{_mem_ext_R3_data, _mem_ext_R2_data, _mem_ext_R1_data, _mem_ext_R0_data};
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assign io_dmem_rdata =
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{_mem_ext_R7_data, _mem_ext_R6_data, _mem_ext_R5_data, _mem_ext_R4_data};
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endmodule
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endmodule
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@ -18,6 +18,7 @@
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// Additional Comments:
|
// Additional Comments:
|
||||||
//
|
//
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||||||
//////////////////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////////////////
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module regfile_32x32(
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module regfile_32x32(
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input [4:0] R0_addr,
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input [4:0] R0_addr,
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input R0_en,
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input R0_en,
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@ -33,7 +34,7 @@ module regfile_32x32(
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output [3:0] io_anodes,
|
output [3:0] io_anodes,
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output [6:0] io_segments,
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output [6:0] io_segments,
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input [31:0] W0_data
|
input [31:0] W0_data
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);
|
);
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reg [31:0] Memory[0:31];
|
reg [31:0] Memory[0:31];
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always @(posedge W0_clk) begin
|
always @(posedge W0_clk) begin
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@ -51,4 +52,3 @@ module regfile_32x32(
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.io_segments (io_segments)
|
.io_segments (io_segments)
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);
|
);
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endmodule
|
endmodule
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|
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6
Top.sv
6
Top.sv
@ -22,10 +22,10 @@
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module Top(
|
module Top(
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input clock,
|
input clock,
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reset,
|
reset,
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output io_exit,
|
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output [3:0] io_anodes,
|
output [3:0] io_anodes,
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output [6:0] io_segments
|
output [6:0] io_segments,
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||||||
);
|
output io_exit
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||||||
|
);
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|
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wire [31:0] _memory_io_imem_inst;
|
wire [31:0] _memory_io_imem_inst;
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wire [31:0] _memory_io_dmem_rdata;
|
wire [31:0] _memory_io_dmem_rdata;
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135
TopOrigin.sv
135
TopOrigin.sv
@ -428,80 +428,32 @@ module Core(
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endmodule
|
endmodule
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|
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// VCS coverage exclude_file
|
// VCS coverage exclude_file
|
||||||
module mem_4096x8(
|
module mem_64x32(
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input [11:0] R0_addr,
|
input [5:0] R0_addr,
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input R0_en,
|
input R0_en,
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R0_clk,
|
R0_clk,
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output [7:0] R0_data,
|
output [31:0] R0_data,
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input [11:0] R1_addr,
|
input [5:0] R1_addr,
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input R1_en,
|
input R1_en,
|
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R1_clk,
|
R1_clk,
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output [7:0] R1_data,
|
output [31:0] R1_data,
|
||||||
input [11:0] R2_addr,
|
input [5:0] W0_addr,
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input R2_en,
|
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R2_clk,
|
|
||||||
output [7:0] R2_data,
|
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input [11:0] R3_addr,
|
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input R3_en,
|
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R3_clk,
|
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output [7:0] R3_data,
|
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||||||
input [11:0] R4_addr,
|
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input R4_en,
|
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R4_clk,
|
|
||||||
output [7:0] R4_data,
|
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||||||
input [11:0] R5_addr,
|
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input R5_en,
|
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R5_clk,
|
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||||||
output [7:0] R5_data,
|
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||||||
input [11:0] R6_addr,
|
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input R6_en,
|
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R6_clk,
|
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||||||
output [7:0] R6_data,
|
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||||||
input [11:0] R7_addr,
|
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||||||
input R7_en,
|
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R7_clk,
|
|
||||||
output [7:0] R7_data,
|
|
||||||
input [11:0] W0_addr,
|
|
||||||
input W0_en,
|
input W0_en,
|
||||||
W0_clk,
|
W0_clk,
|
||||||
input [7:0] W0_data,
|
input [31:0] W0_data
|
||||||
input [11:0] W1_addr,
|
|
||||||
input W1_en,
|
|
||||||
W1_clk,
|
|
||||||
input [7:0] W1_data,
|
|
||||||
input [11:0] W2_addr,
|
|
||||||
input W2_en,
|
|
||||||
W2_clk,
|
|
||||||
input [7:0] W2_data,
|
|
||||||
input [11:0] W3_addr,
|
|
||||||
input W3_en,
|
|
||||||
W3_clk,
|
|
||||||
input [7:0] W3_data
|
|
||||||
);
|
);
|
||||||
|
|
||||||
reg [7:0] Memory[0:4095];
|
reg [31:0] Memory[0:63];
|
||||||
always @(posedge W0_clk) begin
|
always @(posedge W0_clk) begin
|
||||||
if (W0_en & 1'h1)
|
if (W0_en & 1'h1)
|
||||||
Memory[W0_addr] <= W0_data;
|
Memory[W0_addr] <= W0_data;
|
||||||
if (W1_en & 1'h1)
|
|
||||||
Memory[W1_addr] <= W1_data;
|
|
||||||
if (W2_en & 1'h1)
|
|
||||||
Memory[W2_addr] <= W2_data;
|
|
||||||
if (W3_en & 1'h1)
|
|
||||||
Memory[W3_addr] <= W3_data;
|
|
||||||
end // always @(posedge)
|
end // always @(posedge)
|
||||||
`ifdef ENABLE_INITIAL_MEM_
|
`ifdef ENABLE_INITIAL_MEM_
|
||||||
initial
|
initial
|
||||||
$readmemh("src/hex/mem.hex", Memory);
|
$readmemh("src/hex/mem.dat", Memory);
|
||||||
`endif // ENABLE_INITIAL_MEM_
|
`endif // ENABLE_INITIAL_MEM_
|
||||||
assign R0_data = R0_en ? Memory[R0_addr] : 8'bx;
|
assign R0_data = R0_en ? Memory[R0_addr] : 32'bx;
|
||||||
assign R1_data = R1_en ? Memory[R1_addr] : 8'bx;
|
assign R1_data = R1_en ? Memory[R1_addr] : 32'bx;
|
||||||
assign R2_data = R2_en ? Memory[R2_addr] : 8'bx;
|
|
||||||
assign R3_data = R3_en ? Memory[R3_addr] : 8'bx;
|
|
||||||
assign R4_data = R4_en ? Memory[R4_addr] : 8'bx;
|
|
||||||
assign R5_data = R5_en ? Memory[R5_addr] : 8'bx;
|
|
||||||
assign R6_data = R6_en ? Memory[R6_addr] : 8'bx;
|
|
||||||
assign R7_data = R7_en ? Memory[R7_addr] : 8'bx;
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
module Memory(
|
module Memory(
|
||||||
@ -514,71 +466,20 @@ module Memory(
|
|||||||
input [31:0] io_dmem_wdata
|
input [31:0] io_dmem_wdata
|
||||||
);
|
);
|
||||||
|
|
||||||
wire [7:0] _mem_ext_R0_data;
|
mem_64x32 mem_ext (
|
||||||
wire [7:0] _mem_ext_R1_data;
|
.R0_addr (io_imem_addr[7:2]),
|
||||||
wire [7:0] _mem_ext_R2_data;
|
|
||||||
wire [7:0] _mem_ext_R3_data;
|
|
||||||
wire [7:0] _mem_ext_R4_data;
|
|
||||||
wire [7:0] _mem_ext_R5_data;
|
|
||||||
wire [7:0] _mem_ext_R6_data;
|
|
||||||
wire [7:0] _mem_ext_R7_data;
|
|
||||||
wire [11:0] _io_dmem_rdata_T = io_dmem_addr[11:0] + 12'h3;
|
|
||||||
wire [11:0] _io_dmem_rdata_T_3 = io_dmem_addr[11:0] + 12'h2;
|
|
||||||
wire [11:0] _io_dmem_rdata_T_6 = io_dmem_addr[11:0] + 12'h1;
|
|
||||||
mem_4096x8 mem_ext (
|
|
||||||
.R0_addr (io_imem_addr[11:0]),
|
|
||||||
.R0_en (1'h1),
|
.R0_en (1'h1),
|
||||||
.R0_clk (clock),
|
.R0_clk (clock),
|
||||||
.R0_data (_mem_ext_R0_data),
|
.R0_data (io_imem_inst),
|
||||||
.R1_addr (io_imem_addr[11:0] + 12'h1),
|
.R1_addr (io_dmem_addr[7:2]),
|
||||||
.R1_en (1'h1),
|
.R1_en (1'h1),
|
||||||
.R1_clk (clock),
|
.R1_clk (clock),
|
||||||
.R1_data (_mem_ext_R1_data),
|
.R1_data (io_dmem_rdata),
|
||||||
.R2_addr (io_imem_addr[11:0] + 12'h2),
|
.W0_addr (io_dmem_addr[7:2]),
|
||||||
.R2_en (1'h1),
|
|
||||||
.R2_clk (clock),
|
|
||||||
.R2_data (_mem_ext_R2_data),
|
|
||||||
.R3_addr (io_imem_addr[11:0] + 12'h3),
|
|
||||||
.R3_en (1'h1),
|
|
||||||
.R3_clk (clock),
|
|
||||||
.R3_data (_mem_ext_R3_data),
|
|
||||||
.R4_addr (io_dmem_addr[11:0]),
|
|
||||||
.R4_en (1'h1),
|
|
||||||
.R4_clk (clock),
|
|
||||||
.R4_data (_mem_ext_R4_data),
|
|
||||||
.R5_addr (_io_dmem_rdata_T_6),
|
|
||||||
.R5_en (1'h1),
|
|
||||||
.R5_clk (clock),
|
|
||||||
.R5_data (_mem_ext_R5_data),
|
|
||||||
.R6_addr (_io_dmem_rdata_T_3),
|
|
||||||
.R6_en (1'h1),
|
|
||||||
.R6_clk (clock),
|
|
||||||
.R6_data (_mem_ext_R6_data),
|
|
||||||
.R7_addr (_io_dmem_rdata_T),
|
|
||||||
.R7_en (1'h1),
|
|
||||||
.R7_clk (clock),
|
|
||||||
.R7_data (_mem_ext_R7_data),
|
|
||||||
.W0_addr (_io_dmem_rdata_T),
|
|
||||||
.W0_en (io_dmem_wen),
|
.W0_en (io_dmem_wen),
|
||||||
.W0_clk (clock),
|
.W0_clk (clock),
|
||||||
.W0_data (io_dmem_wdata[31:24]),
|
.W0_data (io_dmem_wdata)
|
||||||
.W1_addr (_io_dmem_rdata_T_3),
|
|
||||||
.W1_en (io_dmem_wen),
|
|
||||||
.W1_clk (clock),
|
|
||||||
.W1_data (io_dmem_wdata[23:16]),
|
|
||||||
.W2_addr (_io_dmem_rdata_T_6),
|
|
||||||
.W2_en (io_dmem_wen),
|
|
||||||
.W2_clk (clock),
|
|
||||||
.W2_data (io_dmem_wdata[15:8]),
|
|
||||||
.W3_addr (io_dmem_addr[11:0]),
|
|
||||||
.W3_en (io_dmem_wen),
|
|
||||||
.W3_clk (clock),
|
|
||||||
.W3_data (io_dmem_wdata[7:0])
|
|
||||||
);
|
);
|
||||||
assign io_imem_inst =
|
|
||||||
{_mem_ext_R3_data, _mem_ext_R2_data, _mem_ext_R1_data, _mem_ext_R0_data};
|
|
||||||
assign io_dmem_rdata =
|
|
||||||
{_mem_ext_R7_data, _mem_ext_R6_data, _mem_ext_R5_data, _mem_ext_R4_data};
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
module TopOrigin(
|
module TopOrigin(
|
||||||
|
|||||||
@ -1,8 +0,0 @@
|
|||||||
// format: off
|
|
||||||
// DO NOT EDIT! This file is auto-generated.
|
|
||||||
|
|
||||||
// This file enables sbt-bloop to create bloop config files.
|
|
||||||
|
|
||||||
addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "2.0.6")
|
|
||||||
|
|
||||||
// format: on
|
|
||||||
@ -1,8 +0,0 @@
|
|||||||
// format: off
|
|
||||||
// DO NOT EDIT! This file is auto-generated.
|
|
||||||
|
|
||||||
// This file enables sbt-bloop to create bloop config files.
|
|
||||||
|
|
||||||
addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "2.0.6")
|
|
||||||
|
|
||||||
// format: on
|
|
||||||
@ -1 +0,0 @@
|
|||||||
sbt.internal.DslEntry
|
|
||||||
@ -1 +0,0 @@
|
|||||||
sbt.internal.DslEntry
|
|
||||||
@ -1 +0,0 @@
|
|||||||
[[{},{}],{}]
|
|
||||||
@ -1 +0,0 @@
|
|||||||
-1633561639
|
|
||||||
File diff suppressed because one or more lines are too long
@ -1 +0,0 @@
|
|||||||
644413116
|
|
||||||
@ -1 +0,0 @@
|
|||||||
{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}
|
|
||||||
@ -1,3 +0,0 @@
|
|||||||
[0m[[0m[0mdebug[0m] [0m[0mnot up to date. inChanged = true, force = false[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mUpdating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/"), "micore-build-build-build")...[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mDone updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/"), "micore-build-build-build")[0m
|
|
||||||
@ -1 +0,0 @@
|
|||||||
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]
|
|
||||||
@ -1 +0,0 @@
|
|||||||
[]
|
|
||||||
@ -1,6 +0,0 @@
|
|||||||
[0m[[0m[0mdebug[0m] [0m[0m[zinc] IncrementalCompile -----------[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mIncrementalCompile.incrementalCompile[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mprevious = Stamps for: 0 products, 0 sources, 0 libraries[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mcurrent source = Set()[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0m> initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set())[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mFull compilation, no sources in previous analysis.[0m
|
|
||||||
@ -1,2 +0,0 @@
|
|||||||
[0m[[0m[0mdebug[0m] [0m[0mCopy resource mappings: [0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0m [0m
|
|
||||||
File diff suppressed because one or more lines are too long
@ -1 +0,0 @@
|
|||||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
|
|
||||||
File diff suppressed because one or more lines are too long
@ -1,5 +0,0 @@
|
|||||||
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mAbout to delete class files:[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mWe backup class files:[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mRemoving the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
|
||||||
@ -1 +0,0 @@
|
|||||||
|
|
||||||
File diff suppressed because one or more lines are too long
@ -1 +0,0 @@
|
|||||||
|
|
||||||
@ -1 +0,0 @@
|
|||||||
|
|
||||||
File diff suppressed because one or more lines are too long
@ -1 +0,0 @@
|
|||||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
|
|
||||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@ -1 +0,0 @@
|
|||||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
|
|
||||||
File diff suppressed because one or more lines are too long
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|
|||||||
|
|
||||||
@ -1 +0,0 @@
|
|||||||
|
|
||||||
@ -1 +0,0 @@
|
|||||||
sbt.internal.DslEntry
|
|
||||||
@ -1 +0,0 @@
|
|||||||
sbt.internal.DslEntry
|
|
||||||
@ -1 +0,0 @@
|
|||||||
[[{},{}],{}]
|
|
||||||
@ -1 +0,0 @@
|
|||||||
-756073079
|
|
||||||
File diff suppressed because one or more lines are too long
@ -1 +0,0 @@
|
|||||||
644413116
|
|
||||||
@ -1 +0,0 @@
|
|||||||
{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}
|
|
||||||
@ -1,3 +0,0 @@
|
|||||||
[0m[[0m[0mdebug[0m] [0m[0mnot up to date. inChanged = true, force = false[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mUpdating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build")...[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mDone updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build")[0m
|
|
||||||
@ -1,3 +0,0 @@
|
|||||||
[0m[[0m[0mdebug[0m] [0m[0mnot up to date. inChanged = true, force = false[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mUpdating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build")...[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mDone updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build")[0m
|
|
||||||
@ -1 +0,0 @@
|
|||||||
1606726032
|
|
||||||
File diff suppressed because one or more lines are too long
@ -1,2 +0,0 @@
|
|||||||
[0m[[0m[0mdebug[0m] [0m[0mOther repositories:[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mDefault repositories:[0m
|
|
||||||
@ -1 +0,0 @@
|
|||||||
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]
|
|
||||||
@ -1 +0,0 @@
|
|||||||
[]
|
|
||||||
@ -1,4 +0,0 @@
|
|||||||
[0m[[0m[0mdebug[0m] [0m[0m[micore-build-build] Classpath dependencies List()[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0m[micore-build-build] Dependencies from configurations List()[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mBloop wrote the configuration of project 'micore-build-build' to '/run/media/gh0s7/Data/project/ddca2024/micore/project/project/.bloop/micore-build-build.json'[0m
|
|
||||||
[0m[[0m[32msuccess[0m] [0m[0mGenerated .bloop/micore-build-build.json[0m
|
|
||||||
@ -1 +0,0 @@
|
|||||||
[0m[[0m[0mdebug[0m] [0m[0mRunning postGenerate for micore-build-build[0m
|
|
||||||
@ -1,6 +0,0 @@
|
|||||||
[0m[[0m[0mdebug[0m] [0m[0m[zinc] IncrementalCompile -----------[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mIncrementalCompile.incrementalCompile[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mprevious = Stamps for: 0 products, 0 sources, 0 libraries[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mcurrent source = Set()[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0m> initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set())[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mFull compilation, no sources in previous analysis.[0m
|
|
||||||
@ -1,2 +0,0 @@
|
|||||||
[0m[[0m[0mdebug[0m] [0m[0mCopy resource mappings: [0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0m [0m
|
|
||||||
File diff suppressed because one or more lines are too long
@ -1 +0,0 @@
|
|||||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes
|
|
||||||
File diff suppressed because one or more lines are too long
@ -1,5 +0,0 @@
|
|||||||
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mAbout to delete class files:[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mWe backup class files:[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mRemoving the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
|
||||||
@ -1 +0,0 @@
|
|||||||
|
|
||||||
File diff suppressed because one or more lines are too long
@ -1 +0,0 @@
|
|||||||
|
|
||||||
@ -1 +0,0 @@
|
|||||||
|
|
||||||
@ -1 +0,0 @@
|
|||||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
|
|
||||||
@ -1 +0,0 @@
|
|||||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes
|
|
||||||
@ -1 +0,0 @@
|
|||||||
/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
|
|
||||||
@ -1 +0,0 @@
|
|||||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
|
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@ -1 +0,0 @@
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/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes
|
|
||||||
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