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• b4e64b8f52 Code Optimization and Clean Up main CGH0S7 2025-01-02 17:12:14 +08:00
• 106519d1ab Case closed CGH0S7 2025-01-02 17:11:45 +08:00
• 7ae5ee8c39 SystemVerilog Module Complete devel CGH0S7 2025-01-01 23:19:43 +08:00
• 99703db0db Quest Completed! CGH0S7 2025-01-01 23:17:04 +08:00
• c198fcab4f Micore need to be fixed CGH0S7 2024-12-31 11:23:29 +08:00
• c5eba63085 Fix bugs in Sicore CGH0S7 2024-12-31 09:28:33 +08:00
• b4cb98d8a9 Add single cycle edition CGH0S7 2024-12-31 01:30:15 +08:00
• de44f7d8d3 Try to rebuild the core CGH0S7 2024-12-30 20:09:10 +08:00
• e8e6b6ddb3 Still need to fix CGH0S7 2024-12-30 00:36:45 +08:00
• 582917df99 Some bugs need to be fixed. CGH0S7 2024-12-29 16:20:43 +08:00
• 320f71ac96 Add constraint file and display module CGH0S7 2024-12-28 09:05:23 +08:00
• 66cda81233 Core Opimized CGH0S7 2024-12-28 08:39:07 +08:00
• 7d9846b4a6 Chisel code optimized CGH0S7 2024-12-27 23:35:23 +08:00
• ec0fd8812f Add mem.hex and Fix some bugs CGH0S7 2024-12-27 13:53:58 +08:00
• 7f695e27ac 2024/12/27 Update CGH0S7 2024-12-27 13:43:40 +08:00
• 0c82f4c879 Core.scala Update CGH0S7 2024-12-27 10:30:43 +08:00
• 3c98a8b4c3 Core.scala Update CGH0S7 2024-12-25 11:30:51 +08:00
• d89af6acd5 .gitignore Updated CGH0S7 2024-12-25 09:33:55 +08:00
• 5d8f47c069 完成常量和顶层模块编写 CGH0S7 2024-12-25 08:42:07 +08:00
• f6f4585f78 Remove previously committed dotfiles CGH0S7 2024-12-23 10:18:41 +08:00
• c3d321144f Fix .gitignore CGH0S7 2024-12-23 10:16:04 +08:00
• 3ae04d1240 Initial Chisel Template CGH0S7 2024-12-23 10:14:20 +08:00
• eec6e09111 Initial commit gh0s7 2024-12-19 22:14:30 +08:00